1999 Microchip Technology Inc.
Preliminary
DS21298B-page 1
MCP3204/3208
FEATURES
• 12-bit resolution
• ± 1 LSB max DNL
• ± 1 LSB max INL (MCP3204/3208-B)
• ± 2 LSB max INL (MCP3204/3208-C)
• 4 (MCP3204) or 8 (MCP3208) input channels
• Analog inputs programmable as single-ended or
pseudo differential pairs
• On-chip sample and hold
• SPI
®
serial interface (modes 0,0 and 1,1)
• Single supply operation: 2.7V - 5.5V
• 100ksps max. sampling rate at V
DD
= 5V
• 50ksps max. sampling rate at V
DD
= 2.7V
• Low power CMOS technology
- 500 nA typical standby current, 2µA max.
- 400 µA max. active current at 5V
• Industrial temp range: -40°C to +85°C
• Available in PDIP, SOIC and TSSOP packages
APPLICATIONS
• Sensor Interface
• Process Control
• Data Acquisition
• Battery Operated Systems
DESCRIPTION
The Microchip Technology Inc. MCP3204/3208
devices are successive approximation 12-bit Ana-
log-to-Digital (A/D) Converters with on-board sample
and hold circuitry. The MCP3204 is programmable to
provide two pseudo-differential input pairs or four sin-
gle-ended inputs. The MCP3208 is programmable to
provide four pseudo-differential input pairs or eight sin-
gle-ended inputs. Differential Nonlinearity (DNL) is
specified at ±1 LSB, and Integral Nonlinearity (INL) is
offered in ±1 LSB (MCP3204/3208-B) and ±2 LSB
(MCP3204/3208-C) versions. Communication with the
devices is done using a simple serial interface compat-
ible with the SPI protocol. The devices are capable of
conversion rates of up to 100ksps. The MCP3204/3208
devices operate over a broad voltage range (2.7V -
5.5V). Low current design permits operation with typi-
cal standby and active currents of only 500nA and
320µA, respectively. The MCP3204 is offered in 14-pin
PDIP, 150mil SOIC and TSSOP packages, and the
MCP3208 is offered in 16-pin PDIP and SOIC pack-
ages.
PACKAGE TYPES
FUNCTIONAL BLOCK DIAGRAM
V
DD
CLK
D
OUT
MC
P3
204
1
2
3
4
14
13
12
11
10
9
8
5
6
7
V
REF
D
IN
CH0
CH1
CH2
CH3
CS/SHDN
DGND
AGND
NC
V
DD
CLK
D
OUT
MC
P3
208
1
2
3
4
16
15
14
13
12
11
10
9
5
6
7
8
V
REF
D
IN
CS/SHDN
DGND
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
NC
AGND
PDIP, SOIC, TSSOP
PDIP, SOIC
Comparator
Sample
and
Hold
12-Bit SAR
DAC
Control Logic
CS/SHDN
V
REF
V
SS
V
DD
CLK
D
OUT
Shift
Register
CH0
Channel
Mux
Input
CH1
CH7*
*Note: Channels 5-7 available on MCP3208 Only
D
IN
2.7V 4-Channel/8-Channel 12-Bit A/D Converters
with SPI
®
Serial Interface
MCP3204/3208
DS21298B-page 2
Preliminary
1999 Microchip Technology Inc.
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
V
DD
.........................................................................7.0V
All inputs and outputs w.r.t. V
SS
...... -0.6V to V
DD
+0.6V
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied......-65°C to +125°C
Soldering temperature of leads (10 seconds) .. +300°C
ESD protection on all pins ................................... > 4kV
*Notice: Stresses above those listed under “Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
PIN FUNCTION TABLE
NAME
FUNCTION
V
DD
DGND
AGND
CH0-CH7
CLK
D
IN
D
OUT
CS/SHDN
V
REF
+2.7V to 5.5V Power Supply
Digital Ground
Analog Ground
Analog Inputs
Serial Clock
Serial Data In
Serial Data Out
Chip Select/Shutdown Input
Reference Voltage Input
ELECTRICAL CHARACTERISTICS
All parameters apply at V
DD
= 5V, V
SS
= 0V, V
REF
= 5V, T
AMB
= -40°C to +85°C, f
SAMPLE
= 100ksps and
f
CLK
= 20*f
SAMPLE
, unless otherwise noted.
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNITS
CONDITIONS
Conversion Rate
Conversion Time
t
CONV
12
clock
cycles
Analog Input Sample Time
t
S
AMPLE
1.5
clock
cycles
Throughput Rate
f
SAMPLE
100
50
ksps
ksps
V
DD
= V
REF
= 5V
V
DD
= V
REF
= 2.7V
DC Accuracy
Resolution
12
bits
Integral Nonlinearity
INL
±0.75
±1
±1
±2
LSB
MCP3204/3208-B
MCP3204/3208-C
Differential Nonlinearity
DNL
±0.5
±1
LSB
No missing codes over
temperature
Offset Error
±1.25
±3
LSB
Gain Error
±1.25
±5
LSB
Dynamic Performance
Total Harmonic Distortion
-82
dB
V
IN
= 0.1V to 4.9V@1kHz
Signal to Noise and Distortion
(SINAD)
72
dB
V
IN
= 0.1V to 4.9V@1kHz
Spurious Free Dynamic
Range
86
dB
V
IN
= 0.1V to 4.9V@1kHz
Reference Input
Voltage Range
0.25
V
DD
V
Current Drain
100
0.001
150
3
µA
µA
CS = V
DD
= 5V
Analog Inputs
Input Voltage Range for
CH0-CH7 in Single-Ended
Mode
V
SS
V
REF
V
Input Voltage Range for IN+ In
pseudo-differential Mode
IN-
V
REF
+IN-
Input Voltage Range for IN- In
pseudo-differential Mode
V
SS
-100
V
SS
+100
mV
Leakage Current
0.001
±1
µA
1999 Microchip Technology Inc.
Preliminary
DS21298B-page 3
MCP3204/3208
Analog Inputs (Continued)
Switch Resistance
1K
Ω
Sample Capacitor
20
pF
Digital Input/Output
Data Coding Format
Straight Binary
High Level Input Voltage
V
IH
0.7 V
DD
V
Low Level Input Voltage
V
IL
0.3 V
DD
V
High Level Output Voltage
V
OH
4.1
V
I
OH
= -1mA, V
DD
= 4.5V
Low Level Output Voltage
V
OL
0.4
V
I
OL
= 1mA, V
DD
= 4.5V
Input Leakage Current
I
LI
-10
10
µA
V
IN
= V
SS
or V
DD
Output Leakage Current
I
LO
-10
10
µA
V
OUT
= V
SS
or V
DD
Pin Capacitance
(All Inputs/Outputs)
C
IN
, C
OUT
10
pF
V
DD
= 5.0V (Note 1)
T
AMB
= 25°C, f = 1 MHz
Timing Parameters
Clock Frequency
f
CLK
2.0
1.0
MHz
MHz
V
DD
V
DD
= 2.7V (Note 3)
Clock High Time
t
HI
250
ns
Clock Low Time
t
LO
250
ns
CS Fall To First Rising CLK
Edge
t
SUCS
100
ns
Data Input Setup Time
t
SU
50
ns
Data Input Hold Time
t
HD
50
ns
CLK Fall To Output Data Valid
t
DO
200
ns
See Test Circuits, Figure 1-2
CLK Fall To Output Enable
t
EN
200
ns
See Test Circuits, Figure 1-2
CS Rise To Output Disable
t
DIS
100
ns
See Test Circuits, Figure 1-2
CS Disable Time
t
CSH
500
ns
D
OUT
Rise Time
t
R
100
ns
See Test Circuits, Figure 1-2
(Note 1)
D
OUT
Fall Time
t
F
100
ns
See Test Circuits, Figure 1-2
(Note 1)
Power Requirements
Operating Voltage
V
DD
2.7
5.5
V
Operating Current
I
DD
320
225
400
µA
V
DD
= V
REF
= 5V, D
OUT
unloaded
V
DD
= V
REF
= 2.7V, D
OUT
unloaded
Standby Current
I
DDS
0.5
2
µA
CS = V
DD
= 5.0V
Note 1: This parameter is guaranteed by characterization and not 100% tested.
Note 2: See graphs that relate linearity performance to V
REF
levels.
Note 3: Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity
performance, especially at elevated temperatures. See Section 6.2 for more information.
ELECTRICAL CHARACTERISTICS (CONTINUED)
All parameters apply at V
DD
= 5V, V
SS
= 0V, V
REF
= 5V, T
AMB
= -40°C to +85°C, f
SAMPLE
= 100ksps and
f
CLK
= 20*f
SAMPLE
, unless otherwise noted.
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNITS
CONDITIONS
MCP3204/3208
DS21298B-page 4
Preliminary
1999 Microchip Technology Inc.
FIGURE 1-1:
Serial Interface Timing.
FIGURE 1-2:
Test Circuits.
CS
CLK
D
IN
MSB IN
t
SU
t
HD
t
SUCS
t
CSH
t
HI
t
LO
D
OUT
t
EN
t
DO
t
R
t
F
LSB
MSB OUT
t
DIS
NULL BIT
90%
10%
*
Waveform 1 is for an output with internal condi-
tions such that the output is high, unless dis-
abled by the output control.
† Waveform 2 is for an output with internal condi-
tions such that the output is low, unless disabled
by the output control.
Test Point
1.4V
D
OUT
Load circuit for t
R
, t
F
,
t
DO
3K
C
L
= 100pF
Test Point
D
OUT
Load circuit for t
DIS
and t
EN
3K
100pF
t
DIS
Waveform 2
t
DIS
Waveform 1
CS
CLK
D
OUT
t
EN
1
2
B11
Voltage Waveforms for t
EN
t
EN
Waveform
V
DD
V
DD
/2
V
SS
3
4
D
OUT
t
R
Voltage Waveforms for t
R
, t
F
CLK
D
OUT
t
DO
Voltage Waveforms for t
DO
t
F
V
OH
V
OL
Voltage Waveforms for t
DIS
D
OUT
D
OUT
CS
V
IH
T
DIS
Waveform 1*
Waveform 2†
1999 Microchip Technology Inc.
Preliminary
DS21298B-page 5
MCP3204/3208
2.0
TYPICAL PERFORMANCE CHARACTERISTICS
Note: Unless otherwise indicated, V
DD
= V
REF
= 5V, V
SS
= 0V, f
SAMPLE
= 100ksps, f
CLK
= 20* f
SAMPLE
,T
A
= 25°C
FIGURE 2-1:
Integral Nonlinearity (INL) vs. Sample
Rate.
FIGURE 2-2:
Integral Nonlinearity (INL) vs. V
REF
.
FIGURE 2-3:
Integral Nonlinearity (INL) vs. Code
(Representative Part).
FIGURE 2-4:
Integral Nonlinearity (INL) vs. Sample
Rate (V
DD
= 2.7V).
FIGURE 2-5:
Integral Nonlinearity (INL) vs. V
REF
(V
DD
= 2.7V).
FIGURE 2-6:
Integral Nonlinearity (INL) vs. Code
(Representative Part, V
DD
= 2.7V).
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0
25
50
75
100
125
150
Sample Rate (ksps)
IN
L (LSB)
Positive INL
Negative INL
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0
1
2
3
4
5
6
V
REF
(V)
IN
L(
LSB)
Positive INL
Negative INL
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0
512
1024
1536
2048
2560
3072
3584
4096
Digital Code
IN
L (
L
SB)
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
0
10
20
30
40
50
60
70
80
Sample Rate (ksps)
IN
L (LSB)
Positive INL
Negative INL
V
DD
= V
REF
= 2.7V
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
V
REF
(V)
IN
L(LSB)
Positive INL
Negative INL
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0
512
1024
1536
2048
2560
3072
3584
4096
Digital Code
IN
L (
L
SB)
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50ksps
MCP3204/3208
DS21298B-page 6
Preliminary
1999 Microchip Technology Inc.
Note: Unless otherwise indicated, V
DD
= V
REF
= 5V, V
SS
= 0V, f
SAMPLE
= 100ksps, f
CLK
= 20* f
SAMPLE
,T
A
= 25°C
FIGURE 2-7:
Integral Nonlinearity (INL) vs.
Temperature.
FIGURE 2-8:
Differential Nonlinearity (DNL) vs.
Sample Rate.
FIGURE 2-9:
Differential Nonlinearity (DNL) vs.
V
REF
.
FIGURE 2-10: Integral Nonlinearity (INL) vs.
Temperature (V
DD
= 2.7V).
FIGURE 2-11: Differential Nonlinearity (DNL) vs.
Sample Rate (V
DD
= 2.7V).
FIGURE 2-12: Differential Nonlinearity (DNL) vs. V
REF
(V
DD
= 2.7V)
.
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-50
-25
0
25
50
75
100
Temperature (°C)
IN
L (
L
SB)
Positive INL
Negative INL
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0
25
50
75
100
125
150
Sample Rate (ksps)
DNL (LS
B
)
Positive DNL
Negative DNL
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
0
1
2
3
4
5
V
REF
(V)
DNL
(L
S
B
)
Positive DNL
Negative DNL
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-50
-25
0
25
50
75
100
Temperature (°C)
IN
L (LSB)
Positive INL
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50ksps
Negative INL
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
0
10
20
30
40
50
60
70
Sample Rate (ksps)
DNL
(L
S
B
)
Positive DNL
Negative DNL
V
DD
= V
REF
= 2.7V
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
V
REF
(V)
DNL
(L
S
B
)
Positive DNL
Negative DNL
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50ksps
1999 Microchip Technology Inc.
Preliminary
DS21298B-page 7
MCP3204/3208
Note: Unless otherwise indicated, V
DD
= V
REF
= 5V, V
SS
= 0V, f
SAMPLE
= 100ksps, f
CLK
= 20* f
SAMPLE
,T
A
= 25°C
FIGURE 2-13: Differential Nonlinearity (DNL) vs.
Code (Representative Part).
FIGURE 2-14: Differential Nonlinearity (DNL) vs.
Temperature.
FIGURE 2-15: Gain Error vs. V
REF
.
FIGURE 2-16: Differential Nonlinearity (DNL) vs.
Code (Representative Part, V
DD
= 2.7V).
FIGURE 2-17: Differential Nonlinearity (DNL) vs.
Temperature (V
DD
= 2.7V).
FIGURE 2-18: Offset Error vs. V
REF
.
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0
512
1024
1536
2048
2560
3072
3584
4096
Digital Code
DNL
(L
S
B
)
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-50
-25
0
25
50
75
100
Temperature (°C)
DNL
(
L
S
B
)
Positive DNL
Negative DNL
-4
-3
-2
-1
0
1
2
3
4
0
1
2
3
4
5
V
REF
(V)
G
a
in Error (LSB
)
V
DD
= 2.7V
F
SAMPLE
= 50ksps
V
DD
= 5V
F
SAMPLE
= 100ksps
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0
512
1024
1536
2048
2560
3072
3584
4096
Digital Code
DNL
(L
S
B
)
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50ksps
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-50
-25
0
25
50
75
100
Temperature (°C)
DNL
(
L
S
B
)
Positive DNL
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50ksps
Negative DNL
0
2
4
6
8
10
12
14
16
18
20
0
1
2
3
4
5
V
REF
(V)
Of
fs
et
Error (LSB
)
V
DD
= 5V
F
SAMPLE
= 100ksps
V
DD
= 2.7V
F
SAMPLE
= 50ksps
MCP3204/3208
DS21298B-page 8
Preliminary
1999 Microchip Technology Inc.
Note: Unless otherwise indicated, V
DD
= V
REF
= 5V, V
SS
= 0V, f
SAMPLE
= 100ksps, f
CLK
= 20* f
SAMPLE
,T
A
= 25°C
FIGURE 2-19: Gain Error vs. Temperature.
FIGURE 2-20: Signal to Noise (SNR) vs. Input
Frequency.
FIGURE 2-21: Total Harmonic Distortion (THD) vs.
Input Frequency.
FIGURE 2-22: Offset Error vs. Temperature.
FIGURE 2-23: Signal to Noise and Distortion
(SINAD) vs. Input Frequency.
FIGURE 2-24: Signal to Noise and Distortion
(SINAD) vs. Input Signal Level.
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
-50
-25
0
25
50
75
100
Temperature (°C)
Gain Error (LSB
)
V
DD
= V
REF
= 5V
F
SAMPLE
= 100ksps
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50ksps
0
10
20
30
40
50
60
70
80
90
100
1
10
100
Input Frequency (kHz)
SNR (
d
B)
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50ksps
V
DD
= V
REF
= 5V
F
SAMPLE
= 100ksps
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
1
10
100
Input Frequency (kHz)
T
HD (d
B)
V
DD
= V
REF
= 5V
F
SAMPLE
= 100ksps
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50ksps
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-50
-25
0
25
50
75
100
Temperature (°C)
Of
fs
et
Error (LSB
)
V
DD
= V
REF
= 5V
F
SAMPLE
= 100ksps
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50ksps
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
1
10
100
Input Frequency (kHz)
S
INA
D (d
B
)
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50ksps
V
DD
= V
REF
= 5V
F
SAMPLE
= 100ksps
0
10
20
30
40
50
60
70
80
-40
-35
-30
-25
-20
-15
-10
-5
0
Input Signal Level (dB)
S
INA
D (d
B
)
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50ksps
V
DD
= V
REF
= 5V
F
SAMPLE
= 100ksps
1999 Microchip Technology Inc.
Preliminary
DS21298B-page 9
MCP3204/3208
Note: Unless otherwise indicated, V
DD
= V
REF
= 5V, V
SS
= 0V, f
SAMPLE
= 100ksps, f
CLK
= 20* f
SAMPLE
,T
A
= 25°C
FIGURE 2-25: Effective Number of Bits (ENOB) vs.
V
REF
.
FIGURE 2-26: Spurious Free Dynamic Range
(SFDR) vs. Input Frequency.
FIGURE 2-27: Frequency Spectrum of 10kHz input
(Representative Part).
FIGURE 2-28: Effective Number of Bits (ENOB) vs.
Input Frequency.
FIGURE 2-29: Power Supply Rejection (PSR) vs.
Ripple Frequency.
FIGURE 2-30: Frequency Spectrum of 1kHz input
(Representative Part, V
DD
= 2.7V).
9.00
9.25
9.50
9.75
10.00
10.25
10.50
10.75
11.00
11.25
11.50
11.75
12.00
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V
REF
(V)
E
N
O
B
(rms
)
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50ksps
V
DD
= V
REF
= 5V
F
SAMPLE
=100ksps
0
10
20
30
40
50
60
70
80
90
100
1
10
100
Input Frequency (kHz)
SFDR (
d
B)
V
DD
= V
REF
= 5V
F
SAMPLE
= 100ksps
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50ksps
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0
10000
20000
30000
40000
50000
Frequency (Hz)
Ampl
it
ude (
d
B)
V
DD
= V
REF
= 5V
F
SAMPLE
= 100ksps
F
INPUT
= 9.985kHz
4096 points
8.0
8.5
9.0
9.5
10.0
10.5
11.0
11.5
12.0
1
10
100
Input Frequency (kHz)
E
N
O
B
(rms)
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50ksps
V
DD
= V
REF
= 5V
F
SAMPLE
= 100ksps
-80
-70
-60
-50
-40
-30
-20
-10
0
1
10
100
1000
10000
Ripple Frequency (kHz)
Pow
e
r Supply
R
e
jec
tion (dB
)
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0
5000
10000
15000
20000
25000
Frequency (Hz)
Am
plit
ude (dB)
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50ksps
F
INPUT
= 998.76Hz
4096 points
MCP3204/3208
DS21298B-page 10
Preliminary
1999 Microchip Technology Inc.
Note: Unless otherwise indicated, V
DD
= V
REF
= 5V, V
SS
= 0V, f
SAMPLE
= 100ksps, f
CLK
= 20* f
SAMPLE
,T
A
= 25°C
FIGURE 2-31: I
DD
vs. V
DD
.
FIGURE 2-32: I
DD
vs. Clock Frequency.
FIGURE 2-33: I
DD
vs. Temperature.
FIGURE 2-34: I
REF
vs. V
DD
.
FIGURE 2-35: I
REF
vs. Clock Frequency.
FIGURE 2-36: I
REF
vs. Temperature.
0
50
100
150
200
250
300
350
400
450
500
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
V
DD
(V)
I
DD
(µA
)
V
REF
= V
DD
All points at F
CLK
= 2MHz except
at V
REF
= V
DD
= 2.5V, F
CLK
= 1MHz
0
50
100
150
200
250
300
350
400
10
100
1000
10000
Clock Frequency (kHz)
I
DD
(µA)
V
DD
= V
REF
= 5V
V
DD
= V
REF
= 2.7V
0
50
100
150
200
250
300
350
400
-50
-25
0
25
50
75
100
Temperature (°C)
I
DD
(µA
)
V
DD
= V
REF
= 5V
F
CLK
= 2MHz
V
DD
= V
REF
= 2.7V
F
CLK
= 1MHz
0
10
20
30
40
50
60
70
80
90
100
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
V
DD
(V)
I
RE
F
(µ
A
)
V
REF =
V
DD
All points at F
CLK
= 2MHz except
at V
REF
= V
DD
= 2.5V, F
CLK
= 1MHz
0
10
20
30
40
50
60
70
80
90
100
10
100
1000
10000
Clock Frequency (kHz)
I
RE
F
(µ
A
)
V
DD
= V
REF
= 5V
V
DD
= V
REF
= 2.7V
0
10
20
30
40
50
60
70
80
90
100
-50
-25
0
25
50
75
100
Temperature (°C)
I
RE
F
(µ
A
)
V
DD
= V
REF
= 5V
F
CLK
= 2MHz
V
DD
= V
REF
= 2.7V
F
CLK
= 1MHz
1999 Microchip Technology Inc.
Preliminary
DS21298B-page 11
MCP3204/3208
Note: Unless otherwise indicated, V
DD
= V
REF
= 5V, V
SS
= 0V, f
SAMPLE
= 100ksps, f
CLK
= 20* f
SAMPLE
,T
A
= 25°C
FIGURE 2-37: I
DDS
vs. V
DD
.
FIGURE 2-38: I
DDS
vs. Temperature.
FIGURE 2-39: Analog Input Leakage Current vs.
Temperature.
0
10
20
30
40
50
60
70
80
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
V
DD
(V)
I
DDS
(pA
)
V
REF
= CS = V
DD
0.01
0.10
1.00
10.00
100.00
-50
-25
0
25
50
75
100
Temperature (°C)
I
DDS
(n
A
)
V
DD
= V
REF
= CS = 5V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-50
-25
0
25
50
75
100
Temperature (°C)
Anal
og Input Leakage (
n
A)
V
DD
= V
REF
= 5V
F
CLK
= 2MHz
MCP3204/3208
DS21298B-page 12
Preliminary
1999 Microchip Technology Inc.
3.0
PIN DESCRIPTIONS
3.1
CH0 - CH7
Analog inputs for channels 0 - 7 respectively for the
multiplexed inputs. Each pair of channels can be pro-
grammed to be used as two independent channels in
single ended-mode or as a single pseudo-differential
input where one channel is IN+ and one channel is IN-.
See Section 4.1 and Section 5.0 for information on pro-
gramming the channel configuration.
3.2
CS/SHDN(Chip Select/Shutdown)
The CS/SHDN pin is used to initiate communication
with the device when pulled low and will end a conver-
sion and put the device in low power standby when
pulled high. The CS/SHDN pin must be pulled high
between conversions.
3.3
CLK (Serial Clock)
The SPI clock pin is used to initiate a conversion and to
clock out each bit of the conversion as it takes place.
See Section 6.2 for constraints on clock speed.
3.4
D
IN
(Serial Data Input)
The SPI port serial data input pin is used to load chan-
nel configuration data into the device.
3.5
D
OUT
(Serial Data output)
The SPI serial data output pin is used to shift out the
results of the A/D conversion. Data will always change
on the falling edge of each clock as the conversion
takes place.
3.6
AGND
Analog ground connection to internal analog circuitry.
3.7
DGND
Digital ground connection to internal digital circuitry.
4.0
DEVICE OPERATION
The MCP3204/3208 A/D Converters employ a conven-
tional SAR architecture. With this architecture, a sam-
ple is acquired on an internal sample/hold capacitor for
1.5 clock cycles starting on the fourth rising edge of the
serial clock after the start bit has been received. Follow-
ing this sample time, the device uses the collected
charge on the internal sample and hold capacitor to
produce a serial 12-bit digital output code. Conversion
rates of 100ksps are possible on the MCP3204/3208.
See Section 6.2 for information on minimum clock
rates. Communication with the device is done using a
4-wire SPI-compatible interface.
4.1
Analog Inputs
The MCP3204/3208 devices offer the choice of using
the analog input channels configured as single-ended
inputs or pseudo-differential pairs. The MCP3204 can
be configured to provide two pseudo-differential input
pairs or four single-ended inputs. the MCP3208 can be
configured to provide four pseudo-differential input
pairs or eight single-ended inputs. Configuration is
done as part of the serial command before each con-
version begins. When used in the pseudo-differential
mode, each channel pair (i.e., CH0 and CH1, CH2 and
CH3 etc.) are programmed as the IN+ and IN- inputs as
part of the command string transmitted to the device.
The IN+ input can range from IN- to (V
REF
+ IN-). The
IN- input is limited to ±100mV from the V
SS
rail. The IN-
input can be used to cancel small signal com-
mon-mode noise which is present on both the IN+ and
IN- inputs.
When operating in the pseudo-differential mode, if the
voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. If the voltage at IN+ is equal
to or greater than {[V
REF
+ (IN-)] - 1 LSB}, then the out-
put code will be FFFh. If the voltage level at IN- is more
than 1 LSB below V
SS
, then the voltage level at the IN+
input will have to go below V
SS
to see the 000h output
code. Conversely, if IN- is more than 1 LSB above V
SS
,
then the FFFh code will not be seen unless the IN+
input level goes above V
REF
level.
For the A/D Converter to meet specification, the charge
holding capacitor, (C
SAMPLE
) must be given enough time
to acquire a 12-bit accurate voltage level during the 1.5
clock cycle sampling period. The analog input model is
shown in Figure 4-1.
In this diagram it is shown that the source impedance
(R
S
) adds to the internal sampling switch (R
SS
) imped-
ance, directly affecting the time that is required to
charge the capacitor, C
SAMPLE
. Consequently, larger
source impedances increase the offset, gain, and inte-
gral linearity errors of the conversion. See Figure 4-2.
4.2
Reference Input
For each device in the family, the reference input (V
REF
)
determines the analog input voltage range. As the ref-
erence input is reduced, the LSB size is reduced
accordingly. The theoretical digital output code pro-
duced by the A/D Converter is a function of the analog
input signal and the reference input as shown below.
where:
V
IN
= analog input voltage
V
REF
= reference voltage
When using an external voltage reference device, the
system designer should always refer to the manufac-
turer’s recommendations for circuit layout. Any instabil-
ity in the operation of the reference device will have a
direct effect on the operation of the A/D Converter.
Digital Output Code = 4096 * V
IN
V
REF
1999 Microchip Technology Inc.
Preliminary
DS21298B-page 13
MCP3204/3208
FIGURE 4-1: Analog Input Model
FIGURE 4-2: Maximum Clock Frequency vs. Input
resistance (R
S
) to maintain less than a 0.1LSB
deviation in INL from nominal conditions.
C
PIN
VA
R
S
CHx
7pF
V
T
= 0.6V
V
T
= 0.6V
I
LEAKAGE
Sampling
Switch
SS
R
SS
= 1k
Ω
C
SAMPLE
= DAC capacitance
V
SS
V
DD
= 20 pF
±
1 nA
= Signal Source
= Source Impedance
= Input Channel Pad
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin
due to various junctions
= Sampling Switch
= Sampling Switch Resistor
= Sample/Hold Capacitance
VA
R
S
CHx
C
PIN
V
T
I
LEAKAGE
SS
R
SS
C
SAMPLE
Legend
0.0
0.5
1.0
1.5
2.0
2.5
100
1000
10000
Input Resistance (Ohms)
C
loc
k
F
requenc
y
(M
H
z
)
V
DD
= 5V
V
DD
= 2.7V
MCP3204/3208
DS21298B-page 14
Preliminary
1999 Microchip Technology Inc.
5.0
SERIAL COMMUNICATIONS
Communication with the MCP3204/3208 devices is
done using a standard SPI-compatible serial interface.
Initiating communication with either device is done by
bringing the CS line low. See Figure 5-1. If the device
was powered up with the CS pin low, it must be brought
high and back low to initiate communication. The first
clock received with CS low and D
IN
high will constitute
a start bit. The SGL/DIFF bit follows the start bit and will
determine if the conversion will be done using single
ended or differential input mode. The next three bits
(D0, D1 and D2) are used to select the input channel
configuration. Table 5-1 and Table 5-2 show the config-
uration bits for the MCP3204 and MCP3208, respec-
tively. The device will begin to sample the analog input
on the fourth rising edge of the clock after the start bit
has been received. The sample period will end on the
falling edge of the fifth clock following the start bit.
After the D0 bit is input, one more clock is required to
complete the sample and hold period (D
IN
is a don’t
care for this clock). On the falling edge of the next clock,
the device will output a low null bit. The next 12 clocks
will output the result of the conversion with MSB first as
shown in Figure 5-1. Data is always output from the
device on the falling edge of the clock. If all 12 data bits
have been transmitted and the device continues to
receive clocks while the CS is held low, the device will
output the conversion result LSB first as shown in
Figure 5-2. If more clocks are provided to the device
while CS is still low (after the LSB first data has been
transmitted), the device will clock out zeros indefinitely.
If necessary, it is possible to bring CS low and clock in
leading zeros on the D
IN
line before the start bit. This is
often done when dealing with microcontroller-based
SPI ports that must send 8 bits at a time. Refer to
Section 6.1 for more details on using the
MCP3204/3208 devices with hardware SPI ports.
CONTROL BIT
SELECTIONS
INPUT
CONFIGURATION
CHANNEL
SELECTION
SINGLE/
DIFF
D2*
D1
D0
1
X
0
0
single ended
CH0
1
X
0
1
single ended
CH1
1
X
1
0
single ended
CH2
1
X
1
1
single ended
CH3
0
X
0
0
differential
CH0 = IN+
CH1 = IN-
0
X
0
1
differential
CH0 = IN-
CH1 = IN+
0
X
1
0
differential
CH2 = IN+
CH3 = IN-
0
X
1
1
differential
CH2 = IN-
CH3 = IN+
*D2 is don’t care for MCP3204
TABLE 5-1:
Configuration Bits for the MCP3204.
CONTROL BIT
SELECTIONS
INPUT
CONFIGURATION
CHANNEL
SELECTION
SINGLE/
DIFF
D2
D1
D0
1
0
0
0
single ended
CH0
1
0
0
1
single ended
CH1
1
0
1
0
single ended
CH2
1
0
1
1
single ended
CH3
1
1
0
0
single ended
CH4
1
1
0
1
single ended
CH5
1
1
1
0
single ended
CH6
1
1
1
1
single ended
CH7
0
0
0
0
differential
CH0 = IN+
CH1 = IN-
0
0
0
1
differential
CH0 = IN-
CH1 = IN+
0
0
1
0
differential
CH2 = IN+
CH3 = IN-
0
0
1
1
differential
CH2 = IN-
CH3 = IN+
0
1
0
0
differential
CH4 = IN+
CH5 = IN-
0
1
0
1
differential
CH4 = IN-
CH5 = IN+
0
1
1
0
differential
CH6 = IN+
CH7 = IN-
0
1
1
1
differential
CH6 = IN-
CH7 = IN+
TABLE 5-2:
Configuration Bits for the MCP3208.
1999 Microchip Technology Inc.
Preliminary
DS21298B-page 15
MCP3204/3208
FIGURE 5-1:
Communication with the MCP3204 or MCP3208.
FIGURE 5-2:
Communication with MCP3204 or MCP3208 in LSB First Format.
CS
CLK
D
IN
D
OUT
D1
D2
D0
HI-Z
Don’t Care
Null
Bit
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0 *
HI-Z
t
SAMPLE
t
CONV
SGL/
DIFF
Start
t
CYC
t
CSH
t
CYC
D2
SGL/
DIFF
Start
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB
first data, then followed with zeros indefinitely. See Figure 5-2 below.
** t
DATA
: during this time, the bias current and the comparator power down while the reference input becomes
a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros.
t
DATA
**
t
SUCS
Null
Bit
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
CS
CLK
D
OUT
HI-Z
HI-Z
(MSB)
t
CONV
t
DATA
**
Power Down
t
SAMPLE
Start
SGL/
DIFF
D
IN
t
CYC
t
CSH
D0
D1
D2
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros
indefinitely.
** t
DATA
: During this time, the bias circuit and the comparator power down while the reference input becomes a
high impedance node, leaving the CLK running to clock out LSB first data or zeroes.
t
SUCS
Don’t Care
*
MCP3204/3208
DS21298B-page 16
Preliminary
1999 Microchip Technology Inc.
6.0
APPLICATIONS INFORMATION
6.1
Using the MCP3204/3208 with
Microcontroller (MCU) SPI Ports
With most microcontroller SPI ports, it is required to
send groups of eight bits. It is also required that the
microcontroller SPI port be configured to clock out data
on the falling edge of clock and latch data in on the rising
edge. Because communication with the MCP3204/3208
devices may not need multiples of eight clocks, it will be
necessary to provide more clocks than are required.
This is usually done by sending ‘leading zeros’ before
the start bit. As an example, Figure 6-1 and Figure 6-2
shows how the MCP3204/3208 can be interfaced to a
MCU with a hardware SPI port. Figure 6-1 depicts the
operation shown in SPI Mode 0,0 which requires that the
SCLK from the MCU idles in the ‘low’ state, while
Figure 6-2 shows the similar case of SPI Mode 1,1
where the clock idles in the ‘high’ state.
As shown in Figure 6-1, the first byte transmitted to the
A/D Converter contains five leading zeros before the
start bit. Arranging the leading zeros this way produces
the output 12 bits to fall in positions easily manipulated
by the MCU. The MSB is clocked out of the A/D Con-
verter on the falling edge of clock number 12. After the
second eight clocks have been sent to the device, the
MCUs receive buffer will contain three unknown bits
(the output is at high impedance for the first two clocks),
the null bit and the highest order four bits of the conver-
sion. After the third byte has been sent to the device, the
receive register will contain the lowest order eight bits of
the conversion results. Easier manipulation of the con-
verted data can be obtained by using this method.
Figure 6-2 shows the same thing in SPI Mode 1,1
which requires that the clock idles in the high state. As
with mode 0,0, the A/D Converter outputs data on the
falling edge of the clock and the MCU latches data from
the A/D Converter in on the rising edge of the clock.
FIGURE 6-1:
SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
FIGURE 6-2:
SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CS
SCLK
D
IN
X = Don’t Care Bits
17
18
19
20
21
22
23
24
D
OUT
NULL
BIT
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
HI-Z
MCU latches data from A/D Converter
Data is clocked out of
A/D Converter on falling edges
on rising edges of SCLK
DO
Don’t Care
SGL/
DIFF
D1
D2
Start
0
0
0
0
0
1
X
X
X
X
X
DO
X
X
X
X
X
X
X
X
B7
B6
B5
B4
B3
B2
B1
B0
B11
B10
B9
B8
0
?
?
?
?
?
?
?
?
?
?
?
D1
D2
SGL/
DIFF
Start
Bit
(Null)
MCU Transmitted Data
(Aligned with falling
edge of clock)
MCU Received Data
(Aligned with rising
edge of clock)
X
Data stored into MCU receive register
after transmission of first 8 bits
Data stored into MCU receive register
after transmission of second 8 bits
Data stored into MCU receive register
after transmission of last 8 bits
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CS
SCLK
D
IN
X = Don’t Care Bits
17
18
19
20
21
22
23
24
D
OUT
DO
Don’t Care
NULL
BIT
B11
B10
B9
B8
B6
B5
B4
B3
B2
B1
B0
HI-Z
0
0
0
0
0
1
X
X
X
X
X
DO
SGL/
DIFF
X
X
X
X
X
X
X
X
B7
B6
B5
B4
B3
B2
B1
B0
B11
B10
B9
B8
0
?
?
?
?
?
?
?
?
?
?
?
MCU latches data from A/D Converter
on rising edges of SCLK
Data is clocked out of
A/D Converter on falling edges
D1
D2
SGL/
DIFF
Start
Bit
(Null)
D1
D2
Start
MCU Transmitted Data
(Aligned with falling
edge of clock)
MCU Received Data
(Aligned with rising
edge of clock)
B7
X
Data stored into MCU receive register
after transmission of first 8 bits
Data stored into MCU receive register
after transmission of second 8 bits
Data stored into MCU receive register
after transmission of last 8 bits
1999 Microchip Technology Inc.
Preliminary
DS21298B-page 17
MCP3204/3208
6.2
Maintaining Minimum Clock Speed
When the MCP3204/3208 initiates the sample period,
charge is stored on the sample capacitor. When the
sample period is complete, the device converts one bit
for each clock that is received. It is important for the
user to note that a slow clock rate will allow charge to
bleed off the sample capacitor while the conversion is
taking place. At 85°C (worst case condition), the part
will maintain proper charge on the sample capacitor for
at least 1.2ms after the sample period has ended. This
means that the time between the end of the sample
period and the time that all 12 data bits have been
clocked out must not exceed 1.2ms (effective clock fre-
quency of 10kHz). Failure to meet this criterion may
induce linearity errors into the conversion outside the
rated specifications. It should be noted that during the
entire conversion cycle, the A/D Converter does not
require a constant clock speed or duty cycle, as long as
all timing specifications are met.
6.3
Buffering/Filtering the Analog Inputs
If the signal source for the A/D Converter is not a low
impedance source, it will have to be buffered or inaccu-
rate conversion results may occur. See Figure 4-2. It is
also recommended that a filter be used to eliminate any
signals that may be aliased back in to the conversion
results. This is illustrated in Figure 6-3 where an op
amp is used to drive the analog input of the
MCP3204/3208. This amplifier provides a low imped-
ance source for the converter input and a low pass fil-
ter, which eliminates unwanted high frequency noise.
Low pass (anti-aliasing) filters can be designed using
Microchip’s free interactive FilterLab™ software. Fil-
terLab will calculate capacitor and resistors values, as
well as determine the number of poles that are required
for the application. For more information on filtering sig-
nals, see the application note AN699
“Anti-Aliasing
Analog Filters for Data Acquisition Systems.”
FIGURE 6-3:
The MCP601 Operational Amplifier is
used to implement a 2nd order anti-aliasing filter for
the signal being converted by the MCP3204.
6.4
Layout Considerations
When laying out a printed circuit board for use with ana-
log components, care should be taken to reduce noise
wherever possible. A bypass capacitor should always
be used with this device and should be placed as close
as possible to the device pin. A bypass capacitor value
of 1µF is recommended.
Digital and analog traces should be separated as much
as possible on the board and no traces should run
underneath the device or the bypass capacitor. Extra
precautions should be taken to keep traces with high
frequency signals (such as clock lines) as far as possi-
ble from analog traces.
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing V
DD
connections to
devices in a “star” configuration can also reduce noise
by eliminating return current paths and associated
errors. See Figure 6-4. For more information on layout
tips when using A/D Converters, refer to AN688
“Lay-
out Tips for 12-Bit A/D Converter Applications”.
FIGURE 6-4:
V
DD
traces arranged in a ‘Star’
configuration in order to reduce errors caused by
current return paths.
FilterLab is a trademark of Microchip Technology Inc. in
the U.S.A and other countries. All rights reserved.
MCP3204
V
DD
10µF
IN-
IN+
-
+
V
IN
C
1
C
2
V
REF
4.096V
Reference
ADI
REF198
1µF
1µF
0.1µF
Tant.
0.1µF
MCP601
R
1
R
2
R
3
R
4
V
DD
Connection
Device 1
Device 2
Device 3
Device 4
MCP3204/3208
DS21298B-page 18
Preliminary
1999 Microchip Technology Inc.
6.5
Utilizing the Digital and Analog
Ground Pins
The MCP3204/3208 devices provide both digital and
analog ground connections to provide another means
of noise reduction. As shown in Figure 6-5, the analog
and digital circuitry is separated internal to the device.
This reduces noise from the digital portion of the device
being coupled into the analog portion of the device. The
two grounds are connected internally through the sub-
strate which has a resistance of 5 -10
Ω
.
If no ground plane is utilized, then both grounds must
be connected to V
SS
on the board. If a ground plane is
available, both digital and analog ground pins should
be connected to the analog ground plane. If both an
analog and a digital ground plane are available, both
the digital and the analog ground pins should be con-
nected to the analog ground plane. Following these
steps will reduce the amount of digital noise from the
rest of the board being coupled into the A/D Converter.
FIGURE 6-5:
Separation of Analog and Digital
Ground Pins.
V
DD
Digital Side
-SPI Interface
-Shift Register
-Control Logic
Analog Side
-Sample Cap
-Capacitor Array
-Comparator
Substrate
5 - 10
Ω
Analog
Ground Pin
Digital
Ground Pin
1999 Microchip Technology Inc.
Preliminary
DS21298B-page 19
MCP3204/3208
MCP3204 PRODUCT IDENTIFICATION SYSTEMS
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
MCP3208 PRODUCT IDENTIFICATION SYSTEMS
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
Package:
P = PDIP (14 lead)
SL = SOIC (150 mil Body), 14 lead
ST = TSSOP, 14 lead (C Grade only)
Temperature
I = –40°C to +85°C
Range:
Performance
B = ±1 LSB INL (TSSOP not available in this grade)
Grade:
C = ±2 LSB INL
Device:
MCP3204
=
4-Channel 12-Bit Serial A/D Converter
MCP3204T
=
4-Channel 12-Bit Serial A/D Converter on tape and reel
(SOIC and TSSOP packages only)
MCP3204 - G T /P
Package:
P = PDIP (16 lead)
SL = SOIC (150 mil Body), 16 lead
Temperature
I = –40°C to +85°C
Range:
Performance
B = ±1 LSB INL (TSSOP not available in this grade)
Grade:
C = ±2 LSB INL
Device:
MCP3208
=
8-Channel 12-Bit Serial A/D Converter
MCP3208T
=
8-Channel 12-Bit Serial A/D Converter on tape and reel
(SOIC packages only)
MCP3208 - G T /P
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
Your local Microchip sales office
2.
The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277. After September 1, 1999, (480) 786-7277
3.
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21298B-page 20
1999 Microchip Technology Inc.
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 8/99
Printed on recycled paper.
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08/11/99
W
ORLDWIDE
S
ALES
AND
S
ERVICE
Microchip received ISO 9001 Quality
System certification for its worldwide
headquarters, design, and wafer fabrication
facilities in January 1997. Our field-pro-
grammable PICmicro
®
8-bit MCUs,
K
EE
L
OQ
®
code hopping devices, Serial
EEPROMs, related specialty memory prod-
ucts and development systems conform to
the stringent quality standards of the Inter-
national Standard Organization (ISO).
Document Outline
- 1.0 ELECTRICAL CHARACTERISTICS
- 1.1 Maximum Ratings*
- 2.0 Typical Performance Characteristics
- FIGURE 21: Integral Nonlinearity (INL) vs. Sample Rate.
- FIGURE 22: Integral Nonlinearity (INL) vs. Vref.
- FIGURE 23: Integral Nonlinearity (INL) vs. Code (Representative Part).
- FIGURE 24: Integral Nonlinearity (INL) vs. Sample Rate (Vdd = 2.7V).
- FIGURE 25: Integral Nonlinearity (INL) vs. Vref (Vdd = 2.7V).
- FIGURE 26: Integral Nonlinearity (INL) vs. Code (Representative Part, Vdd = 2.7V).
- FIGURE 27: Integral Nonlinearity (INL) vs. Temperature.
- FIGURE 28: Differential Nonlinearity (DNL) vs. Sample Rate.
- FIGURE 29: Differential Nonlinearity (DNL) vs. Vref.
- FIGURE 210: Integral Nonlinearity (INL) vs. Temperature (Vdd = 2.7V).
- FIGURE 211: Differential Nonlinearity (DNL) vs. Sample Rate (Vdd = 2.7V).
- FIGURE 212: Differential Nonlinearity (DNL) vs. Vref (Vdd = 2.7V).
- FIGURE 213: Differential Nonlinearity (DNL) vs. Code (Representative Part).
- FIGURE 214: Differential Nonlinearity (DNL) vs. Temperature.
- FIGURE 215: Gain Error vs. Vref.
- FIGURE 216: Differential Nonlinearity (DNL) vs. Code (Representative Part, Vdd = 2.7V).
- FIGURE 217: Differential Nonlinearity (DNL) vs. Temperature (Vdd = 2.7V).
- FIGURE 218: Offset Error vs. Vref.
- FIGURE 219: Gain Error vs. Temperature.
- FIGURE 220: Signal to Noise (SNR) vs. Input Frequency.
- FIGURE 221: Total Harmonic Distortion (THD) vs. Input Frequency.
- FIGURE 222: Offset Error vs. Temperature.
- FIGURE 223: Signal to Noise and Distortion (SINAD) vs. Input Frequency.
- FIGURE 224: Signal to Noise and Distortion (SINAD) vs. Input Signal Level.
- FIGURE 225: Effective Number of Bits (ENOB) vs. Vref.
- FIGURE 226: Spurious Free Dynamic Range (SFDR) vs. Input Frequency.
- FIGURE 227: Frequency Spectrum of 10kHz input (Representative Part).
- FIGURE 228: Effective Number of Bits (ENOB) vs. Input Frequency.
- FIGURE 229: Power Supply Rejection (PSR) vs. Ripple Frequency.
- FIGURE 230: Frequency Spectrum of 1kHz input (Representative Part, Vdd = 2.7V).
- FIGURE 231: Idd vs. Vdd.
- FIGURE 232: Idd vs. Clock Frequency.
- FIGURE 233: Idd vs. Temperature.
- FIGURE 234: Iref vs. Vdd.
- FIGURE 235: Iref vs. Clock Frequency.
- FIGURE 236: Iref vs. Temperature.
- FIGURE 237: Idds vs. Vdd.
- FIGURE 238: Idds vs. Temperature.
- FIGURE 239: Analog Input Leakage Current vs. Temperature.
- 3.0 PIN DESCRIPTIONS
- 3.1 CH0 - CH7
- 3.2 CS/SHDN(Chip Select/Shutdown)
- 3.3 CLK (Serial Clock)
- 3.4 Din (Serial Data Input)
- 3.5 Dout (Serial Data output)
- 3.6 AGND
- 3.7 DGND
- 4.0 Device Operation
- 4.1 Analog Inputs
- 4.2 Reference Input
- 5.0 Serial communications
- 6.0 Applications Information
- 6.1 Using the MCP3204/3208 with Microcontroller (MCU) SPI Ports
- 6.2 Maintaining Minimum Clock Speed
- 6.3 Buffering/Filtering the Analog Inputs
- 6.4 Layout Considerations
- 6.5 Utilizing the Digital and Analog Ground Pins
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