Xilinx Design Summary counter_binary_2bit Project Status (05/28/2013 - 19:07:01) Project File: seven_seg_bright_control.xise Parser Errors: No Errors Module Name: Dmux_1_4_1bit Implementation State: Synthesized Target Device: xc6slx16-3csg324 Errors:   Product Version:ISE 14.2 Warnings:   Design Goal: Balanced Routing Results:   Design Strategy: Xilinx Default (unlocked) Timing Constraints:   Environment:   Final Timing Score:      Detailed Reports [-] Report NameStatusGenerated ErrorsWarningsInfos Synthesis Report      Translation Report      Map Report      Place and Route Report      CPLD Fitter Report (Text)      Power Report      Post-PAR Static Timing Report      Bitgen Report        Secondary Reports [-] Report NameStatusGenerated ISIM Simulator LogCurrentWt 28. maj 19:09:09 2013 Date Generated: 05/28/2013 - 19:09:50