Synthesis Log
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Function IID_IDispatch
IID_IDispatch = "{00020400-0000-0000-C000-000000000046}"
End Function
Function CLSID_Executor
CLSID_Executor = "Aldec.ExePlugIn.Generic.7"
End Function
Sub OpenPlugIn (progid, template, document, element, string)
Dim executor, command
Set executor = window.external.aldec.connector.OpenPlugIn(CLSID_Executor, IID_IDispatch)
command = "?Activate[][][][][]"
executor.ExecuteCommand command, ""
End Sub
Synthesis Log
Created on 14:18:31 12/11/15
Running XST Synthesis...
Please wait...
Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.48 s | Elapsed : 0.00 / 0.00 s
--> Parameter xsthdpdir set to e:/projekty_vhdl/plksrk88/plksrk88/synthesis/xst
CPU : 0.00 / 0.48 s | Elapsed : 0.00 / 0.00 s
-->
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
5) Advanced HDL Synthesis
5.1) HDL Synthesis Report
6) Low Level Synthesis
7) Final Report
7.1) Device utilization summary
7.2) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : plksrk88.prj
Input Format : mixed
Ignore Synthesis Constraint File : no
---- Target Parameters
Output File Name : plksrk88
Output Format : NGC
Target Device : xcv50bg256-6
---- Source Options
Top Module Name : plksrk88
Automatic FSM Extraction : yes
FSM Encoding Algorithm : Auto
Resource Sharing : yes
FSM Style : lut
RAM Extraction : yes
RAM Style : auto
ROM Extraction : yes
ROM Style : auto
Mux Extraction : yes
Mux Style : auto
Decoder Extraction : yes
Priority Encoder Extraction : yes
Shift Register Extraction : yes
Logical Shifter Extraction : yes
XOR Collapsing : yes
Multiplier Style : lut
Automatic Register Balancing : no
---- Target Options
Add IO Buffers : yes
Global Maximum Fanout : 100
Add Generic Clock Buffer(BUFG) : 4
Register Duplication : yes
Equivalent register Removal : yes
Pack IO Registers into IOBs : auto
Slice Packing : yes
---- General Options
Optimization Goal : speed
Optimization Effort : 1
Global Optimization : allclocknets
RTL Output : yes
Write Timing Constraints : no
Keep Hierarchy : no
Hierarchy Separator : _
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
Slice Utilization Ratio Delta : 5
---- Other Options
verilog2001 : yes
cross_clock_analysis : no
Read Cores : yes
tristate2logic : yes
Optimize Instantiated Primitives : no
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file e:/projekty_vhdl/plksrk88/plksrk88/synthesis/./../compile/plksrk88.vhd in Library work.
Architecture plksrk88_arch of Entity plksrk88 is up to date.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <plksrk88> (Architecture <plksrk88_arch>).
Set property "fsm_extract = yes" for signal <Sreg0>.
Set property "fsm_fftype = d" for signal <Sreg0>.
Entity <plksrk88> analyzed. Unit <plksrk88> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <plksrk88>.
Related source file is e:/projekty_vhdl/plksrk88/plksrk88/synthesis/./../compile/plksrk88.vhd.
Found finite state machine <FSM_0> for signal <Sreg0>.
-----------------------------------------------------------------------
| States | 8 |
| Transitions | 13 |
| Inputs | 1 |
| Outputs | 1 |
| Clock | clk (rising_edge) |
| Reset | rst (positive) |
| Reset type | asynchronous |
| Reset State | s1 |
| Power Up State | s1 |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Summary:
inferred 1 Finite State Machine(s).
Unit <plksrk88> synthesized.
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <Sreg0> with one-hot encoding.
Dynamic shift register inference ...
=========================================================================
HDL Synthesis Report
Macro Statistics
# FSMs : 1
# Registers : 8
1-bit register : 8
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <plksrk88> ...
Loading device for application Xst from file 'v50.nph' in environment D:/Xilinx.
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block plksrk88, actual ratio is 0.
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : plksrk88.ngr
Top Level Output File Name : plksrk88
Output Format : NGC
Optimization Goal : speed
Keep Hierarchy : no
Design Statistics
# IOs : 4
Cell Usage :
# BELS : 8
# LUT2_L : 3
# LUT3_L : 5
# FlipFlops/Latches : 8
# FDC : 7
# FDP : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 3
# IBUF : 2
# OBUF : 1
=========================================================================
Device utilization summary:
---------------------------
Selected Device : v50bg256-6
Number of Slices: 5 out of 768 0%
Number of Slice Flip Flops: 8 out of 1536 0%
Number of 4 input LUTs: 8 out of 1536 0%
Number of bonded IOBs: 3 out of 184 1%
Number of GCLKs: 1 out of 4 25%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 8 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -6
Minimum period: 3.564ns (Maximum Frequency: 280.584MHz)
Minimum input arrival time before clock: 3.780ns
Maximum output required time after clock: 7.184ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay: 3.564ns (Levels of Logic = 1)
Source: Sreg0_FFd1 (FF)
Destination: Sreg0_FFd6 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: Sreg0_FFd1 to Sreg0_FFd6
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 3 1.065 1.332 Sreg0_FFd1 (Sreg0_FFd1)
LUT3_L:I2->LO 1 0.573 0.000 Sreg0_FFd6-In1 (Sreg0_FFd6-In)
FDC:D 0.594 Sreg0_FFd6
----------------------------------------
Total 3.564ns (2.232ns logic, 1.332ns route)
(62.6% logic, 37.4% route)
-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset: 3.780ns (Levels of Logic = 2)
Source: x (PAD)
Destination: Sreg0_FFd8 (FF)
Destination Clock: clk rising
Data Path: x to Sreg0_FFd8
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 8 0.768 1.845 x_IBUF (x_IBUF)
LUT3_L:I0->LO 1 0.573 0.000 Sreg0_FFd6-In1 (Sreg0_FFd6-In)
FDC:D 0.594 Sreg0_FFd6
----------------------------------------
Total 3.780ns (1.935ns logic, 1.845ns route)
(51.2% logic, 48.8% route)
-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset: 7.184ns (Levels of Logic = 1)
Source: Sreg0_FFd1 (FF)
Destination: y (PAD)
Source Clock: clk rising
Data Path: Sreg0_FFd1 to y
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 3 1.065 1.332 Sreg0_FFd1 (Sreg0_FFd1)
OBUF:I->O 4.787 y_OBUF (y)
----------------------------------------
Total 7.184ns (5.852ns logic, 1.332ns route)
(81.5% logic, 18.5% route)
=========================================================================
CPU : 1.69 / 2.59 s | Elapsed :
1.00 / 2.00 s
-->
Total memory usage is 55416 kilobytes
Processing design ...
Writing file plksrk88.vhd completed.
Synthesis finished successfully.
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