TH-A30
SERVICE MANUAL
DVD DIGITAL THEATER SYSTEM
TH-A30
Area suffix
J ------------------- U.S.A.
C ---------------- Canada
SP-XSA30 2 SP-XA30 3
STANDBY/ON
AUDIO
TV VCR TV/VIDEO PROGRESSIVE
DISPLAY STEP TV CHANNEL
AUDIO/
FM MODE SUBTITLE TV VOLUME
VCR
DVD FM/AM AUX CONTROL
TUNER PRESET
DOWN UP
REW FF
VCR CHANNEL
TUNING
B.SEARCH F.SEARCH
ENTER
VOLUME
TOP MENU MENU RETURN MUTING
STANDBY
AUDIO/FM MODE
STANDBY/ON D I G I T A L
DSP VOLUME SOURCE
SURROUND
DVD DIGITAL THEATER SYSTEM TH-A30 D I G I T A L
RM-STHA30J
DVD THEATER SYSTEM
XV-THA30 SP-WA30
Contents
Safety precautions 1-2
Disassembly method 1-5
Importance administering
Wiring connection 1-11
point on the safety 1-3
Description of major ICs 1-12~27
Preventing static electricity 1-4
No.21128
COPYRIGHT 2002 VICTOR COMPANY OF JAPAN, LTD.
Aug. 2002
TH-A30
1. This design of this product contains special hardware and many circuits and components specially for safety
purposes. For continued protection, no changes should be made to the original design unless authorized in
writing by the manufacturer. Replacement parts must be identical to those used in the original circuits. Services
should be performed by qualified personnel only.
2. Alterations of the design or circuitry of the product should not be made. Any design alterations of the product
should not be made. Any design alterations or additions will void the manufacturer`s warranty and will further
relieve the manufacture of responsibility for personal injury or property damage resulting therefrom.
3. Many electrical and mechanical parts in the products have special safety-related characteristics. These
characteristics are often not evident from visual inspection nor can the protection afforded by them necessarily
be obtained by using replacement components rated for higher voltage, wattage, etc. Replacement parts which
have these special safety characteristics are identified in the Parts List of Service Manual. Electrical
components having such features are identified by shading on the schematics and by ( ) on the Parts List in
the Service Manual. The use of a substitute replacement which does not have the same safety characteristics
as the recommended replacement parts shown in the Parts List of Service Manual may create shock, fire, or
other hazards.
4. The leads in the products are routed and dressed with ties, clamps, tubings, barriers and the like to be
separated from live parts, high temperature parts, moving parts and/or sharp edges for the prevention of
electric shock and fire hazard. When service is required, the original lead routing and dress should be
observed, and it should be confirmed that they have been returned to normal, after re-assembling.
5. Leakage currnet check (Electrical shock hazard testing)
After re-assembling the product, always perform an isolation check on the exposed metal parts of the product
(antenna terminals, knobs, metal cabinet, screw heads, headphone jack, control shafts, etc.) to be sure the
product is safe to operate without danger of electrical shock.
Do not use a line isolation transformer during this check.
Plug the AC line cord directly into the AC outlet. Using a "Leakage Current Tester", measure the leakage
current from each exposed metal parts of the cabinet, particularly any exposed metal part having a return
path to the chassis, to a known good earth ground. Any leakage current must not exceed 0.5mA AC (r.m.s.).
Alternate check method
Plug the AC line cord directly into the AC outlet. Use an AC voltmeter having, 1,000 ohms per volt or more
sensitivity in the following manner. Connect a 1,500 10W resistor paralleled by a 0.15 F AC-type capacitor
between an exposed metal part and a known good earth ground.
AC VOLTMETER
Measure the AC voltage across the resistor with the AC
(Having 1000
ohms/volts,
voltmeter.
or more sensitivity)
Move the resistor connection to each exposed metal part,
particularly any exposed metal part having a return path to
0.15 F AC TYPE
the chassis, and meausre the AC voltage across the resistor.
Place this
Now, reverse the plug in the AC outlet and repeat each
probe on
measurement. Voltage measured any must not exceed 0.75 V
each exposed
AC (r.m.s.). This corresponds to 0.5 mA AC (r.m.s.).
1500 10W
metal part.
Good earth ground
!
1. This equipment has been designed and manufactured to meet international safety standards. Burrs formed during molding may
2. It is the legal responsibility of the repairer to ensure that these safety standards are maintained. be left over on some parts of the
3. Repairs must be made in accordance with the relevant safety standards. chassis. Therefore, pay attention to
4. It is essential that safety critical components are replaced by approved parts. such burrs in the case of
5. If mains voltage selector is provided, check setting for local voltage. preforming repair of this system.
In regard with component parts appearing on the silk-screen printed side (parts side) of the PWB diagrams, the
parts that are printed over with black such as the resistor ( ), diode ( ) and ICP ( ) or identified by the " "
mark nearby are critical for safety.
(This regulation does not correspond to J and C version.)
1-2
TH-A30
Importance administering point on the safety
Main board (Forward side)
Caution: For continued protection against risk of
fire, replace only with same type 2.5A/250V for AFU1,
160mA/250V for AFU3 .
This symbol specifies type of fast operating fuse.
Precaution: Pour eviter risques de feux, remplacez
le fusible de surete de et AFU1 comme le meme type
que 2.5A/250V, et 160mA/250V pour AFU3.
^
Ce sont des fusibles suretes qui functionnes rapide.
1-3
2.5A 250V
160mA 250V
TH-A30
Preventing static electricity
1.Grounding to prevent damage by static electricity
Electrostatic discharge (ESD), which occurs when static electricity stored in the body, fabric, etc. is discharged,
can destroy the laser diode in the traverse unit (optical pickup). Take care to prevent this when performing repairs.
2.About the earth processing for the destruction prevention by static electricity
Static electricity in the work area can destroy the optical pickup (laser diode) in devices such as CD players.
Be careful to use proper grounding in the area where repairs are being performed.
2-1 Ground the workbench
Ground the workbench by laying conductive material (such as a conductive sheet) or an iron plate over
it before placing the traverse unit (optical pickup) on it.
2-2 Ground yourself
Use an anti-static wrist strap to release any static electricity built up in your body.
(caption)
Anti-static wrist strap
Conductive material
(conductive sheet) or iron plate
3. Handling the optical pickup
1. In order to maintain quality during transport and before installation, both sides of the laser diode on the
replacement optical pickup are shorted. After replacement, return the shorted parts to their original condition.
(Refer to the text.)
2. Do not use a tester to check the condition of the laser diode in the optical pickup. The tester's internal power
source can easily destroy the laser diode.
4.Handling the traverse unit (optical pickup)
1. Do not subject the traverse unit (optical pickup) to strong shocks, as it is a sensitive, complex unit.
2. Cut off the shorted part of the flexible cable using nippers, etc. after replacing the optical pickup. For specific
details, refer to the replacement procedure in the text. Remove the anti-static pin when replacing the traverse
unit. Be careful not to take too long a time when attaching it to the connector.
3. Handle the flexible cable carefully as it may break when subjected to strong force.
4. It is not possible to adjust the semi-fixed resistor that adjusts the laser power. Do not turn it.
Attention when traverse unit is decomposed
*Please refer to "Disassembly method" in the text for pick-up and how to detach the substrate.
1. Solder is put up before the card
wire is removed from connector
DVD mechanism assembly (bottom side) (These two points are
soldered respectively,
on the pick up board as shown in
Short land
and are made to
DVD loading
Figure.
mechanism short-circuit)
(When the wire is removed
without putting up solder, the CD
pick-up assembly might destroy.)
2. Please remove solder after
Connector
connecting the card wire with
when you install picking up
Pick up board
in the substrate.
Card wire
DVD loader board
1-4
TH-A30
Top cover
Disassembly method
B
Removing the top cover (See Fig.1)
1. Remove the four screws A attaching the top cover
on both sides of the body.
2. Remove the three screws B on back of the body.
A 2
Fig.1
3. Remove the top cover from behind in the direction of
Front panel assembly
the arrow while pulling both sides outward.
CC
Removing the front panel assembly
(See Fig.2A, 2B and 3)
Claw1
Prior to performing the following procedure, remove
the top cover.
1. Remove the three screws C attaching the front panel
assembly on bottom of the body.
(bottom side)
2. Remove the two screws D attaching the front panel
assembly on both sides of the body.
Fig.2A
3. Remove the claw1, claw2 and claw3, and detach the
Claw3
front panel assembly toward the front. Front panel assembly
4. Disconnect the card wire from the connector FCW1
Claw2
(both side)
and FCW2 on the display board.
Removing the power cord (See Fig.4)
Prior to performing the following procedure, remove
D
the top cover.
(both side)
1. Disconnect the power cord from the connector
ACW1 on the main board and pull up the cord
stopper upward.
Notes : The power cord is exchangeable.
Fig.2B
FCW2 FCW1
Display board
Front panel assembly
Power cord ACW1
(Inner side)
Rear panel
Power cord
Fig.3
stopper
Fig.4
1-5
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DVD mechanism assembly
Removing the DVD mechanism assembly
DVD
(See Fig.5 and 6)
MPEG
board
Prior to performing the following procedure, remove
the top cover.
J14
1. Disconnect the card wire from the connector J14 and
J21 on the DVD MPEG board.
E
J21
2. Remove the two screws E attaching the DVD
mechanism assembly and pull up with drawing out.
3. Disconnect the harness from the connector DJ6 on
the DVD loader board.
Removing the rear panel (See Fig.7 and 8)
Prior to performing the following procedure, remove
the top cover and power cord.
1. Disconnect the harness from the connector J9 on the
Rear panel
Fig.5
DSP board.
DVD mechanism
2. Remove the two screws F, four screws G, one screw
assembly
I and five screws J attaching the each board to the
rear panel.
3. Remove the three screws K attaching the rear panel
on back of the body.
Removing the tuner pack (See Fig.7 and 8)
Prior to performing the following procedure, remove
DVD loader board
the top cover.
1. Disconnect the card wire from the connector CON01
DJ6
on the tuner pack.
Fig.6
2. Remove the two screws F attaching the tuner pack Rear panel
to the rear panel.
G
H
Fan motor
I
Removing the jack board (See Fig.7 and 8)
Prior to performing the following procedure, remove
the top cover.
1. Disconnect the card wire from the connector VW2 on
the jack board.
F
K K K
J
2. Disconnect the harness from the connector J10 on
Fig.7
the DSP board.
J10 (on the
3. Remove the four screws G attaching the jack board
DSP board
DSP board)
to the rear panel.
Removing the fan motor (See Fig.7 and 8)
CON01
Prior to performing the following procedures, remove
the top cover .
1. Disconnect the harness from the connector J9 on the
DSP board .
VW2
Rear panel
Tuner pack
J9(on the
DSP board)
Jack board
2. Removing the two screws H attaching the fan motor
on the rear panel.
Fig.8
1-6
TH-A30
J1 J3
Removing the DSP board (See Fig.9)
DSP board
Prior to performing the following procedure, remove
the top cover, front panel assembly and DVD
mechanism assembly.
J10
1. Disconnect the harness from the connector J9 and
J10 on the DSP board. J9
L
2. Disconnect the card wire from the connector J1 and
J3 on the DSP board.
3. Remove the one screw L attaching the DSP board.
4. Remove the one screw I attaching the DSP board to
the rear panel (see fig.7).
J6 J5 J7 J2
5. Pull up the DSP board from the front side upwards
Fig.9
disconnecting the connector J2, J5, J6 and J7.
Main board M
Removing the main board (See Fig.10)
Prior to performing the following procedure, remove
the top cover, front panel assembly, DVD
Heat sink1
mechanism assembly and DSP board.
ACW2
1. Disconnect the card wire from the connector CW8 on CW8
M
the main board.
Heat sink2
2. Disconnect the harness from the connector ACW2, ACW3
M
ACW3, ACW4 and ACW5 on the main board.
M
3. Remove the five screws J attaching the speaker
terminals and jack to the rear panel (see fig.7).
ACW5
Heat sink3
4. Remove the ten screws M attaching the main board.
ACW4
Fig.10
5. When the rear panel is not removed, pull up the
main board from front side.
Solder part 1
Main board
(Each power transistor is fixed)
(Reverse side )
Removing the power transistor & power IC
(See Fig.10 to 12)
Prior to performing the following procedure, remove
the top cover, front panel assembly, DVD
mechanism assembly, DSP board and main board.
1. After removing the solder part 1 soldered to the main
board, remove each screw and remove the heat sink
from the power transistor.
2. After removing the solder part 2 soldered to the main
Solder part 3
board, remove each screw and remove the heat sink
(Power IC is fixed)
Solder part 2
from the power IC.
(Power IC is fixed)
Fig.11
1-7
(Rear panel side)
(Front panel side)
TH-A30
Heat sink 3
3. The power ICs fixed to the heat sink 3 can be
(to which power
removed individually that it is easy to remove
IC is attached)
screws (in meaning that a screw driver arrives). It is
Screws
not necessary to remove whole like above-
mentioned 1. and 2. .
After removing each screw which is fixing each
Heat sink 2
power IC to the heat sink 3, the solder part 3 to
(to which power
which it corresponds on the main board is removed.
IC is attached)
Heat sink 1
(to which power
In addition, probably, the way after removing the
transistor is attached)
whole will be safe when a screw driver does not
Fig.12
arrive too.
Removing the power transformer
ACW4 ACW3
(See Fig.13)
Prior to performing the following procedure, remove
the top cover.
ACW5
Tie band
1.
Cut off the tie band fixing the harness, if needed.
2.
Disconnect the harness from the connector ACW2
(see fig.10), ACW3, ACW4 and ACW5 on the main
board.
Power
transformer
3.
Remove the four screws N attaching the power
transformer.
N
Fig.13
Front panel assembly

Display board
(inner side)
Removing the display board & switch
Switch board
FCW2 FCW1
board (See Fig.1 and 2)
Prior to performing the following procedure, remove
the top cover and the front panel assembly.
1. Disconnect the card wire from the connector FCW1
FW2
and FCW2 on the display board.
A B
Fig.1
2. Remove the five screws A attaching the display
Front panel assembly
board on the inner of the front panel assembly.
(inner side)
Switch button
3. Remove the four screws B attaching the switch
board on the inner of the front panel assembly.
CC C
4. Disconnect the harness from connector FW2 on the
display board, if needed.
Removing the front window
(See Fig.2 and 3)
Claw
Prior to performing the following procedure, remove
Fig.2
the top cover, front panel assembly, display board
and switch board.
Front panel assembly
(front side)
1. Remove the switch buttons, if needed.
2. Remove the three screws C attaching the front
window on the front panel.
Front window
3. Remove the eight claws fixing the front window on
Fig.3
the front panel.
1-8
TH-A30
DVD mechanism assembly

(top side)
Removing the DVD loader board
(See Fig.1 to 3)
Prior to performing the following procedure, remove
the top cover and DVD mechanism assembly.
1. Disconnect the card wire from the connector J6 on
DVD MPEG board
the DVD MPEG board.
J6
2. Disconnect the harness from the connector on the
Fig.1
motor board.
DVD mechanism assembly
3. Disconnect the harness from the connector MJ5 on DVD loader board (bottom side)
the DVD loader board.
Motor board
4. Remove the four screws A attaching the DVD loader
board to DVD mechanism assembly.
A
CAUTION!! (see fig.3)
Before removing the card wire which
connects the pickup board and DVD loader
board, solder the two soldering parts and
RCN1
MJ5
Connector
make it short-circuit.
Fig.2
Moreover, while having removed the card
wire, don't remove these solder.
5. Disconnect the card wire from the connector RCN1
Pick up
on the DVD loader board. Soldering parts
Motor board
board
ONE POINT
How to eject the DVD tray manually
(see fig.2)
The white lever of the mark is moved in
the direction of the arrow. Then, the tray will
DVD loading
be opened.
mechanism
Moreover, the tray is separable from a DVD
mechanism assembly by removing two
screws of the mark (see fig.1) and drawing
out the tray.
Fig.3
Removing the DVD loading mechanism
DVD mechanism assembly
B
(bottom side)
(See Fig.4)
Bracket
Prior to performing the following procedure, remove
X
the top cover, DVD mechanism assembly and DVD
loader board.
Lever
1. Remove the two screws B and remove the bracket.
DVD loading
2. Remove the one screw C fixing the DVD loading
mechanism
mechanism.
3. Move the lever in the direction of the arrow X.
Y
4. Remove the DVD loading mechanism from the DVD
mechanism assembly by moving it in the direction of C
the arrow Y.
Fig.4
1-9
TH-A30
DVD loading mechanism
(top side)
Removing the DVD traverse mechanism
(See Fig.5)
Prior to performing the following procedure, remove
DVD traverse
the top cover, DVD mechanism assembly, DVD
mechanism
loader board and DVD loading mechanism.
1. Remove the four screws D attaching the DVD
D D
traverse mechanism to DVD loading mechanism.
Fig.5
Removing the holder & DVD MPEG board
(See Fig.6 and 7)
Holder
Prior to performing the following procedure, remove
the top cover, DVD mechanism assembly and DVD
loader board.
1. Remove the two claws1, and remove the holder from
Claw1
the DVD mechanism assembly as it is pushed down.
Note: When removing only the DVD MPEG board, it is not
necessary to remove this holder.
2. Remove the four claws2 and remove the DVD
MPEG board from the holder.
DVD mechanism assembly
(bottom side)
Fig.6
Holder
DVD MPEG board
Claw2
Fig.7
ONE POINT
DVD MPEG board
When inserting DVD MPEG board in
Holder
holder. (see fig.8)
Insert in after uniting with a lower claws,
when inserting DVD MPEG board in holder.
< Speaker section >
It is exchange in a unit.
Fig.8
Please do not decompose.
1-10
TH-A30
Color codes are shown below.
Wiring connection 1 Brown
6 Blue
2 Red
7 Violet
3809-001305
3 Orange
8 Gray
4 Yellow
9 White
5 Green
0 Black
DSP BOARD
3809-001334
1-11
CON01
TUNER PACK
DVD MPEG
J6
BOARD
DJ3
J14
J21
DVD LOADER BOARD
RCN1
JACK BOARD (V-OUT)
VW2
3809-001274
3809-001234
MJ5
DJ6
0
MJ4
J10-1
9
4
0
0
9
0
2
0
9
0
9
0
0
9
2
0
2
4
0
J3
J1
J8
J10
J9
SWITCH BOARD
J2
J7
J5
J6
0
9
FW3
AFU1
ACW1
3809-001335
CW8
ACW2
0
9
3
0
4
AFU3
FCW1-1
PT1
FW2
FCW1
9
0
DISPLAY BOARD
PW4
3
0
PW3
CW7
3
2
2
3
CW6
CW5
4
4
0
4
FCW2
3 2 2 3
4 0 4
MAIN BOARD
POWER TRANCE
ACW4
2
0
9
ACW3
1
6
0
6
ACW5
9
1
2
TH-A30
Description of major ICs
ZiVA-5 (U8) : DVD controller
1. Pin layout
157 VDD_3.3
DAI-DATA 104
158 VSS
DAI-BCK/SYSCLKBP 103
159 MDATA31
DAI-LRCK/IEC958BP 102
160 MDATA30
I2C_CL 101
161 MDATA29
I2C_DA 100
162 MDATA28
RTS1 99
163 VDD_3.3
RXD1 98
164 MDQM3
TXD1 97
165 VSS
CTS1 96
166 MDATA27
VSS 95
167 MDATA26
VDD_3.3 94
168 MDATA25
SD-DATA7 93
169 MDATA24
SD-DATA6 92
170 MDATA23
SD-DATA5 91
171 MDATA22
SD-DATA4 90
172 MDATA21
VSS 89
173 MDATA20
VDDC 88
174 VDD_3.3
SD-DATA3 87
175 MDQM2
SD-DATA2 86
176 VSS
SD-DATA1 85
177 MDATA19
SD-DATA0 84
178 MDATA18
SD-REQ 83
179 MDATA17
SD-EN 82
180 MDATA16
VSS 81
181 VDDC
VDD_3.3 80
182 VSS
SD-ERROR 79
183 MDATA15
SD-CLK 78
184 MDATA14
VSYNC/HIRQ1 77
185 MDATA13
RTS2/SPI_CLK 76
186 MDATA12
RXD2/SPI_MISO 75
187 VDD_3.3
TXD2/SPI_MOSI 74
188 MDQM1
CTS2/SPI_CS 73
189 VSS
VDD_5 72
190 MDATA11
HCS4 71
191 MDATA10
HCS3 70
192 MDATA9
HCS2 69
193 MDATA8
HCS1 68
194 MDATA7
HCS0 67
195 MDATA6
VSS 66
196 MDATA5
VDD_3.3 65
197 MDATA4
TRST 64
198 VDD_3.3
TDO 63
199 MDQM0
TDI 62
200 VSS
TMS 61
201 MDATA3
TCK 60
202 MDATA2
RESET 59
203 MDATA1
ALE 58
204 MDATA0
VSS 57
205 MCLK
VDDC 56
206 VDD_3.3
HAD3 55
207 VSS
HAD2 54
208 MWE
VSS 53
2. Pin function (1/4)
1
Description
Name Pin No. Type
Active Low Reset. Assert for at least 5-milliseconds in the presence of
RESET 202 I
clock to reset the entire chip.
Video clock that outputs 27 MHz.
VCLK 105 I/O
Crystal output. When the internal DCXO is used, a 13.5 MHz crystal
XOUT 138 O
should be con-nected between this pin and the XIN pin.
Crystal input. When the internal DCXO is used, a 13.5 MHz crystal should
XIN/bypass clk_216 139 I
be con-nected between this pin and the XOUT pin. When an external
oscillator or VCXO is used, its output should be connected to this pin.
When configured for an external bypass clock, a 216 MHz clock should be
connected to this pin. The frequency of an external VCXO can be either 27
or 13.5 MHz.
1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor.
1-12
DA-IEC958
DA-DATA3
DA-DATA2
VSS
VDD_3.3
DA-DATA1
DA-DATA0
DA-BCK
DA-LRCK
DA-XCK
VSS
VDDC
A_VSS1
A_VDD1
A_VDD2
A_VSS2
XVDD
XTAL/VCLK216BP
XTAL
XVSS
VSS_RREF
VDAC_RREF
VDD_RREF
VDAC_DVDD
VDAC_DVSS
VDAC_0
VDAC_VDD0
VDAC_0B
VDAC_1
VDAC_VDD1
VDAC_1B
VDAC_2
VDAC_VDD2
VDAC_2B
VDAC_3
VDAC_VDD3
VDAC_3B
VDAC_4
VDAC_VDD4
VDAC_4B
HSYNC/IRQ2
VDATA0
VDATA1
VDATA2
VSS
VDD_3.3
VDATA3
VDATA4
VDATA5
VDATA6
VDATA7
VCLK
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
BA1
47
BA0
48
R/W
27
HA1
2
VSS
13
VSS
21
VSS
29
VSS
31
VSS
43
HAD9
9
HAD8
10
HAD7
11
HAD6
14
HAD5
15
HAD4
16
HAD3
17
HAD2
18
HAD1
19
HAD0
22
VDDC
30
MCS0
49
MCS1
50
MRAS
51
MCAS
52
IRRX1
28
HIRQ0
24
HAD15
3
HAD14
4
HAD13
5
HAD12
6
HAD11
7
HAD10
8
VDD_3.3
1
VDD_3.3
12
VDD_3.3
20
VDD_3.3
32
VDD_3.3
44
MADDR9
33
MADDR8
34
MADDR7
35
MADDR6
36
MADDR5
37
MADDR4
38
MADDR3
39
MADDR2
40
MADDR1
41
MADDR0
42
LDS/LWE
26
UDS/UWE
25
MADDR10
45
MADDR11
46
HDTACK/WAIT
23
System Services
TH-A30
2. Pin function (2/4)
Name Pin No. Type1 Description
VNW 189 Power 5-V supply voltage for 5V-tolerant I/O signals.
VDDP 12, 20, 111, 152, 167, 181, 196 Power 3.3-V supply voltage for I/O signals
VDD25 32, 44, 55, 63, 74, 87, 98, 104 Power 3.3-V supply voltage for SDRAM I/O signals
XVDD 140 Power 3.3V Crystal interface power
VDD 30, 80, 145, 173, 205 Power 1.8-V supply voltage for core logic
VDD_VDAC[4:0] 118, 121, 124, 127, 130 Power Analog Video DAC Power
VDAC_DVDD 133 3.3V Digital supply for 5 DACs
A_VDD[2:1] 142, 143 3.3-V Analog PLL Power
VDAC_REFVDD 134 Power 3.3V Analog Video Reference Voltage
GNDP 13, 21, 112, 153, 166, 180, 195, 208 Ground Ground for I/O signals
GND 29, 79, 146, 172, 204 Ground Ground for core logic
GND25 31, 43, 54, 61, 72, 85, 96, 103 Ground Ground for SDRAM I/O signals
VDAC_DVSS 132 Ground Digital VSS for DACs
AVSS[2:1] 141, 144 Ground Analog PLL Ground
VDAC_REFVSS 136 Ground Video Analog Ground
XVSS 137 Ground Crystal interface ground
HCS[4:2]/GPIO[41:43] 190-192 O Host chip select. Host asserts HCS to select the controller for a read or
write operation. The falling edge of this signal triggers the read or write
operation. General Purpose I/Os 41, 42, and 43, respectively.
HCS[1:0] 193, 192 I Host chip select. Host asserts HCS to select the controller for a read or
write operation. The falling edge of this signal triggers the read or write
operation.
HA[3:1] 206, 207, 2 I/O Host (muxed address) address bus. 3-bit address bus selects one of eight
host inter-face registers. These signals are not muxed in ATAPI master
mode.
HA[15:0] 3-11, 14-19, 22 I/O HA[15:0] is the 16-bit (muxed address and data) bi-directional host data
bus through which the host writes data to the decoder Code FIFO. MSB of
the 32-bit word is writ-ten first. The host also reads and writes the decoder
internal registers and local SDRAM/ROM via HA[7:0]. These signals are
not muxed for ATAPI master mode.
HDTACK/WAIT 23 I/OD Host Data Transfer Acknowledge.
HIRQ0 24 I/O Host interrupt. Open drain signal, must be pulled-up via 4.7k to 3.3 volts.
Driven high for 10 ns before tristate.
HUDS/UWE 25 I/O Host Upper Data Strobe. Host high byte data, HA[15:8], is valid when this
pin is active.
HLDS/LWE 26 I/O Host Lower Data Strobe. Host low byte data, HA[7:0], is valid when this pin
is active.
HREAD 27 I/O Read/write strobe
ALE 203 I/O Address latch enable
MCS[1:0] 50, 49 O Memory chip select.
MCAS 52 O Active LOW SDRAM Column Address Strobe.
MRAS 51 O Active LOW SDRAM Row Address Strobe.
MDQM[3:0] 97, 86, 73, 62 O These pins are the bytes masks corresponding to MD[7:0], [15:8], [23:16]
and [31:24]. They allow for byte reads/writes to SDRAM.
MA[11:0] 46, 45, 33-42 O SDRAM Address
MD[31:0] 102-99, 95-88, 84-81, I/O SDRAM Data
78-75, 71-64, 60-57
MWE 53 O SDRAM Write Enable. Specifies transaction to SDRAM: read (=1) or
write (=0)
MCLK 56 O SDRAM Clock
BA[1:0] 47, 48 O SDRAM bank select
HSYNC/HIRQ2/ 116 I/O Horizontal sync. The decoder begins outputting pixel data for a new
GPIO1[9] horizontal line after the falling (active) edge of HSYNC.
Host Interrupt Request 2
General Purpose I/O 9
VCLK 105 I/O Video clock. Clocks out data on input. VDATA[7:0].
Clock is typically 27 MHz.
VDATA[7:0]/GPIO[1:7] 106-110, 113-115 I/O Video data bus. Byte serial CbYCrY data synchronous with VCLK. At
powerup, the decoder does not drive VDATA. During boot-up, the
decoder uses configuration parameters to drive or 3-state VDATA.
General Purpose I/Os [1:7]
VSYNC/HIRQ1/ 184 I/O Vertical sync. Bi-directional, the decoder outputs the top border of a new
GPIO36 field on the first HSYNC after the falling edge of VSYNC. VSYNC can
accept vertical synchroni-zation or top/bottom field notification from an
external source. (VSYNC HIGH = bot-tom field. VSYNC LOW = Top field)
Active Low Host Interrupt Pin
General Purpose I/O 36
1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor.
1-13
Power and Ground
Host Interface
SDRAM Interface
Digital Video Input/Output
TH-A30
2. Pin function (3/4)
1
Name Pin No. Type Description
SDDATA[7]/VDATA2[7] 168 I Compressed data from DVD DSP. Bit 7. In parallel mode, bit 7 is the first
/HDMARQ/GPIO24 (earliest in time) bit in the bitstream, while bit 0 is the last bit.
Video Data Bus 2, Bit 7
Host DMA Request
General Purpose I/O 24
SDDATA6/VDATA2[6] 169 Compressed data from DVD DSP. Bit 6.
/HXCVR_EN/GPIO25 Video Data Bus 2, Bit 6
ATAPI Transceiver Enable
General Purpose I/O 25
SDDATA5/VDATA2[5] 170 Compressed data from DVD DSP. Bit 5.
HDMACK/GPIO26 Video Data Bus 2, Bit 5
Host DMA Acknowledge
General Purpose I/O 26
SDDATA4/VDATA2[4]/ 171 Compressed data from DVD DSP. Bit 4.
GPIO27 Video Data Bus 2, Bit 4
General Purpose I/O 27
SDDATA3/ 174 Compressed data from DVD DSP. Bit 3.
VDATA2[3]/GPIO28 Video Data Bus 2, Bit 3
General Purpose I/O 28
SDDATA2/ 175 Compressed data from DVD DSP. Bit 2.
VDATA2[2]/GPIO29 Video Data Bus 2, Bit 2
General Purpose I/O 29
SDDATA1/ 176 Compressed data from DVD DSP. Bit 1.
VDATA2[1]/GPIO30 Video Data Bus 2, Bit 1
General Purpose I/O 30
SDDATA0/ 177 In serial mode, bit 0 should be used as the input, with the unused bits
VDATA2[0]/GPIO31 either used as GPIOs or tied to ground.
Video Data Bus 2, Bit 0
General Purpose I/O 31
SDCLK 183 I Data clock. The maximum frequency is 25 MHz for parallel mode, and
???? MHz for serial mode. The polarity of this signal is programmable.
SDERROR 182 I Error in input data. This signal carries the error bit associated with the
channel data type (if set, the byte is corrupted).
SDEN/GPIO33 179 I Data enable. Assertion indicates that data on SDDATA[7:0] is valid.
The polarity of this signal is programmable.
General Purpose I/O [33]
SDREQ/GPIO32 178 O Bitstream request. controller asserts SDREQ to indicate that the bitstream
input buffer has available space.
General Purpose I/O 32
VDAC_[4B:0B] 117, 120, 123, 126, 129 Analog O Video DAC Bias Bits[4:0]
VDAC_4 119 Analog O DAC video output format: R, V, C, or CVBS. Macrovision encoded.
VDAC_3V 122 Analog O DAC video output format: B, U, C, or CVBS. Macrovision encoded.
DAC_2 125 Analog O DAC video output format: G or Y. Macrovision encoded.
VDAC_1 128 Analog O DAC video output format: C. Macrovision encoded.
VDAC_0 131 Analog O DAC video output format: CVBS or Y. Macrovision encoded.
VDAC_REF 135 Analog I Video DACs Reference Resistor. Connecting to pin 136 through
a 1.18K+/- 1% resis-tor is required.
VCLK 105 I/O System clock that drives internal PLLs. ZiVA-5 27-MHz TTL oscillator.
(See descrip-tion of VCLK for Digital Video Output.) Also optional video
clock for internal PLLs or external encoder.
ADATA[3:0]/GPIO[4:1] 155, 154, 151, 150 O PCM Data Out. Eight channels. Serial audio samples relative to BCK
and LRCK. General Purpose I/Os [4:1]
BCK 149 O PCM Bit Clock. BCK can be either 48 or 32 times the sampling frequency
LRCK PCM Left Clock. Identifies the channel for each sample. The polarity is
148 O programma-ble.
XCK 147 I/O Audio External Frequency clock input or output. BCK and LRCK are
derived from this clock.
IEC958/GPIO14 156 O PCM data out (IEC-958 format ) or compressed data out
(IEC-1937 format). General Purpose I/O [14]
DAI_DATA/GPIO15 157 I PCM data input.
General Purpose I/O [15]
DAI_BCK/ 158 I PCM input bit clock.
BYPASS_SYSCLK/ BYPASS_SYSCLK: Alternate function TBS.
GPIO16 General Purpose I/O [16]
DAI_LRCK/ 159 I PCM left/right clock.
IEC958BP/GPIO17 IEC958 input bypass
General Purpose I/O [17]
1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor.
1-14
Parallel DVD/CD or Serial CD Interface
Digital Mic In
Audio Interface
Analog Video Output
TH-A30
2. Pin function (4/4)
1
Name Pin No. Type Description
IRRX1/GPIO0 28 I IR Remote Receive. This input connects to an integrated (photo diode,
band pass, demodulator) IR receiver. General Purpose I/O 0
IDC_CL/GPIO18 160 I/O Serial clock signal for IDC data transfer. It should be pulled up to the
positive supply voltage, depending on the device) using an external
pull-up resistor. General Purpose I/O [18]
IDC_DA/GPIO19 161 Serial data signal for IDC data transfer. It should be pulled up to the supply
voltage using an external pull-up resistor. General Purpose I/O [19]
RTS1/GPIO20 162 O Ready to send, UART1
General Purpose I/O [20]
RXD1/GPIO21 163 I Receive data, UART1
General Purpose I/O [21]
TXD1/GPIO22 164 O Transmit data, UART1
General Purpose I/O [22]
CTS1/GPIO23 165 I Clear to send, UART1
General Purpose I/O [23]
RTS2/SPI_CLK/ 185 O Ready to send, UART2
GPIO37 Serial Peripheral Interface Clock
General Purpose I/O [37]
RXD2/SPI_MISO/ 186 I Receive data, UART2
GPIO38 Serial Peripheral Interface - Master Input/Slave Output
General Purpose I/O [38]
TXD2/SPI_MOSI/ 187 O Transmit data, UART2
GPIO39 Serial Peripheral Interface - Master Output/Slave Input
General Purpose I/O [39]
CTS2/SPI_CS/ 188 I Clear to send, UART2
GPIO40 Serial Peripheral Interface ????
General Purpose I/O [40]
TRST 197 I Test reset. BST reset - resets the TAP controller.
This signal must be pulled low.
TDO 198 O Test data Out. BST serial data output.
TDI/GPI0 199 I Test data In. BST serial data chain input.
General Purpose Input pin 0.
TMS/GPI1 200 I Test mode select. Controls state of test access port (TAP) controller.
General Purpose Input pin 1.
TCK 201 I Test clock. Boundary scan test (BST) serial data clock.
1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor.
3. Block diagram
32-128Mbit
SDRAM
SDRAM Controller
CCIR 656
Parallel/serial Track Buffer
Digital Video
Decryption
Interlaced/
DVD Interface Processor
Composite
Graphics
Progressive
Five 10-bit
Y/R
Engine
Video
ZiVA
Video
C
Audio Encoder
A/V Core
DACs
I2S Stereo In Cr/Pr/G
Input Unit
Cb/Pb/B
System Control Bus
SPARC IEC 958/1937
Audio
Microprocessor
Downmix
Output
Left/right
Unit Center/subwoofer
Bus Interface Unit
Left/ right/surround
Phase
Lock
ASYNC BUS IR GPIO SPI UART1&2 ATAPI IDC JTAG Interface
Loop
Remote Control
13.5 MHz Crystal
1-15
IR
IDC
UART1
UART2
JTAG
TH-A30
LC86P6548 (UIC1) : Microcontroller
1.Pin layout
81
S48/PG0 50 S19/PC3
82
S49/PG1 49 S18/PC2
83
S50/PG2 48 S17/PC1
84
S51/PG3 47 S16/PC0
85
P00 46 VDD3
86
P01 45 S15/T15
87
P02 44 S14/T14
88
P03 43 S13/T13
89
VSS2 42 S12/T12
90
VDD2 41 S11/T11
91
P04 40 S10/T10
92
P05 39 S9/T9
93
P06 38 S8/T8
94
P07 37 S7/T7
95
P10/SO0 36 S6/T6
96
P11/SI0/SB0 35 S5/T5
97
P12/SCK0 34 S4/T4
98
P13/SO1 33 S3/T3
99
P14/SI1/SB1 32 S2/T2
100
P15/SCK1 31 S1/T1
2.Block diagram
Interrupt Control
IR PLA
A15-A0
Standby Control D7-D0
PROM
TA
Control CE
OE
DASEC
CF
PROM(48KB)
RC
X tal
PC
BaseTimer
Bus Interface ACC
SIO0 Port 1 B Register
SIO1 Port 3 C Register
Timer 0 Port 7
ALU
Timer 1 Port 8
ADC PSW
INT0-3
RAR
Noise Filter
SIO Automatic
RAM
transmission
Stack Poi nter
RAM
128 by
tes
Port 0
VFD
Controller
Watchdog Timer
High voltage Output
1-16
S47/PF7
S46/PF6
S45/PF5
S44/PF4
S43/PF3
S42/PF2
S41/PF1
S40/PF0
VDD4
S39/PE7
S38/PE6
S37/PE5
S36/PE4
S35/PE3
S34/PE2
S33/PE1
S32/PE0
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
S25/PD1
S24/PD0
S23/PC7
S22/PC6
S21/PC5
S20/PC4
VP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P30
3
P31
4
P32
5
P33
6
P34
7
P35
8
P36
9
P37
10
CF1
16
CF2
17
RES
12
VSS1
15
VDD1
18
S0/T0
30
XT1/P74
13
XT2/P75
14
P80/AN0
19
P81/AN1
20
P82/AN2
21
P83/AN3
22
P84/AN4
23
P85/AN5
24
P86/AN6
25
P87/AN7
26
P16/BUZ
1
P70/INT0
11
P71/INT1
27
P17/PWM0
2
P72/INT2/T0I
28
P72/INT3/T0I
29
Clock
Generator
TH-A30
3. Pin function
Pin No. Symbol I/O Function
1 P16/BUZ I/O Buzzer output
2 P17/PWM0 I/O Timer 1 output (PWM0 output)
3 P30 I/O 8bit input/output port
to to Input/output in bit unit
10 P37 15V withstand at N-channel open drain output
11 P70/INT0 I/O INT0 input /HOLD release/N-channel Tr. ouptput forwatchdog timer
12 RES I Reset pin
13 XT1/P74 I 32.768kHz crystal oscillation terminal XT1
14 XT2/P75 I 32.768kHz crystal oscillation terminal XT2
15 VSS1 - Power pin (-)
16 CF1 I Input pin for the ceramic resonator oscillation
17 CF2 O Output pin for the ceramic resonator oscillation
18 VDD1 - Power pin (+)
19 P80/AN0 I 4-bit input port
to to Input /output in bit unit
22 P83/AN3
23 P84/AN4 O
to to
26 P87/AN7
27 P71/INT1 I INT1 input/HOLD release input
28 P72/INT2/T0I I INT2 input/timer 0 event input
29 P72/INT3/T0I
30 S0/T0 O Output for VFD display controller segment/timing incommon
to to
36 S6/T6
37 S7/T7 O Output for VFD dis;lay controller segment/timing withinternal pull-down
to to resistor in common
45 S15/T15 Internal pull-down resistor output
46 VDD3 - Power pin (+)
47 S16/PC0 I/O Output for VFD display controller
to to High voltage input port PC0 to PC3
50 P19/PC3
51 VP - Power pin (+) for the VFD output pull-down resist
52 S20/PC4 I/O Output for VFD display controller
to to High voltage input port PC4 to PC7, PD0 to PD7
63 S31/PD7
64 S32/PE0 I/O Output for VFD displaya controller segment
to to High voltage input port PE0 to PE7
71 S39/PE7
72 VDD4 - Power pin (+)
73 S40/PF0 I/O Output for VFD displaya controller segment
to to High voltage input port PF0 to PF7
80 S47/PF7
81 S48/PG0 I/O Output for VFD displaya controller segment
to to High voltage I/O port PG0 to PG3
84 S51/PG3
85 P00 I/O 8-bit input/output port. Input for port0 interrupt.
86 P01 Input/output in nibble unit
87 P02 Input for HOLD release
88 P03 15V withstand at N-channel open drain output
89 VSS2 - Power pin (-)
90 VDD2 - Power pin (+)
91 P04 I/O 8-bit input/output port. Input for port0 interrupt.
92 P05 Input/output in nibble unit
93 P06 Input for HOLD release
94 P07 15V withstand at N-channel open drain output
95 P10/SO0 I/O SIO0 data output
8-bit input/output port
96 P11/SI0/SB0 SIO0 data input/bus input/output
Input/output can be specified in a bit unit
97 P12/SCK0 SIO0 clock input/output
98 P13/SO1 SIO1 data output
99 P14/SI1/SB1 SIO1 data input/bus input/output
100 P15/SCK1 SIO1 clock input/output
1-17
TH-A30
BA5954 (MU9) : Motor driver
1. Block diagram
28 27 26 25 24 23 22 21 20 19 18 17 16 15
10k
PreGND PVCC2 PGND
7.5k
STAND
+ - 10k 15k
-BY
20k
LOADING ACTUATOR
-
DRIVER DRIVER
2
+
7.5k
DET.AMP.
+ -
THERMAL
SHUT DOWN
PVCC1
PVCC2
VCC
DET.AMP.
+ -
7.5k
2
+
SLED ACTUATOR
-
DRIVER DRIVER
20k 10k 25k
+ -
7.5k
+ - VCC PVCC1 PGND
10k
1 2 3 4 5 6 7 8 9 10 11 12 13 14
2. Pin function
Pin No. Symbol Function
1 VINFC Focus driver input
2 CFCerr1 Capacitor connection terminal for error amplifier filter
3 CFCerr2 Capacitor connection terminal for error amplifier filter
4 VinSL + Operational amplifier input for thread driver (+)
5 VinSL - Operational amplifier input for thread driver (-)
6 VOSL Operational amplifier output for thread driver
7 VNFFC Focal driver return terminal
8 VCC Pre VCC, thread driver part power VCC
9 PVcc1 Power
10 PGND Loading driver part power VCC
11 VOSL - Thread driver part output (-)
12 VOSL + Thread driver part output (+)
13 VOFC - Focus driver part output (-)
14 VOFC + Focus driver part output (+)
15 VOTK + Tracking driver output (+)
16 VOTK - Tracking driver output (-)
17 VOLD + Loading driver output (+)
18 VOLD - Loading driver output (-)
19 PGND Power GND
20 VNFTK Tracking driver return terminal
21 PVcc2 Actuator driver part power VCC
22 PreGND Pre GND
23 VinLD Loading driver input
24 CTKerr2 Capacitor connection terminal for error amplifer filter
25 CTKerr1 Capacitor connection terminal for error amplifer filter
26 VinTK Tracking driver input
27 BIAS Bias input
28 STBY Standby terminal
1-18
TH-A30
SST39VF800A (U6) : 8M Flash memory
1. Pin layout
A15 1 48 A16
A14 2 47 NC
A13 3 46 Vss
A12 4 45 DQ15
A11 5 44 DQ7
A10 6 43 DQ14
A9 7 42 DQ6
A8 8 41 DQ13
NC 9 40 DQ5
NC 10 39 DQ12
WE# 11 38 DQ4
NC 12 37 VDD
NC 13 36 DQ11
NC 14 35 DQ3
NC 15 34 DQ10
A18 16 33 DQ2
A17 17 32 DQ9
A7 18 31 DQ1
A6 19 30 DQ8
A5 20 29 DQ0
A4 21 28 OE#
A3 22 27 Vss
A2 23 26 CE#
A1 24 25 A0
2. Block diagram
EEPROM
X-Decoder
Cell Array
Memory Address
Address Buffer & Latches
Y-Decoder
CE#
Control Logic
OE#
I/O Buffers & Data Latches
WE#
DQ15-DQ0
3. Pin function
Symbol Pin name Function
AMS- A0 Address Inputs To provide memory addresses. During Sector-Erase AMS-A11 address lines will
select the sector. During Block-Erase AMS-A15 address lines will select the block.
DQ15- DQ0 Data Input/Output To output data during Read cycles and receive input data during Write cycles. Data is
internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is
high.
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
VDD Power Supply To provide power supply voltage: 2.7-3.6V
Vss Ground
NC No Connection Unconnected pins.
1-19
TH-A30
AK4355 (U6) : DAC
1.Pin layout 2.Block diagram
1 28
DZF
2 27
Audio
3 26
LOUT1+
I/F
4 25
SCF DAC DATT
5 24
LOUT1-
6 23
MCLK
7 22
8 21
LRCK
9 20 ROUT1+
10 19 SCF DAC DATT
BICK
ROUT1-
11 18
12 17
13 16
14 15
LOUT2+
CSN
SCF DAC DATT
Control
LOUT2-
CCLK
Register
CDTI
ROUT2+
SCF DAC DATT
ROUT2-
LOUT3+
SCF DAC DATT
LOUT3-
SDTI1
SDTI2
ROUT3+
SDTI3
SCF DAC DATT
ROUT3-
3.Pin function
Pin No. Symbol I/O Function
1 VREF I Positive Voltage Reference Input Pin
2 DZF O Zero Input Detect Pin
3 PDN I Power-Down Mode Pin
When at  L , the AK4355 is in the power-down mode and is held in reset.
The AK4355 should always be reset upon power-up.
4 MCLK I Master Clock Input Pin
An external TTL clock should be input on this pin.
5 BICK I Audio Serial Data Clock Pin
6 SDTI1 I DAC1 Audio Serial Data Input Pin
7 SDTI2 I DAC2 Audio Serial Data Input Pin
8 SDTI3 I DAC3 Audio Serial Data Input Pin
9 LRCK I L/R Clock Pin
10 CSN I Chip Select Pin
11 CCLK I Control Clock Pin
12 CDTI I Control Data Input Pin
13 DVDD - Digital Power Supply Pin
14 DVSS - Digital Ground Pin
15 ROUT3- O DAC3 Rch Negative Analog Output Pin
16 ROUT3+ O DAC3 Rch Positive Analog Output Pin
17 LOUT3- O DAC3 Lch Negative Analog Output Pin
18 LOUT3+ O DAC3 Lch Positive Analog Output Pin
19 ROUT2- O DAC2 Rch Negative Analog Output Pin
20 ROUT2+ O DAC2 Rch Positive Analog Output Pin
21 LOUT2- O DAC2 Lch Negative Analog Output Pin
22 LOUT2+ O DAC2 Lch Positive Analog Output Pin
23 ROUT1- O DAC1 Rch Negative Analog Output Pin
24 ROUT1+ O DAC1 Rch Positive Analog Output Pin
25 LOUT1- O DAC1 Lch Negative Analog Output Pin
26 LOUT1+ O DAC1 Lch Positive Analog Output Pin
27 AVSS - Analog Ground Pin
28 AVDD - Analog Power Supply Pin
Note: All input pins should not be left floating.
1-20
TH-A30
M62463AFP (U11) : Surround decoder
1. Pin layout
RLC8 49 32 FBIN
RLC6 50 31 LPF2 OUT
LBPF2 51 30 LPF2 IN2
LBPF1 52 29 LOF2 IN1
RBPF2 53 28 DAINT OUT
RBPF1 54 27 DAINT IN
LT 55 26 DACONT
RT 56 25 ADCONT
LIN 57 24 ADINT OUT
RIN 58 23 ADINT IN
ABcc 59 22 LPF1 OUT
VREF 60 21 LPF1 IN2
IREF 61 20 LPF1 IN1
NGC3 62 19 DSEL OUT
NGC2 63 18 MICOUT
NGC1 64 17 DVss
2. Block diagram
SW1
BY-PASS
NOISE SPACE
1
2
SURROUND
SEQUENCER
+
LOUT
PROLOGIC 1
MUTE
3
4
BY-PASS
L
1
CENTER 2
LIN 57
SPACE
+/-
MODE SURROUND
ROUT
2
CONTROL
3
R 4
ADAPTICVE
MUTE
MATRIX
PROLOGIC SW2
WIDE
NORMAL
C
PHANTOM
RIN 58 5
OFF
MASTER
4
VOLUME
S'
SW3
CVOLOUT
3
Digital Delay
1
Modified BNR
2
10Kbit SRAM 8 SVOLOUT
L+R
L-R
2
Logic
SW4
MASTER
7
2 1
VOLUME
6
3
4
SW5
F.B.VOL MCU
MICIN 12
Interface
1
2
MICVOL
SW6
18 19 20 32 31 33 14 15 16
MICOUT DATA SCK REQ
1-21
RLC3
RLC7
RLC4
RLC1
RLC2
RLC5
PSC4
PSC1
PSC5
PSC2
PSC6
PSC3
DBC3
DBC2
DBC1
BNR IN
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
REQ
CMC
DVdd
LOUT
DATA
SOUT
ROUT
COUT
MICIN
AGND
VREFD
SVOLIN
CVOLIN
SVOLOUT
CVOLOUT
INPUT
BALANCE
SELECTOR
LPF
A/D
D/A
LPF
TH-A30
SP3721A (RU1) : DVD anlog front end chip
1.Pin layout
64-49
2.Pin function
Pin No. Symblo I/O Function
17-32
1,2 DVDRFP,VDVDRFN I RF Signal Inputs
3,4 PD1,PD2 I CD Photodetector Interface Inputs
5-8 A2,B2,C2,D2 I Photo Detector Interface Inputs
9 CP I/O Differential Phase tracking LPF pin
10 CN I/O Differential Phase tracking LPF pin
11-14 A,B,C,D I Photo Detector Interface Inputs
15,16 E,F I CD trackin Error Inputs
17 CDTE - CD Tracking
18 VCI2 - Reference Voltage Input
19 NC - No Connct
20 VNB - Ground
21 DVDPD I APC Input
22 DVDLD O APC ouput
23 CDPD I APC Input
24 CDLD O APC output
25 LDON# I APC Output On/Off
26 VC - Reference Voltage output
27 VCI - Reference Voltage Input
28 VPB - Power
29 MIRR O Mirror Detect Output
30 MP - MIRR signal Peak hold pin
31 MB - MIRR signal Bottom hold pin
32 FDCHG# I Low Impedance Enalle
33 MLPF - MIRR signal LPF pin
34 MEVO O SIGO Bottom Envelope Output
35 MIN I RF signal Input for Mirror
36 PI O Pull-in Signal Output
37 DFT O Defect Output
38 TPH - PI Top Hold pin
39 MEV - Sigo Bottom Envelope pin
40 MEI I Mirror Envelope Input
41 TE O Tracking Error Signal Output
42 FE O Focusing Error Signal Output
43 CE O Center Error Signal Output
44 LCN - Center Error LPF pin
45 LCP - Center Error LPF pin
46 SCLK I Serial Clock
47 SDATA I/O Serial Data
48 SDEN I Serial Data Enable
49 HOLD1 I Hold Control
50 VNA - Ground
51,52 FNP,FNN O Differential Normal Output
53,54 DIP,DIN I Analog inputs for RF Single Buffer
55 RX - Reference Resistor Input
56 BYP I/O
57 SIGO O Single Ended Normal Output
58 VPA - Power
59,60 AIP,AIN I AGC Amplifier Inputs
61,62 ATOP/ATON O Differential Attenuator Output
63 CDRF I RF Signal Input
64 CDRFDC O CD RF signal Output
1-22
16-1
33-48
TH-A30
M12L64164A (AU13, AU14) : SDRAM
1.Pin layout 2.Pin function
VDD 1 54 VSS
Symbol Function
DQ0 2 53 DQ15
CLK System Clock
VDDQ 3 52 VSSQ
DQ1 4 51 DQ14 CS Chip Select
DQ2 5 50 DQ13
CKE Clock Enable
VSSQ 6 49 VDDQ
A0 ~ A11 Address
DQ3 7 48 DQ12
DQ4 8 47 DQ11
A12 , A13 Bank Select Address
VDDQ 9 46 VSSQ
RAS Row Address Strobe
DQ5 10 45 DQ10
DQ6 11 44 DQ9 CAS Column Address Strobe
VSSQ 12 43 VDDQ
WE Write Enable
DQ7 13 42 DQ8
L(U)DQM Data Input / Output Mask
VDD 14 41 VSS
LDQM 15 40 NC
DQ0 ~ DQ15 Data Input / Output
WE 16 39 UDQM
VDD / VSS Power Supply / Ground
CAS 17 38 CLK
RAS 18 37 CKE VDDQ / VSSQ Data Output Power / Ground
CS 19 36 NC
NC No Connection
A13 20 35 A11
A12 21 34 A9
A10/AP 22 33 A8
A0 23 32 A7
A1 24 31 A6
A2 25 30 A5
A3 26 29 A4
VDD 27 28 VSS
3.Block diagram
CLK
Clock
Generator
Bank D
CKE
Bank C
Bank B
Row
Address
Address
Buffer
Mode Bank A
&
Register
Refresh
Counter
Sense Amplifier
L(U)DQM
Column
Column Decoder
CS
Address
Buffer
RAS
&
Refresh
CAS
Counter
Data Control Circuit
DQ
WE
1-23
Row Decoder
Control Logic
Buffer
Command Decoder
Latch Circuit
Input & Output
TH-A30
BA4560 (AIC2, IC5, IC6, IC7, U1, U3, U5, U9, U13) : Dual op amp.
1.Pin layout
OUT1 1 8 VCC
 IN1 2 7 OUT2
1ch
 +
2ch
+ IN1 3 6  IN2
+ 
VEE 4 5 + IN2
74LVT573 (U10, U11, U12) : Latch
1. Pin layout 2. Pin function 3. Truth table
Symbol Function
Inputs Outputs
OE 1 20 Vcc
D0 2 19 O0
D0-D7 Data Inputs
LE OE Dn On
D1 3 18 O1
LE Latch Enable Input
X H X Z
D2 4 17 O2
D3 5 16 O3
OE Output Enable Input H L L L
D4 6 15 O4
H L H H
O0-O7 3-STATE Latch Outputs
D5 7 14 O5
L L X O0
D6 8 13 O6
H:HIGH Voltage Level
D7 9 12 O7
L:LOW Voltage Level
GND 10 11 LE Z:High Impedance
X:Immaterial
O0:Previous O0 before HIGH to LOW transition of Latch Enable
FAN8082 (U10) : DC motor driver
2. Block diagram
1.Pin layout
1 8
DRIVER OUT
GND 1 8 VO2 GND V
O2
V
O1 2
7
VO1 2 7 PVCC PV
CC
PRE DRIVER
VCTL 3
6
SV
VCTL 3 5 SVCC CC
TSD BIAS
VIN1 4 LOGIC SWITCH
5
V
IN2
VIN1 4 6 VIN2
3. Pin function
Pin No. Symbol I/O Function
1-
GND
Ground
2V O Output 1
O1
3V I Motor speed control
CTL
4VIN1 I Input 1
5VI Input 2
IN2
6SV- Supply voltage (Signal)
CC
7PVCC - Supply voltage (Power)
8V O Output 2
O2
1-24
TH-A30
74HCT245 (U15) : Transceiver
1.Pin layout 2.Truth table
ENABLE
Control
Vcc G B1 B2 B3 B4 B5 B6 B7 B8
Operation
Inputs
20 19 18 17 16 15 14 13 12 11
G DIR 245
L L B data to A bus
L H A data to B bus
H X
isolation
H = HIGH Level
L = LOW Level
X = Irrelevant
1 2 3 4 5 6 7 8 9 10
DIR A1 A2 A3 A4 A5 A6 A7 A8 GND
M5705 (DU3) : DVD-ROM controller
1.Block diagram
4M DRAM
M5703/M5707
RF
ATAPI
Amp
&
Data
PC
M
MPEG
Separator
RAM
DVD-DSP I/F
Arbiter
MPEG
DEC.
C3 ECC
EDC
Digital
Motor
CD-DSP
Servo
Target MCU
Driver
Search
ROM
1-25
TH-A30
BA7612F (VIC3) : Video signal switcher
1. Block diagram
2. Truth table
CTL A CTL B OUT
IN1 1 8 VOUT
MUTE
L (OPEN) L (OPEN) IN1
6dB 75&!
CTLA 2 7 VCC
L (OPEN) HIN2
CTLB 3 LOGIC 6 IN3
HIN3
L (OPEN)
HH MUTE
IN2 4 5 GND
TDA7440D (U2) : Audio processor
1. Terminal layout 2. Block diagram
MUXO-L IN(L) TRE(L) BIN(L) BOUT(L)
4 8 9 18 14 15
LIN1
RIN3 1 28 RIN4
100K
RB
RIN2 2 27 LOUT
5
RIN1 3 26 ROUT
LIN2
LIN1 4 25 AGND 100K
27
LIN2 5 24 VS SPKR ATT
6 G VOLUME TREBLE BASS LOUT
LEFT
LIN3
LIN3 6 23 CREF
100K
LIN4 7 22 SDA
7
MUXO-L 8 21 SCL
LIN4
IN(L) 9 20 DGND
100K
21
0/30dB SCL
MUXO-R 10 19 TRE(R)
I2CBUS DECODER + LATCHES 22
2dB STEP
3 SDA
IN(R) 11 18 TRE(L)
RIN1 20
DGND
BIN(R) 12 17 PS1 100K
BOUT(R) 13 16 LP
2
RIN2
BIN(L) 14 15 BOUT(L)
100K 26
SPKR ATT
G VOLUME TREBLE BASS ROUT
RIGHT
1
RIN3
VREF
100K
24
28 VS
RIN4 SUPPLY 25
INPUT MULTIPLEXER AGND
RB
100K
+ GAIN
10 11 19 12 13 23
MUXO-R IN(R) TRE(R) BIN(R) BOUT(R) CREF
W29EE512 (DU5) : Flash memory
1. Pin layout 2. Block diagram
3. Pin function
VDD
Symbol Function
Vss
4 3 2 1 32 31 30
A0~A15 Address input
A7 5 29 A14
DQ0~DQ7 Data I/O
A6 6 28 A13
DQ0
A5 7 27 A8
CS CE Chip enable
OUTPUT
CONTROL
A4 8 26 A9
OE
OE Output enable
BUFFER
A3 9 25 A11
WE DQ7
A2 10 24 OE
WE Write enable
A1 11 23 A10
Vcc Power
A0 12 22 CE
DQ0 13 21 DQ7 GND Ground
A0
14 15 16 17 18 19 20
NC No connect
CORE
DECODER
ARRY
A15
1-26
A12
A15
NC
NC
Vcc
WE
NC
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
GND
TH-A30
TDA7449L (U7, U12) : Audio processor
1.Pin layout 2.Block diagram
MUXOUTL
10
CREF 1 20 SDA
8
L-IN1
VS 2 19 SCL
100K
PGND 3 18 DIG_GND
ROUT 4 17 N.C.
9
L-IN2 5
LOUT 5 16 N.C. SPKR ATT
G VOLUME LOUT
LEFT
100K
R_IN2 6 15 N.C.
R_IN1 7 14 N.C.
L_IN1 8 13 N.C.
19
0/30dB SCL
L_IN2 9 12 N.C.
7 I2CBUS DECODER + LATCHES 20
2dB STEP
R-IN1 SDA
MUXOUT(L) 10 11 MUXOUT(R)
18
100K DIG_GND
6
R-IN2 4
SPKR ATT
G VOLUME ROUT
RIGHT
100K
VREF
2
VS
SUPPLY 3
INPUT MULTIPLEXER AGND
+ GAIN
11 1
D98AU868
MUXOUTR CREF
TL3472 (RU2) : Op. amp.
1.Pin layout
1OUT 1 8 VCC+
1INą 2 7 2OUT
1IN+ 3 6 2INą
VCCą/GND 4 5 2IN+
1-27
TH-A30
VICTOR COMPANY OF JAPAN, LIMITED
AUDIO & COMMUNICATION BUSINESS DIVISION
PERSONAL & MOBILE NETWORK BUSINESS UNIT. 10-1,1chome,Ohwatari-machi,Maebashi-city,371-8543,Japan
200208
(No.21128)