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IV SEMESTER HDL Lab

1) \/HDL codę to realize all the logie gates

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity BASIC_GATES is port(a,b: in bit;

c,d,e,f,g,h: out bit); end BASI C_GATES;

architecture Behavioral of BASIC_GATES is begin

c<= not a; d<= a and b; e<= a or b; f<= a nand b; g<= a nor b; h<= a xor b;

end Behavioral;

Verilog codę

module basic_gates (a,b,c,d,e,f,g,h);

input a,b;

output c,d,e,f,g,h;

assign c= ~a;

assign d=a&b;

assign e=a|b;

assign f=~(a&b);

assign g = -(a|b);

assign h=a^/vb;

endmodule

Department of Electronics & Communication En*ę. 1 Dr.TTIT.KGF