Mikroprocesor MicroBlaze

Dariusz Chaberski

§ charakterystyka

+ opis w języku HDL (ang. Hardware Description Language)

najczęściej jest to VHDL (ang. Very High Speed Circuit Integrated HDL)

+ możliwość doboru szerokości magistral, ilości rejestrów pod konkretne zastosowanie

+ możliwość implementacji dodatkowego sprzętu pod konkretne zastosowanie (liczniki, PWM,

generatory itp)

+ implementacja do układu programowalnego FPGA

+ narzędzie wspomagające EDK (ang. Embeded Development Kit) firmy Xilinx

3 aplikacja - język C

3 opis mikroprocesora - język VHDL

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§ MicroBlaze Core Block Diagram

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§ Data Types and Endianness

+ Word Data Type

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§ Half Word Data Type

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§ Byte Data Type

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§ Pipeline Architecture

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§ EDK

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§ download.cmd

setMode -bscan

setCable -p usb21

identify

assignfile -p 4 -file implementation/download.bit

program -p 4

quit

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§ Impact

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§ *.mhs

... BEGIN lmb bram if cntlr

PARAMETER INSTANCE = ilmb cntlr

PARAMETER HW VER = 2.00.a

PARAMETER C BASEADDR = 0x00000000

PARAMETER C HIGHADDR = 0x0000ffff

BUS INTERFACE SLMB = ilmb

BUS INTERFACE BRAM PORT = ilmb port

END

BEGIN bram block

PARAMETER INSTANCE = lmb bram

PARAMETER HW VER = 1.00.a

BUS INTERFACE PORTA = ilmb port

BUS INTERFACE PORTB = dlmb port

END ...

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§ *.mss

...

BEGIN DRIVER

PARAMETER DRIVER NAME = bram

PARAMETER DRIVER VER = 1.00.a

PARAMETER HW INSTANCE = dlmb cntlr

END

BEGIN DRIVER

PARAMETER DRIVER NAME = bram

PARAMETER DRIVER VER = 1.00.a

PARAMETER HW INSTANCE = ilmb cntlr

END

...

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§ *.ucf

...

Net fpga 0 LEDs 8Bit GPIO IO pin<0> LOC = E13;

Net fpga 0 LEDs 8Bit GPIO IO pin<0> IOSTANDARD=LVCMOS25;

Net fpga 0 LEDs 8Bit GPIO IO pin<0> PULLDOWN;

Net fpga 0 LEDs 8Bit GPIO IO pin<0> SLEW=SLOW;

Net fpga 0 LEDs 8Bit GPIO IO pin<0> DRIVE=2;

Net fpga 0 LEDs 8Bit GPIO IO pin<1> LOC = D14;

Net fpga 0 LEDs 8Bit GPIO IO pin<1> IOSTANDARD=LVCMOS25;

Net fpga 0 LEDs 8Bit GPIO IO pin<1> PULLDOWN;

Net fpga 0 LEDs 8Bit GPIO IO pin<1> SLEW=SLOW;

Net fpga 0 LEDs 8Bit GPIO IO pin<1> DRIVE=2;

...

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ML 501 (Xilinx)

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§ GPIO LED [0:7] (ML501)

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§ *.c

#include "xgpio.h"

#include "xparameters.h"

int main(void) {

XGpio gpioLED;

XGpio gpioKEY;

XGpio Initialize(&gpioLED, XPAR LEDS 8BIT DEVICE ID);

XGpio SetDataDirection(&gpioLED, 1, 0x00);

XGpio Initialize(&gpioKEY, XPAR DIP SWITCHES 8BIT DEVICE ID);

XGpio SetDataDirection(&gpioKEY, 1, 0xff);

int val;

while(1) {

val = XGpio DiscreteRead(&gpioKEY, 1);

XGpio DiscreteWrite(&gpioLED, 1, val); }

return 0; }

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§ *.c (pola bitowe)

#include "xgpio.h"

#include "xparameters.h"

struct pole bitowe

{

unsigned int : 24;

unsigned int b7 : 1;

...

unsigned int b1 : 1;

unsigned int b0 : 1;

};

#define keys *(unsigned int *)&vi

#define key0 vi.b0

...

#define leds *(unsigned int *)&vo

#define led0 vo.b0

...

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int main(void){

XGpio gpioLED;

XGpio gpioKEY;

XGpio Initialize(&gpioLED, XPAR LEDS 8BIT DEVICE ID);

XGpio SetDataDirection(&gpioLED, 1, 0x00);

XGpio Initialize(&gpioKEY, XPAR DIP SWITCHES 8BIT DEVICE ID);

XGpio SetDataDirection(&gpioKEY, 1, 0xff);

struct pole bitowe vi, vo;

while(1){

keys = XGpio DiscreteRead(&gpioKEY, 1);

led0=key0 & key1 | key2;

led1=key3 ^ key4;

//przerzutnik RS

led6=~(key6 & led7);

led7=~(key7 & led6);

XGpio DiscreteWrite(&gpioLED, 1, leds);}

return 0;}

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GPIO

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§ fpga editor *.ncd

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SLICE (2 x CLB)

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CLB (4 x LUT, 4 x FF/LATCH)

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BRAM

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OPB Interrupt Controller

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§ *.ucf (Interrupt pin)

Net irq pin LOC = K20; #DHR1 12 ml501

§ *.c

#include "xgpio.h"

#include "xparameters.h"

#include "xintc l.h"

int val;

void interrupt function(int num)

{

val++;

}

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int main(void)

{

XIntc RegisterHandler(XPAR OPB INTC 0 BASEADDR, XPAR OPB INTC 0 MTM IRQ PIN INTR,

(XInterruptHandler)interrupt function, (void*)0);

XIntc mMasterEnable(XPAR OPB INTC 0 BASEADDR);

XIntc mEnableIntr(XPAR OPB INTC 0 BASEADDR, XPAR MTM IRQ PIN MASK);

microblaze enable interrupts();

XGpio gpioLED;

XGpio Initialize(&gpioLED, XPAR LEDS 8BIT DEVICE ID);

XGpio SetDataDirection(&gpioLED, 1, 0x00);

while(1)

{

XGpio DiscreteWrite(&gpioLED, 1, val);

}

return 0;

}

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