P.R. KSA WETI PG

Industrial Computer

Architecture Box

6. Microcontroller systems

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8-bit microcontroller example

Port A

Port D

Port C

Port B

Port E

Analog

multiplexer

8-bit

8-bit

8-bit

4-bit

8-bit

A/D

converte

r

Programmable

timer

I/O

serial

port

UART

serial

port

Clock circuit

Reset circuit

Watchdog

Interrupt controller

CPU

8192-

byte

ROM

512-byte

EEPROM

256-byte

RAM

Motorola 68HC11 block diagram

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Port 3

Port 2

Port 1

Port 0

8-bit

UART

serial

port

Clock circuit

Programmable

timer (16-bit)

Reset circuit

Interrupt controller

CPU

4096-

byte

ROM

128-byte

RAM

8-bit microcontroller example

Programmable

timer (16-bit)

Intel MCS-51 (8051)

8-bit

8-bit

8-bit

Alternate port function

external system bus A15-A8

Alternate port function

external system bus AD7- AD0

RD & WR

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Port 2

Port 0

Port 4

Port 3

Port 1

8-bit

Programmable

timer

I/O

serial

port

Clock circuit

Reset circuit

Watchdog

Interrupt controller

CPU

8192-

byte

ROM

232-byte

RAM

16-bit microcontroller example

Intel 8096

8-bit

8-bit

8-channel analog

multiplexer

10-bit A/D

converter

8-bit

8-bit

8-bit

High speed

I/O

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Port 2

Port 1

Port 0

real-time output

I/O

serial

port

Clock circuit

Reset circuit

Watchdog

Interrupt controller

CPU

8192-

byte

ROM

256-byte

RAM

NEC uPD78310/312

8-bit

8-bit

4-channel analog

multiplexer

8-bit A/D

converter

8-bit

Macro service

sequencer

16-bit microcontroller example

Port 4

Port 5

Port 3

Programmable

16-bit timer

Programmable

16-bit timer

PWM

8-bit

8-bit

P.R. KSA WETI PG

bus and operand widths

Address bus

Data bus

Motorola 68HC11

Intel MCS-51

Intel 8096

Intel 8096

Motorola 68HC11

Intel MCS-51

NEC uPD 78310/312

NEC uPD 78310/312

68HC11

MCS-51

8096

78310

0

5

10

15

20

25

30

35

68HC11

MCS-51

8096

78310

bit

byte

word

double

word

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CPU organization

PSW

Buffer

Accumulator

Buffer

internal data bus

ALU

Accomulator

B-register

PSW

Special function

registers

SP

DPL

DPH

MCS-51 family

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CPU organization

Temp register

Constants

Loop counter

PSW register

Lower word shift register

Higher word shift register

Prog. counter

Incrementator

Delay

ALU

16-bit data bus

8-bit address bus

(16)

(8)

(16)

(16)

upper

lower

(8)

(8)

Intel 8096

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internal program and data memory organization

07 06 05 04 0302 0100

0F 0E 0D0C 0B0A 0908

7F 7E 7D7C 7B7A 7978

20H

2FH

8 register bank 0

8 register bank 1

8 register bank 2

8 register bank 3

00H

1FH

work register banks

bit addressable area

data RAM memory

00H

20H

30H

7FH

data RAM memory

80H

FFH

special function

registers

direct addressing mode

indirect addressing mode

Intel MCS-51 family

internal

ROM

4 - 8 kB

bank selector

PSW bit 3,4

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external program and data memory

P

O

R

T
0

P

O

R

T
2

Intel

8051

L

A

T

C

H

A8-A15

A0-A7

AD0-AD7

A8-A15

A0-A15

ROM

External

RAM

External

8

8

8

16

16

16

D0 - D7

D0 - D7

8

8

8

Intel MCS-51 family

PORT 3

RD

WR

PSEN

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SFR - special function registers map and function

Adress

+0

+1

+2

+3

+4

+5

+6

+7

F8
F0

B

E8
E0

ACC

D8
D0

PSW

C8
C0
B8

IP

B0

P3

A8

IE

A0

P2

98

SCON

SBUF

90

P1

88

TCON

TMOD

TL0

TL1

TH0

TH1

80

P0

SP

DPL

DPH

PCON

Bit addressable SFR

A, B, PSW, DPL, DPH - CPU related registers

IP, IE - interrupt priority and enable registers

SBUF, SCON - UART data and configuration registers

P0, P1, P2, P3 - bi-directional parallel ports

TCON, TMOD, TL0, TL1, TH0, TH1 - timer registers

PCON - power control register

Intel 8051

7 6 5 4 3 2 1 0

E0

byte

address

bit number

byte address

+ bit number

bit address

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parallel port structures and operation

Q

Q

D

Cl

latch

read latch

read pin

alternate output

function

Vcc

PIN

alternate
output function

write to
latch

internal
data bus

7 6 5 4 3 2 1 0

Internal data bus

I/O configurations

read latch / read pin

write latch / write pin

read-modify-write feature

port circuit example

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port alternate functions example

I/O lines

7 6 5 4 3 2 1 0

Internal data bus

basic port function

7 6 5 4 3 2 1 0

Internal data bus

alternate port function

RxD

TxD

Int0

Int1

T0

T1

WR

RD

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read - modify - write port feature

Q

Q

D

Cl

latch

read latch

read pin

alternate output

function

Vcc

PIN

alternate
output function

write to
latch

internal
data bus

7 6 5 4 3 2 1 0

Internal data bus

ANL P3,#0FCH

wired AND

P3 content

immediate

argument

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synchronous and asynchronous data exchange

protocols

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3

Data

Shift clock

character i

character i

+1

synchronization

character

synchronization

character

data

character

data

character

data

character

D0 D1 D2 D3 D4 D5 D6 D7 D7

Data

one frame

one start bit

one stop bit

one frame

one frame

one frame

SS

asynchronous protocol

synchronous protocol

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UART interface hardware resources

internal data bus

Transmitter buffer

Transmitter control

SHIFT

START

TxCLOCK

SEND

write to buffer

start bit

AND

OR

RxD pin

SHIFT

CLOCK

NAND

TxD

pin

clock

RxCLOCK

read from buffer

Receiver shift buffer

START

RECEIVE

SHIFT

Receiver control

AND

reception

enable

not reception

finished flag

RxD pin

Receiver buffer

load buffer

internal data bus

TI

RI

OR

serial port

interrupt

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UART operating modes (Intel MCS-51 family)

7 6 5 4 3 2 1 0

TxD

shift clock = 1/12 f

osc

MODE 0

RxD

Transmitter

buffer

shift clock

variable

(programmable)

MODE 1

Receiver

buffer

Timer 1

7 6 5 4 3 2 1 0

RxD

7 6 5 4 3 2 1 0

TxD

frame bits

7 6 5 4 3 2 1 0

8

Transmitter

buffer

MODE 2

Receiver

buffer

RxD

frame bits

7 6 5 4 3 2 1 0

8

TxD

shift clock = 1/32 f

osc

or 1/64 f

osc

8-th bit

shift clock

variable

(programmable)

Timer 1

7 6 5 4 3 2 1 0

8

Transmitter

buffer

MODE 3

Receiver

buffer

RxD

frame bits

7 6 5 4 3 2 1 0

8

TxD

8-th bit

2

SMOD

Oscillator frequency

Baud Rate = ----------- * ----------------------------------------

(in mode 1 and 3 )

32 12 * [256 - timer initial value]

• SMOD is a control bit

• UART is controlled via SCON control register

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UART control registers and baud rate generation

(MCS-51)

internal data bus

MODE 3

7 6 5 4 3 2 1 0

8

RxD

7 6 5 4 3 2 1 0

8

TxD

Timer 1

internal data bus

SBUF

SCON

SM

0

SM

1

SM

2

RE

N

TB8 RB

8

TI

RI

• SM0, SM1 - mode

• SM2 - multiprocessor communication feature

• REN - remote enable

• TB8 - 9th transmitted data bit in mode 2 and 3

• RB8 - 9th received data bit in mode 2 and 3

• TI - transmit interrupt flag

• RI - receive interrupt flag

OSC

2

SMOD

/64

1/12

clock sources

constant baud rate (mode 0 & 2)

variable baud rate (mode 1 & 3)

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UART multiprocessor communication features

Transmitter

buffer

RxD

7 6 5 4 3 2 1 0

8

MODE 2 & 3

Receiver

buffer

7 6 5 4 3 2 1 0

8

TxD

SCON

TB8 RB8

SM2

SM2 RB8 UART Interrupt

0

0

YES

0

1

YES

1

0

NO

1

1

YES

• network address send with TB8=1

• network data send with TB8=0

uC1

RxD TxD

uC2

RxD TxD

uC3

RxD TxD

uC4

RxD TxD

sender

receiver

TB8=1

SM2 =1

SM2 =1

SM2 =1

TB8=0

SM2 =1

SM2 =0

SM2 =1

addressing

phase

data transfer

phase

Intel MCS-51

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SDA

I

2

C protocol

SDA

SCL

START

STOP

data stable

and valid

data floating

I

2

C frame

•

A - acknowledge

•

A - not acknowledge

•

S - start

•

P - stop

S

Slave address R/W

A

DATA

A

DATA

A/A

P

S

Slave address R/W

A

DATA

A

DATA

A/A

P

n *

n *

master to slave

slave to master

master - sender, slave - receiver

master - receiver, slave - sender

SCL

1 - 7

ADDRESS

8

R/W

9

ACK

1 - 7

ADDRESS

8

R/W

9

ACK

S

P

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I2C interface hardware resources

internal data bus

SIDAT

SICON

Data

buffer

Configuration

register

SIADR

SISTA

Address

register

Status

register

S

7 6 5 4 3 2 1

R/W

ACK

7 6 5 4 3 2 1 0

ACK P

SDA

SCL

internal data bus

status

control

if RECEIVED ADDRESS = MY ADDRESS
receive data
else ignore them

• MST - master/slave

• TRX - transmission direction

• BB - bus busy

• PIN - pending interrupt

• ESO - enable input

• BCi - bit counter

• AL - arbitration lost

• AD0 - broadcast address

ALS

BIT

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programmable timer/counters hardware and

modes

TLi 5/8 bits

THi 8 bits

TFi

interrupt

OSC

1/12

C/T=0

C/T=1

Ti pin

AND

TRi

OR

NOT

GATE

INTi

timer configuration in mode 0 and 1

control

TLi 8 bits

THi 8 bits

TFi

interrupt

OSC

1/12

C/T=0

C/T=1

Ti pin

AND

TRi

OR

NOT

GATE

INTi

timer configuration in mode 2 (Auto-
Reload)

reload

control

in mode 3 timer 0 is split into two 8-bit counters

Intel MCS-51

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programmable timer/counters - programming

internal data bus

TMOD

TCON

TF1

TF0

TR1

TR1 IE1

IE0

IT1

IT0

G

M1

C/T

M0 G

M1

C/T

M0

timer 1

timer 0

•

G

- getting control when set, timer/counter

is enabled only when INTi is high and TRi
control pin is set, when cleared timer i is
enabled whenever TRi is set.

•

C/T

- timer or counter selector.

•

M1, M0

- operating mode.

•

TFi

- timer i overflow flag, set by

hardware and cleared by hardware
when processor vectors to interrupt
routine.

•

TRi

- timer i run control bit.

•

IEi

- external interrupt flag, set by

hardware when external signal
detected, cleared when interrupt
processed.

• ITi

- external interrupt type control

bit (falling edge or low level)

where i is a timer index

Intel MCS-51 family

Mode 0

- 8-bit counter with a 5 bit prescaler

Mode 1

- 16 bit timer/counter

Mode 2

- 8-bit auto reload timer/counter

Mode 3

- timer 0 split into two independent

8-bit timer/counters, timer 1 stopped

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interrupt sources and priority

internal data bus

IP

IE

EA

-

-

ES ET1

ET0

EX1

EX0

-

-

-

PS PT1

PT0

PX1

PX0

•

IP

- interrupt priority register

1 - defines higher priority level
0 - defines lower priority level.

•

IE

- interrupt enable register

1 - enables interrupt source
0 - disables interrupt source

Intel MCS-51 family

Each interrupt source can be

individually

programmed to one of two priority levels

by

setting or clearing a bit in SFR IP. A low
priority interrupt can itself be interrupted by a
high-priority interrupt, so Interrupt can be
nested.

IE0

INT0

IE0

INT0

TF0

TF0

OR

TI

RI

interrupt

sources

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resolving simultaneous interrupt requests

interrupt flags

S

IE0

IE1 TF0

TF1

interrupt flags
polling order

Source Priority within level

1

IE0

highest

2

TF0

3

IE1

4

TF1

5 RI+TI

lowest

example priority

1

0

0

0

1

IP

1

higher priority interrupt
interrupts lower priority
interrupt service routine

2

the same priority
interrupt
ordered by priority in
level

interrupt service routine
in progress

t

T0 S

E0

E1

T1

1

2

1

latency for E0

latency for E1

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how interrupts are handled

code area

data area

PC

SP

PC

interrupt

loading vector

service routine

return command

stack

main program

Interrupt

source

Vector

address

External 0

0003H

Timer 0

000BH

External 1

0013H

Timer 1

001BH

Sertial

0023H

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clock generation and reset circuitry

C1=C2=30 +/- 10 pF

C1

C2

8051

1,2-12 MHz

XTAL1

XTAL2

8051

1,2-12 MHz

XTAL1

XTAL2

External

clock

(TTL)

S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6

machine cycle

machine cycle

ALE

command

fetch

idle

command

fetch

Vcc

8051

WATCH DOG

OR

internal reset

R

C

reset

key

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power saving options

8051

C1

C2

OSC

XTAL1

XTAL2

NAND

clock

generator

NAND

CPU

interrupt, serial

port,

timer blocks

PD

IDL

internal bus

IDL

PD

PCON

SFR area

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watch dog circuit

internal bus

WLE

SFR

register

Watch dog TIMER

Prescaler

AND

fosc/12

OR

overflow

RST

internal

reset

clear

load

OR

enable

watch dog

write watch dog

clear

in SFR area

watch dog write enable

fosc
f timer = -------------------
12 * prescaler

write enable

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single chip application example

Liquid chromatography column

Pump

P

h

ili

p

s

8

0

C

5

5

2

m

ic

ro

co

n

tr

o

lle

r

11.058 MHz

X

TA

L1

X

TA

L2

E

W

+Vcc

E

A

Reset

Amplifiers

P

1

PWM

UV lamp

A

D

C

absorption

sensor

Terminal

P

3

RxD
TxD

Liquid chromatography controller

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bringing out the internal bus

multiplexed

AD0 - AD7

data bus D0 - D7

address bus A8 -

A15

address bus A0 - A7

LATCH

REGISTER

ALE

(address latch

enable)

PORT n

PORT m

PORT k

RD - external memory read strobe

WR - external memory write strobe

MICRO-

CONTROLLER

external

system

bus

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external memory expansion example

A0-A7

A8-A15

AD0-AD7

8051

Port

0

Port

2

L

A

T

C

H

Port

0

A0-A10

D0-D7

EPROM

2 kB

RAM
4 kB

D0-D7

A0-A11

PSEN

EA

RD

WR

74138

ADDRESS

DECODER

A11-A15

A

B

C

E2

E1

0

1

2

3

4

5

6

7

CS

OR

OR

CS

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expanding I/O port techniques example

A0-A7

A8-A15

AD0-AD7

8051

Port

0

Port

2

L

A

T

C

H

Port

0

D0-D7

EA

RD

WR

74138

ADDRESS

DECODER

A

B

C

E2

E1

0

1

2

3

4

5

6

7

L
A
T
C
H

A15

A2-A0

L
A
T
C
H

output

port

input

port

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expanding pulse I/O port techniques

Microcontroller

output port

output select

timer output

74138
3- to 8-line decoder

EN

A B C

7 6 5 4 3 2 1 0

active low
pulse outputs

active high pulse outputs

generation of

nonoverlaping

accurately timed

outputs

Microcontroller

output port

input select

timer input

74151
1-of-8 data selector

EN

A B C

7 6 5 4 3 2 1 0

edge-sensitive inputs

making accurately

timed measurements
on up to eight inputs,

one at a time

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8051 CPU register structure and addressing

modes

ACC

B

PSW

DPH

DPL

PC

CY AC

F0 RS1

OV -

P

RS0

External

RAM

ROM

SP

Internal

RAM

r0

r1

r2

r3

r4

r5

r6

r7

•

register addressing mode MOV A,B

• direct addressing mode MOV A,27

• register indirect addressing mode MOV A,@r1; MOVX A,@DPTR

• immediate addressing mode MOV B,#40H

• indirect base and index register addressing mode
MOV A,@DPTR +A; MOV A,@PC +A

P.R. KSA WETI PG

instruction set summary (Intel MCS-51 family)

Arithmetic commands

ADD

A=A+op2

ADDC

A=A+op2+CY

SUBB

A=A-op2-CY

MUL

A,B=A*B

DIV

A,B=A/B

INC

A, reg, direct, @reg, DPTR

DEC

A, reg, direct, @reg

where op2 = reg, direct address,

indirect address (@reg),
immediate operand (#)

Bit oriented commands

ANL

C AND bit, C AND not bit

ORL

C OR bit, C OR not bit

CPL

bit

CLR

bit

SETB

bit

Logic commands

ANL

A=A AND op2, direct=A AND direct

ORL

A=A OR op2, direct=A OR direct

XRL

A=A XOR op2, direct=A XOR direct

CPL

A

CLR

A

RL

cyclic shift A to left

RLC

cyclic shift A to right

RR

cyclic shift A to left through CY

RRC

cyclic shift A to right through CY

where op2 = reg, direct address,

indirect address (@reg),
immediate operand (#)

Subroutine calls

ACALL

11-bit address

LCALL

16-bit address

RET

return

RETI

return from interrupt

Stack related commands

PUSH

direct

POP

direct

Other commands

SWAP

A

XCH

A,op2

XCHD

A,@reg

NOP
where op2 = reg, direct, @reg

P.R. KSA WETI PG

instruction set summary (Intel MCS-51 family)

Jump commands

SJMP

relative 8-bit address

AJMP

11-bit address

LJMP

16-bit address

CJNE

compare and jump if not equal

compared pairs A,direct, A,#, reg,#
DJNZ

decrement (A, direct) and jump if not zero

JB

jump if bit set (8-bit relative address)

JBC

if bit set clear it and jump (8-bit relative address)

JNB

jump if bit not set (8-bit relative address)

JC

jump if CY=1 (8-bit relative address)

JNC

jump if CY=0 (8-bit relative address)

JZ

jump if A=0 (8-bit relative address)

JNZ

jump if A<>0 (8-bit relative address)

JMP

jump to address @A+DPTR

Data move commands

MOV

A,reg

MOV

A,direct

MOV

A,@reg

MOV

A,#

MOV

reg,A

MOV

reg,direct

MOV

reg,#

MOV

direct,A

MOV

direct,reg

MOV

direct,direct

MOV

direct,@reg

MOV

direct,#

MOV

@reg,A

MOV

@reg,direct

MOV

@reg,#

MOV

DPTR,#16

bit transfer commands

MOV

C,bit

MOV

bit,C

Data transfer from CODE SEGMENT

MOV

A,@A+DPTR

MOV

A,@A+PC

Data exchange with external data memory

MOVX

A,@DPTR

MOVX

@DPTR,A

P.R. KSA WETI PG

References

[1] Halang W.A., Sacha K.M.,
Real-Time Systems. Implementation of Industrial Process Automation,
Wrold Scientific 1992.
[2] Frederick M. Cady,
Microcontrollers and Microcomputers. Principles of software and hardware engineering,
Oxford University Press 1997.
[3] John B. Peatman,
Design with Microcontrollers,
McGraw-Hill International Editions, 1988.
[4] H. Małysiak, B. Pochopień, P. Podsiadło, E. Wróbel,
Modułowe systemy mikrokomputerowe,
Wydawnictwa Naukowo-Techniczne, 1990.
[5] Piotr Misiurewicz,
Układy mikroprocesorowe, struktury i programowanie,
Wydawnictwa Naukowo-Techniczne, 1983.
[6] Antoni Niederliński,
Mikroprocesory, mikrokomputery, mikrosystemy,
Wydawnictwa Szkolne i Pedagogiczne, 1988.
[7] Douglas E. Comer, Sieci komputerowe TCP/IP.
Zasady, protokoły i architektura,
Wydawnictwa Naukowo-Techniczne, 1997
(vol I. Principles, Protocols and Architecture, Prentice Hall Inc. 1995).