V772 CRT Monitor Service Guide
Circuit Operation Theory
ACER V772 DEFLECTION CIRCUIT OPERATION THEORY
1. The Block Diagram of Deflection:
H-sync
Digital
Tilt
Rotation
V-sync
Controller
Circuit
C il
I2C BUS
AutoSync Deflection
Controller
IC TDA4856
Vertical
Deflection
Step Up
Output
G1 & Spot
IC TDA4866 for B+
Dynamic
Killer Circuit
Focus
H-SIZE
Compensation
Shut down
Circuit
G1
Dynamic
Regulation
Feedback
Horizontal
Deflection Output
Circuit
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Circuit Operation Theory
2. Autosync Deflection Controller (TDA4856)
2.1 pin 1 is AFC feedback.
2.2 pin XRAY: if V XRAY > threshold (6.25V typical) switches the whole IC into protection mode.
2.3 pin 3,4,5,6,8 for B+ control function block.
2.4 pin 11(EWDRV) is a parabolic waveform used for pincushion correction
2.5 pin 16 generates video claming & blanking pulse.
2.6 pin 18,19 is I2C data.
2.7 pin 21 V-regulation.
2.8 the resistor from pin 28 (HREF) to ground determines the maximum oscillator frequency.
2.9 the resistor from pin 27 (HBUF) to pin 28 defines the frequency range.
2.10 pin 31 H-regulation.
2.11 pin 32 focus.
+48V
ZD204
C205 +
+14V 30V
2.2U R205
50V
110K
D201
(EL)
1N4148
R236
10
R203
1/2W
62K
VR201
(FS) R238 R257
+14V
HVADJ
12K 2.2K
(OPEN)
HDRV
+14V
C203 C226 +
EWDRV ZD201
R206
2200P 100U
R265 12V
R267
JUMPER 100V 25V
V2
56K (EL)
(PE)
100
HV-ADJ C222
R204
V1
1U
R222
2.2K
R264 50V
C202
1/4W 4.7K
100 (EL) R221
0.01U C227
1/4W
10K
PWM
VBL
100V 0.1U
R201
+C201 (PE) 50V
100 47U
(D)
Q201
HBL 50V
H945
R202 (EL)
100 R237 R208
CLAMP
10K 1M
C204 R216
+2.2U 15.8K
50V (1%)
TP3 TP2
(EL)
+48V
R217 R218
+14V
100K 22.1K
IC201
(1%) (1%)
TDA4856 R235
10K
R270
HFLB
10K
R263
1K
HULK
FOCUS
FOCUS
SCL HSMOD
R214
R209 C207 R220
1.27K
R213
100 0.1U JUMPER
(1%) R262
3.3K
100V
SDA R215 (OPEN)
(PE)
R210 C206 2.67K
C208 C210 R268 R261
C209 C211 SC2
100 0.1U (1%)
0.1U 0.01U 120K (OPEN)
R212
8200P R266 2200P
VSMOD 100V R260 D208
100V 100V
22.1K
100V 100V
R211 (PE) 8.2M 390K (OPEN)
(PE) (EPI)
(1%)
(PE) (PE)
JUMPER
R258 SC1
(OPEN)
D206
(OPEN)
SC0
D207
1N4148
Fig 2 Autosync Deflection Controller circuit
3. H-Driver & Output CKT:
3.1 HDRV signal comes from IC201 pin8, then goes into Q301, Q301 constitutes an inverting stage
and combines with T302 to drive Q302.
3.2 Q302, C306, C309, D305 constitute the H-output CKT with diode modulator mode.
3.3 Q324 & Q325 constitute a switch for lower frequency driver switching to cover the low h HOT
fe
running under low frequency will occur poor-drive condition.
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17 HUNLOCK
CLBL
16
18 SCL
HSYNC 15
19 SDA
VSYNC 14
20 ASCOR
VOUT1 13
21 VSMOD
VOUT2 12
22 VAGC
EWDRV11
23 VREF
VCC10
24 VCAP
i.c.
9
25 SGND
HDRV 8
26 HPLL1
GND 7
27 HBUF
BDRV 6
28 HREF
BIN
5
29 HCAP
BSENS 4
30 HPLL2
BOP 3
31 HSMOD
XRAY 2
32 FOCUS
HFLB 1
V772 CRT Monitor Service Guide
Circuit Operation Theory
Fig 3 HDRV & output circuit
4. Dynamic focus CKT
According to the CRT spec
H dynamic focus Vpp = 300 V
V dynamic focus Vpp = 130 V
4-1 Vertical dynamic focus
The signal from IC201 (pin 32) is a vertical frequency parabolic waveform.
Q321: an inverting amplifier stage.
4-2 Horizontal dynamic focus:
The waveform of C313 (CS-2, CS-1) is a horizontal frequency parabolic waveform, and is amplified by
T304.
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Circuit Operation Theory
+14V
DAF
R391
1K
CS-2
C329
+
C346
+
C327
R351 R373 0.033U
22U
10U
68K 150 400V
16V R327
50V
1/2W (MPE)
(EL) 10
(EL)
1W
(FS)
R352
T304
3.9K
3
2
R379
Q321
1K
FOCUS
BF423
2W
4
1
CS-1
19.20113.001
C328
470P
R353
1KV
560K
(D)
1/4W
-190V
Fig 4 Dynamic Focus circuit
5. Brightness & spot killer CKT.
5.1 G1 CKT
The bright control signal from UC controller is about 0 ~ 5V, when the voltage of bright control signal
decreases, the current flow through R241 increases and the voltage of G1 increases.
5.2 Blanking CKT
To avoid the disturbed picture display on the screen, we have to blank the monitor in the following
situations.
(1) when display mode is changed.
(2) when the monitor enter the power saving mode.
(3) blank the vertical retrace line
when the " blank" signal becomes "high" Q208 "ON" , Q203 "OFF".G1 voltage is about ( -190 *
R"
R271/(R271+R241)) -184V. The signal which is IC201 (pin 16) is inverted and amplified by Q202,
and coupling to G1.During the vertical retrace interval , the G1 voltage will be drop down about 48V.
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Circuit Operation Theory
+45V
+6.5V
R231 R232
100 5.6K
1/4W 1/2W
CLAMP
ZD203 R240
R254
5.1V 3.3K
2.7K
C224
Q208
+
Q202
0.22U
H945
H945
C223
250V
R255
0.01U
(EL) R239
BLANK BRITE Q203
50V
6.8K
10K BF423
(D)
R256
G1
HULK
10K
R241
R271
R269
100K
1M
1K
1/2W
1/2W
-190V
Fig5 Brightness & Spot killer circuit
6. BDRV and step-up CKT
6.1 The "BDRV" signal from TDA4856 pin6 is a square waveform. It is inverted and amplified by
Q201, Q311 and Q312 constitute a buffer stage.
6.2 Q325, L301, D318, C323 is step-up circuit B+ = 45 * ( T + T ) / T .
on off off
B+ +45V
C334
1000P
R333
C322
1KV
10
(OPEN) L301
(D)
1W
100V 900UH
(PE) 19.40195.001
+14V
Q311
A
H945
D318
UG4D
+
C323
Q325
4.7U
IRF630 R370
250V
47
(EL)
R371
PWM
10K
Q312
A733
Fig 6 BDRV & Step-up circuit
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Circuit Operation Theory
7. HV Shutdown Circuit
The IC201 pin2 (XRAY) provides a voltage detector with a threshold. If the voltage at pin XRAY
exceeds this threshold (6.25v typical) the pins HDRV, BDRV, VOUT1 and VOUT2 are floating.
When anode voltage increases, the voltage at FBT (pin3) increases, the voltage at IC201 pin2 increases.
The shutdown voltage is about 28KV.
C204 R216
+2.2U 15.8K
50V (1%)
TP3 TP2
(EL)
+48V
R217 R218
100K 22.1K
IC201
(1%) (1%)
TDA4856
Fig 7 HV- shutdown CKT
8.Horizontal linearity CKT
V772 Cs control truth table
Frequency range SC0 SC1 SC2 Cs Capacitor
ÿ
Fh 36K 0 0 0 C310+C311+C312+C313
ÿ ÿ
36K Fh 40K 0 0 1 C310+C311+C312
ÿ ÿ
40K Fh 51K 1 0 1 C310+C312
ÿ ÿ
51K Fh 62K 1 0 1 C310+C312
ÿ ÿ
62K Fh 72K 1 1 1 C310
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17 HUNLOCK
CLBL 16
18 SCL
HSYNC 15
19 SDA
VSYNC 14
20 ASCOR
VOUT1 13
21 VSMOD
VOUT2 12
22 VAGC
EWDRV11
23 VREF
VCC10
24 VCAP
i.c.
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25 SGND
HDRV 8
26 HPLL1
GND 7
27 HBUF
BDRV 6
28 HREF
BIN 5
29 HCAP
BSENS 4
30 HPLL2
BOP 3
31 HSMOD
XRAY 2
32 FOCUS
HFLB 1
V772 CRT Monitor Service Guide
Circuit Operation Theory
T301
19.70066.001
D
1
*
(RED)
DYH+
B+
A
15
2
DYH-
12
(WHT)
L304
10UH 16
B 19.50051.051
+6.5V
R322
8
2 3 10
2W
D322 5
1N4148
R309
3
220
2W 54 Q322
H945
H-LIN 4
R319
C321
Q324 10K 6
D312
560P
C2235
C330
RGP10J 1KV
9
(OPEN)
50V
(D)
B
CS-2
C313 C312 C311
0.15U 0.33 1.0U +14V
250V 250V 250V
(MPP) (MPP) (MPP)
R316
4.7K
C310
Q307
Q308
0.3U
IRF640
IRF630
400V
R338 R320
(MPP)
100K 100K
A D309
1/4W 1/4W
FR155
C316
R317
0.047U
47K
SC0
50V
Q303
A R315
(D)
H945
47K
D310
C317
R324
FR155
0.047U
47K SC1
50V Q304
R325
(D) H945
R326
47K
Q309 4.7K
IRF630
R321
A
100K
+14V
1/4W
D311 R312
4.7K
C315 FR155
R313
0.047U
47K
50V
SC2
(D)
Q305
CS-1 R311
H945
47K
Fig 8 Linear circuit
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Circuit Operation Theory
9. ABL CIRCUIT
When the beam current is over the limited current, the ABL circuit will pull down the
voltage of the video preamp (pin 10) to reduce the gain of video amplifier.
T301
19.70066.001
1
(RED)
15
2
12
(WHT)
16
ABLADJ
8 R308 R310
D306
10K 1.5K
1N4148
5 1/2W
C324
1500P
3 ABL
100V
R314
(PE) D307
6.8K
1N4148
4
6
9
Fig 9 ABL circuit
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Circuit Operation Theory
10. TILT CKT
We can rotate raster clockwise or counterclockwise by changing the direction of the current flow
through the tilt coil.
When the voltage of MP202 (pin3) is larger than 8V, the current flows from Q205 to Tilt coil, other
wise, the current flows from tilt coil to Q206
+6.5V
+14V +14V
MP202
3P
Q207
1
H945
R247
R249
2.2K 2
(OPEN)
Q205
1/4W
+5V
H945 3
TILT-COIL
R246 R245
10K 10K
R243
+C228
(OPEN)
2.2U
Q206
50V
A733
(EL)
Q204
TILT
C225
+2.2U
H945
R244 Q210
2.2K
A733
50V
(EL)
Fig 10 TILT circuit
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Circuit Operation Theory
11. Vertical Output Circuit
This vertical driver IC circuit is a half bridge configuration
The signals from TDA4856 OSC IC to TDA4863AJ
IC202
TDA4863AJ
+14V
-8.5V
C217
R227
470U
0.22
16V
+
1/2W
(EL)
R228
(FS)
1K
V1
C213
+
D202 1000U
V2
1N4003 25V
R229
(EL)
1K (105C)
R224
C219 C218 C214
+
R253
5.6
5600P 5600P 100U
180 1/4W
100V 100V 35V ZD202
DYV+
R250 R251 R252
(PE) (PE) 1/4W (EL) 20V
1.8K 1.8K
180
C216
DYV-
C220 1/4W
0.1U
R274
0.1U R226
100V
33K
100V 270
(PE)
(PE)
V+
R275
C215
27K
470U
R225
16V
+
1
(EL)
1/2W
TR201
100
Fig11 Vertical output circuit
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INP
INN
V-OUT
GND
VP2
VP3
VP1
7
6
5
4
3
2
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V772 CRT Monitor Service Guide
Circuit Operation Theory
Switching Power Supply Operation Theory
1. General Specification
Input Voltage: 90~264VAC (FULL RANGE)
Input Frequency: 47~63Hz
Output Requirement: Dc Output
+6V
+13V
+78V
+45V
-10V
2. Block Diagram
DEGAUSS
CIRCUIT
OUTPUT
RECTIFIER
RECTIFIER ISOLATION
AC RFI SWITCHING
AND
& TRANSFOR OUTPUT
INPUT FILTER ELEMENT
FILTER
FILTER -MER
FEEDBACK
CONTROL
POWER
CIRCUIT
SAVING
CONTROL
3. Circuit Operation Theorem
3.1 RFI FILTER
L
C603
L602 L603
2200P
C601
250V
0.47U
3 4
(Y)
R601
250V
C602
(X)
2200P
1 2 L604
250V
(Y)
N
FG
This circuit designed to inhibit electric and magnetic interference for meet FCC, VDE, VCCI standard
requirements.
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Circuit Operation Theory
3.2 Rectifier and filter
L
D602~D605
20D6 * 4
3
~
4 1
AC INPUT
-+
C612
~2
+
220U
DC OUTPUT
400V
N (EL)
When power switch is turn on, the AC voltage is Rectifier and filter by D603~D606, C612. The DC
output voltage will be 1.4*(ac input)
3.3 switching Element and isolation transformer
FR701
T601
C53
B61
6
11
(SHORT)
R604
C613
82K 0.01U
1KV
2W ZD601
(D)
C50 (OPEN)
12
D610
C614 D613
UF4007
(OPEN) (OPEN)
FR702
10
L606
1
C51
(SHORT)
(BEAD)
L608
D608
C608
RGP10D
47U
(BEAD)
8
25V
C624
(EL)
220P
Q602 1KV
FS14SM-12
(D)
L607 15
R619
(BEAD)
D614
R608 470
UF4007
18
20K 2W
R607
*
0.15
16
2W
FR704
(SHORT)
13
EGP30B
9
R611
1K
In a flyback converter operated in the discontinuous mode, the energy stored in the flyback
transformer(actually an inductor) must be zero at the beginning and end of each switching
period.
During the "ON" time, energy taken from the input is stored in the transformer when
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Circuit Operation Theory
the switching transistor turn-off, this stored energy is all delivered to the output.
3.4 Output Rectifier and filter
The structure of each output is illustrated as below
T601 D1 L1
+ +
C1 C2
since the transformer T601 acts as a storing energy inductance, diode D1 and capacitor C1 are to
produce a dc output and additional L1, C2 to suppress high-frequency switching spikes.
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Circuit Operation Theory
3.5 Control circuit
C625
1N4004 R607
(OPEN)
0.15
2W
76
8
R611
VREF VCC OUT
1K
3
R613 R614
D611 IC601 ISSEN
36K 100K
1N4148 UC3842
*
4
R/C
COMP FB GND
C615
D612
2200P 1 2 5
1N4148 C619
ZD602
50V IC603
*
MCR100-3 24V
(PE)
0.022U
A
C620
50V
C618
R622 820P
C617
(D)
R612 0.01U 510
+
50V
4.7U
47 50V
(D)
50V R615
K G
(D)
+C627
(EL) 51K
R620
10U
10K 50V
(EL)
C616
R616
0.01U
10K
100V M603
+6.5VA
(PE)
R738
82
1/2W
ZD603
4 1
5.1V
M604
The current mode control IC UC3842 is used in the switching power supply which function of each
pin
described as follows.
pin 1 : Error amplifier output pin 5 : Ground
pin 2 : Error amplifier reverse input pin 6 : Output
pin 3 : Current sense pin 7 : VCC
pin 4 : OSC sawtooth pin 8 : Reference Voltage:5V
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Circuit Operation Theory
When power is initially applied to the circuit, capacitor C626 charges through R624, R623, ZD601.
When the voltage across C607 reaches a level of 16V, IC601 is turn-on the +5Vdc will be
set up at pin8 then R613, C615 generate a fixed frequency sawtooth wave to pin4, at this time
MOSFET will be driver by pin6 with square wave the pulse width of square wave is decided by
pin2, pin3 is current feedback control, It will to sense MOSFET current. The D613, D612, R614,
C617 are soft start components to avoid the duty too large when power starts up.
3.6 Feedback circuit
This power supply is a primary feedback circuit. It used IC601 for voltage regulation
, The output voltage differential signal will be detected and sensed to the pin2 of UC3842 for
comparison then the duty cycle of MOSFET will be decided to control the output voltage.
0.15
(OPEN) 50V (D)
2W
1
76
R611
8
VREF VCC OUT 1K
3
ISSEN
R614 D612 IC601
100K 1N4148 UC3842B
4
R/C
ZD602
COMP FB GND
24V
D613
1 2 5
1N4148
C619
0.022U
C620
50V
C617 C618
820P
(D)
+
10U 0.01U 50V
50V 50V (D)
(EL) (D)
R615
560K
C609 (EL)
0.22U 50V
R616 VR601 R617
57.6K * 2K 9.09K
R618
(OPEN)
* *
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V772 CRT Monitor Service Guide
Circuit Operation Theory
3.7 DEGAUSS CIRCUIT
+12V
RL601
43
1
DEGAUSS
D740
1N4148
2
6 5
R741
2.2K
Q740
H945
TR602
2R9M
M602
B53
2P
L610
L611
3T
3T
L604
L603
180UH
180UH
C604
(OPEN)
250V
(Y)
This circuit has the function of auto degaussing and manual degaussing. When power supply is
switched ON it is auto degaussing stage. When user make the selection of the manual degaussing
function in OSD, the degaussing current will flow through coil to degauss the screen of monitor.
TR602 is a PTCR to control degaussing coil current
3.8 power saving control
Mode H-sync V-sync LED Power Rating
Normal Normal Normal Green jþ
100
Stand-by None Normal Amber f"
5W
Suspend Normal None Amber f"
5W
Off None None Amber f"
5W
When both of the H-sync and V-sync are none, the power supply +14v output will be cut-off.
The power input will be under 5W.
When the H-sync or V-sync is none, the power supply +14v output will be cut-off. The power input
will be under 5W.
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Circuit Operation Theory
30. Video CKT
ÿ
V772 VIDEO C.K.T. BLOCK DIAGRAM
31. OSD Preamp CKT:
(a) AS shown in the block diagram:
The R/G/B signals will generate an enough amplitude of Vpp to show up on the
CRT screen after the amplification of two amplifiers. The first one, preamp CKT,
process the signal and mix up the OSD, and the second one does the power
amplification.
(b) OSD preamp IC101, LM1269, will output the R.G.B signals separated. The R.G, B
driver will control the gain of these three guns individually to approach the white
balance of CRT.
(c) The signal H-Blank is to let the output of LM1269 down to 0.2V while non-display
duration. Then the CRT driver CKT will generate a level higher than Black Level. (i.e.
SYNC TIP), therefore the video signal will be blanked in order to prevent the fold over
to occure while adjusting H-phase. Besides, the SYNC TIP is used for
the DC Restoration of cascode CKT.
(d) LM1269 is equipped with OSD mixer, when signal CUT is Low, the output of
LM1269 is video signal when signal CUT goes high, the output will be OSD signal.
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32. CRT DRIVER CKT:
Output stage adopts CRT driver LM2468 to amplify the signal which has been
recessed by LM1269 to a enough amplitude of Vpp, then display on the CRT. The IC
contains three high input impedance, wide band amplifiers which directly drive the
RGB cathodes of a CRT. The gain of each channel is internally set at -15 and can
drive CRT capacitive loads as well as resistive loads presented by other application
limited only by the package s power dissipation.
33. DC Restore CKT:
(a) The video signal amplified by the output stage is coupled to CRT by way of AC
coupling. So DC restoration CKT is needed to do the white balance adjustment.
(b) This DC restoration circuit adopts SYNC TIP CLAMP, in the duration of
SYNC TIP the capacitor charges, and the capacitor discharge in the other time.
The Black Level is kept to the level of DC restoration set by UC.
34. ABL CKT: (Auto Brightness Limit)
ABL is a protection circuit. When the anode current goes higher than the setting
value of ABL circuit. ABL will pull down the voltage of contrast to limit the anode
current. This is helpful to protect CRT.
35. H-BLANK CKT:
Affair the collect pulse comes from FBT being shaped and inverted, it will be sent
to preamp CKT and used as the H-Blank.
36. Brightness, V-blank, change mode blank, spot killer CKT:
(a) About the cut off voltage , while the voltage, cathode to G1 , over the cut off ,
voltage, the picture will disappear, If cut off voltage of the CRT is
set at 110V and the black level of cathode is 60v, the picture won t show,
the signals higher the black level once the G1 voltage is lower than-50v.
(b) As described above, we may using the voltage control G1 as the brightness
control. Generally the G1 control range is about 10~15V if the raster
brightness is form 0 to 0.8 ft-L.
(c) Similarly, we may overlap a negative pulse of vertical duration on the G1
voltage to prevent the vertical retrace line from showing on the picture , This
is to keep the voltage cathode to G1 over the cut off voltage during the
period of vertical retrace.
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Circuit Operation Theory
(d) In order to avoid the picture occur transiently while change mode, pull
down the G1 voltage and let the voltage cathode to G1 over CUT OFF voltage.
This will make the picture blanking.
(e) While monitor turned off , the discharge speed of high voltage circuit is slow
since there is no deflection scan act on the electronic beam, a spot which will
destroy the phosphor of CRT. So the SPOT KILLER circuit will generate a
negative voltage higher than CUT OFF to the G1 to beam this is to protect
the CRT.
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ACER V772 MICROCONTROLLER CIRCUIT OPERATION THEORY
1. Introduction:
This model, V772, will support powerful OSD function to help end user fine adjustment. The
Microcontroller circuit of the V772 can determine what mode it is by detecting the frequency of
horizontal and vertical synchronous and the polarity of horizontal synchronous, and provide DC
voltages to control the picture and save the adjusted value into the EEPROM by using the OSD,
"On Screen Display control", that means the user can get any information of the picture display or
adjust it and save the status values into the EEPROM by choosing and pressing the proper key
according to the indication of the OSD. In addition, user can press i-key to do auto-calibration.
2. Block diagram :
The major parts of V772 Microcontroller circuit are MCU, EEPROM, OSD IC, and Auto
Calibration Module. The circuit block diagram is shown as below.
MCU(MTV112)
Degaussing
Detecting the
Hsync
Blanking
input signals
Vsync
SC0 - SC2
of H,Vsync &
H-polarity
H-polarity. OSD IC
EEPROM
Display OSD
and output
Preset mode data,
Searching for
PWM to video
User saved mode data.
the same saved
circuit
mode timing
PWM
Reset circuit
To deflection
with the input
output
circuit
signals and
12MHz Crystal
get the data.
AP3113
circuit
DCLK
Auto
HBNK
Control Panel
DATA Calibration
VBNK
Checking if the
Module
RGB
5 keys input
valid key be pressed
Signal
i-key
and do key function.
Left,Right,Enter,Exit
PC
(UART) External
RS232
adjustment
auto alignment
function
program
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Circuit Operation Theory
3.MCU and the peripheral circuit operation theory:
3-1.MCU function:
The MCU is MTV112, it is an 87C51 with PWM output controlled microcontroller, after
power on, the reset circuit output a "High" to "Low" signal (>40mS) and the 12MHz crystal
oscillated circuit working, the MCU begin to manages the following functions,
(1) To detect mode and output proper SC0, SC1 and SC2 to deflection circuit.
(2) To check if there is the same saved mode in the EEPROM and get the data to transfer into
DC voltages by PWM output and RC filter circuits to control the picture, color, contrast
and brightness.
(3) To check if there is the valid key be pressed and do the key function.
(4) To memorize mode timings and any adjustable parameters of the picture into EEPROM.
(5) To output data to OSD IC for making an "on screen display control" menu.
(6) The inner registers and PWM output of MCU can be controlled by the external PC
alignment program.
(7) To calibrate the size, position, and geometry of the picture by pressing i-key. It will be
placed right size and position.
3-2.How to detect mode timing:
Only when the mode timing input is stable, we can adjust the picture and check the
horizontal and vertical sync frequency by the OSD menu, and the mode timing input mean the
horizontal sync signal and the vertical sync signal.
(1) The vertical sync frequency measurement:
We use the base timer, it can generate a count during a fixed time, this fixed time is
12/12MHz and we call it "Time base", so when the first vertical sync generated, we enable
the base timer, and the next vertical sync generated, we disable the base timer, and we only
need to calculate how many counts are during a vertical sync period. The formula is
Vertical sync frequency
= FV
= 1 / Vertical sync period
= 1 / [Counts * (Time base)]
==> Vertical sync frequency = 1000000 / Counts
(2) The horizontal sync frequency measurement:
We use the event counter for calculating how many counts are during a long fixed time,
because the vertical sync period is longer than the horizontal sync period, we can enable the
event counter when the first vertical sync generated and disable the event counter when the
next vertical sync generated, this time, we can get the horizontal sync counts during a vertical
sync period.
The formula is Horizontal sync frequency
= FH
= Horizontal sync counts / Vertical sync period
==> Horizontal sync frequency
= Horizontal sync Counts / Vertical sync period
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3-3.What are the valid key functions for user:
There are four keys on V772 control panel. They are "Left," "Right," "Enter," and "Exit."
There are used for OSD controlling. "Enter" for entering sub-menu of main menu, "Exit"
for escaping to main menu from sub-menu or leaving OSD menu, and "Left," "Right" for
adjusting the bar value.
Except the OSD basic key functions, the user can only press "Right" for brightness
adjustment, or "Left" for contrast adjustment.
3-4.How to memorize the timing and adjusted data:
The EEPROM of V772 is 24C08, it has 1024 bytes memory size and communicates with
MCU by two wires of I2C bus, one wire is "SCL," the other is "SDA".
The MCU send clock and data to EEPROM to do "Write" function and send clock and
receive data from EEPROM to do "Read" function by these two wires.
We define three parts of storage area. One is for the storage of the factory preset data,
another is for saving user adjusted data, the other is for common settings area where stored
the data of the OSD color temperature settings, contrast and brightness value.
3-5.How to display the OSD menu:
The OSD IC of V772 is AP3122 which is developed by vender, it receives the data of the
OSD fonts and attribute what we want to display on the screen from the MCU by 2 wires of
communication, and exports OSD window data and PWM volume to the VIDEO circuit, the
block diagram is shown as below,
OSD IC (AP3114)
MCU(MTV112)
SDA
(1)Send data to
Shift receiving
Output to
PWM
RAM for OSD SCL
register and decoder.
the VIDEO circu
output
fonts or
attribute.
(2)Send data to
ROUT
Control Fonts
Control RAM
GOUT
register generator
registers
BOUT
s
for PWM ouput
FBKGC
or OSD window
VSYNC
VCO circuit
HSYNC
(H-BLANK,HBNK)
3-6.How to execute the auto alignment function:
The MCU MTV112 supports the UART function, it has 2 I/O serious ports, one is the
receiver, the other is the transmitter, they are connected with an interface to PC and PC can
execute alignment program by RS232 communication to send the formatted data to the MCU
for adjusting any adjustable parameters of the picture and saving the adjusted values into
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EEPROM. By this way, we can get the products with the same quality and reduce the
manufacturing time.
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