W510

3

3

2

2

1

1

LNA

LNA

LNA

TX_HB

DCS/PCS OUT

GSM850/

B+

15

11, 20,

26

25

GSM900 OUT

Se

ria

l

Inte

rface

D1

E3

G3

1

U200
PA + Antenna Switch

6

13 8

E1

D2

F1

DBG_DATA

MS

MDI

DRI

VR

AM

P

Y100

26MHz

2, 4

1

1800 MHz

1900 MHZ

850 MHz

900 MHz

(P

A P

o

wer

Contr

o

l)

J100

Mechanical

Antenna Switch

Internal
Antenna

M100

RES

E

T

B

US_

E

U

R

O

TX_

A

N

T

_S

W_

EN

TX_

S

T

A

R

T

F3

(T

ra

ns

m

itt E

n

able)

RF_CLK

RF_DATA

RF_CS

B3

PA Control

B9

C2 A2

E2

GPIO

(U100 Control Bus)

ADC
Voltage

Reg.

VM_REG
VBUCK
RF_REG

J5, J8

H2
B4

(VCC’s from Atlas)

A4

1Mbit RAM

DSP

DSP

UltraLite
104 MHz

DSP Peripherals
accelerator, encryption
Timer, Interupts

Shared Memory

MCU

52 MHz

ARM7

MCU

26 MHz
Oscillator

Memory

Memory

SIM

Interface

External

Interface

Memory

N10

Clock Generator

SPI

Power

NEPTUNE LTE2

U800

W10

U9

T8

GPIO

L1 Timer

U6

U8
V7
W9

UART / USB

Interface

Keypad
Interface

On

Off

SIM DIO

SIM_RST

SIM_CLK
SIM_PD

VSIM_EN

VBUCK

(VCC + 1,875V)

(from Atlas )

SIM_REG

(to Atlas)

IO_REG

J4
L1

K3

R1
M1

K2

(from Atlas )

PERIPH_REG

EGSM: CH 37 -- 942,4Mhz

DCS: CH 700 -- 1842,8MHz

PCS: CH 661 -- 1960MHz

RX MID CHANNELS

GSM: CH 62 -- 947,4 MHz

850: CH190 -- 881,6

MQSPI
Display

U701

EB1B
EB0B

OEB

R_WB

CS1B

ADDRESS BUS

DATA BUS

K16

J19

G17

T16

BURSTCLK

LBAB

CS0B

ECBB

V17

T19
L16

N18

A1-24

D0-15

64 MB Flash

RESET OUT

F3
C2

G8

E5

F5,D5
J2,H1,H8

G7

C6

D3

F4

D6

HS INT

C14

PA12

16 MB SRam

(from Neptune)

MEMORY

U13

BB

_SA

P

_T

X

B

B

_

S

AP

_R

X

BB

_SA

P

_

F

S

BB

_S

A

P

_

C

LK

B13

B12

A12

D13

(fram

es

y

n

c)

(cl

o

ck)

CLK

13 MH

z

W13

C15

C16

D15

A16

BB

_

S

P

I_C

LK

BB

_S

PI_M

O

S

I

B

B

_S

PI_

M

IS

O

AU

L_

CS

Neptune /Atlas

Communication

T11

V12

V11

W12

ST

AN

DB

Y_1

_5V

G8

ST

A

N

DB

Y

CL

K 32

KH

Z

E3

B14

AU

L_

INT

RE

SET

B

V13

(13 M

H

z)

(W

a

tchdog)

WD

OG

OW

B

W11

O

n

e W

ire d

at

a from

B

at

te

ry

(from

M

122

0)

US

B_V

P

IN

U

S

B

_

XR

XD

US

B_V

P

O

U

T

US

B_V

M

IN

U

S

B

_

TX

EN

B

US

B_V

M

O

U

T

B16

A17

Neptune /Atlas

USB/ RS232

Communication

(t

o At

las

)

RE

SET

O

U

T

W5

(t

o U701)

(from/ to Neptune

Serial Audio for Ringtone

and Voice Audio)

BL

UE

_R

X

B

L

U

E

_T

X

B

L

U

E

_R

TS

B

B

L

U

E

_C

TS

B

N17

N13

V16

D16

(from/ to U301 BT, J1300

Neptune - BT - Neptune

Communication and Wakeup)

BLU

E_

W

A

KE

B

B

L

UE

_H

OS

T_W

A

K

E

B

D19

B15

KB

R0

-7

KB

C

0

-1

F3....

G3.....

Timer

GPIO

Interface

BaseBand

Port Interface

Serial Audio

(tx)

(rx)

MQSPI

One

Bus

Wire

UART2

Universal

Asynchron.

Rx /Tx

BT

CS2B

W19

W8

T10

GA

_

INT

9

LB_

HB

C3

TX

_E

N

2

3

4

Power and

Antenna

Control

16

A1

3

K5

K4

LNA

TX_LB

L8

L10

2

4

(fro

m A

tl

as

)

VBUCK

E4...

(from

Atlas

)

U806

Level

(t

o Atlas

)

P2

LCD_RS

P1

LCD_SDATA_DATA7

M4

LCD_CLK_DATA6

N3

LCD_CS

L3...

LCD DATA (0 - 5)

(LCD Control to J1300 )

Hall Effect

Shift

(VCC + 1,575V)

REF_REG

E2

PC0

U11

(t

o

J1

300

)

(VCC + 2.775V)

C5,A11, ......

(VCC + 2.775V)

H1

L19, V2, ....

TOUT12

U10

(Bias output for THERM signal)

(Clock )

(Reset )

(Data In /OUT)

(T

rans

mit

t E

n

abl

e

)

(Clock )

(Chip select)

(Data In /OUT)

10

(fro

m A

tl

as

)

T18

(Trans Flash Enable to U970 )

EL_EN

N9

(EL Backlight Enable to U1370)

17

IPC

_

BC

M

B2

VCO_REG

18,31

FL109

FL108

4

4

2

2

FL100

Quadband Saw Filter

4

3

Low Band

850MHz

Low Band

900MHz

High Band

1800MHz

High Band

1900MHz

6

1

and Matching

14

15

12

13

8

9

10

11

K12

L12

G12

H12

A12

B12

D12

E12

DC
Correct

LPF

÷

4

90°

÷

2

90°

÷

2

÷

2

LPF

LPF

Transmit
Modulator

TX CP

RX CP

Phase Modulation

Amplitude Modulation

TX VCO

RX VCO

VCO_REG

C10

IO_REG

C1

Digital Radio

Receiver

Synt

hesize

r

RX /

TX

Cl

ock

RX /

TX

In

/ O

u

t -

P

u

t c

o

n

tr

o

le

r

SYSCLK

G2

(RX Data)

(TX/RX Enable)

(TX Data)

(SPI readback)

J1

BT_CLK

J3

BT_CLK_EN

G1

SYSCLK_EN

VD

ET

EC

T

A4

REF1V2

C5

D18

GA_SPI_CS

TO

U

T

9

T7

(from / to J24_DB)

TX_EN_BM

V8

(to Atlas U900)

(Flip Open/ Close

Detect)

1

6

PERIPH_REG

U1220

Servive, Engineering & Optimization

2007.2.27

LEVEL 3 AL Block Diagram

Rev. 1.0

W510

Page 1of 3

Key-Matrix
0-9,*,#
Navigation,
Smart,
Volume

(from

U

600

vi

a

J1

3

00)

D14

LCD_RD

Transceiver

U100

Revision Overview
Rev. 1.0: Initial Block Diagram

(only used in Engineering debug mode

1. IPC: Input Power Control mode - for EDGE mode

2.BCM: Bias Control mode - for GMSK mode

(PA gain is fixed and PA input power varies)

(PA gain varies according to power step and fixed input PA power)

PA Power Control selection via VRAMP, TX_HB and TX_LB

- not for Service)

21, 30,

14

PC

13

A15

(To J1300)

(to U400)

(from Atlas)

A14

PE12

(to U901)

input

output

Ant Port Conn

Pin 8

Pin 9

Pin 13

1

0

0

TX_LB

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

TX_HB

PCS

DCS

EGSM

GSM850

Revision Overview
Rev. 1.0: Initial Block Diagram

Servive, Engineering & Optimization

2007.2.27

LEVEL 3 AL Block Diagram

Rev. 1.0

W510

Page 2of 3

W510

41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9

42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10

LCD_DATA4

LCD_DATA1

GRAPH_REG

CAM_REG

LCD_DATA2

IO_REG

LCD_DATA3

LCD_DATA0

LCD_DATA5

HAND_SPKR-
HAND_SPKR+

LEDR1

BB_SAP_TX

BB_SAP_CLK

BB_SAP_FS

PERIPH_REG

GND

LCD_CS

PCO

LCD_RS
LCD_RD

7
5
3

g1- g4, 1, 2

GND

8
6
4

GND

(from Atlas)

J1300

Main CONNECTOR

Main Connector

GND

GA_INT

VBUCK

GND

(clock)

CLK_13MHZ

V12

CLK_32KHZ_2_7V

P16

TIMER

WDOG

K10

CNTL.

PRI SPI

LOGIC

Logic

J

1

6

,J

4

,J

1

5

..

...

...

S

w

it

cher

BB

_SP

I_C

LK

BB

_SP

I_M

OS

I

BB

_SP

I_M

IS

O

AUL

CS

U1

8

U1

6

T1

8

T1

7

R5

Interface

USB

Y900

V17

D12

RTC_BATT

V16

B+

HAND_SPKR-

HAND_SPKR+

T6

R7

T9

P9

V10

U8

ON1

B

F14

B4

E3

F3

U900

ATLAS UL

ON

LOGIC

OWB

THERM

P13

THERM

BATT+

D14

GND

CHRGCTRL

B16

VBUS

S

G

D

CHARGE

Charger

BATT CONN.

CNTL.

LED

E12

B

B

_S

AP

_FS

BB

_S

A

P

_

C

LK

BB

_S

AP_

T

X

BB

_SA

P

_

R

X

CODEC

16 BIT

STEREO

(tx) (rx)

ALERT-

ALERT+

STANDBY

F12

(to Neptune and U400 BT)

A

U

L_

INT

N1

4

RESETB

(from U800)

Neptune Atlas

Communication

UID

H8

Q904 (M3)

1

2

B+

B12

BATTFET

Battery to BPLUS

US

B_V

P

IN

U

S

B

_

XR

XD

US

B_V

P

O

U

T

US

B_V

M

IN

U

S

B

_

TX

EN

B

US

B_V

M

O

U

T

USB/RS232

(communication)

B2

C4

F4

B1

,.

.

B3

E4

MIC_INM

MIC_BIAS1

Det.

Stereo

B

oos

t 300mA

B4

,.

..

.

S

w

it

cher

B

u

ck 350

mA

F1

6

( 1,

87

5V

)

VBU

C

K

H

2

,...

( 2

,77

5V

)

P

E

R

IPH

_

REG

U6

( 2,

7

75V

)

AU

D_ R

E

G

( 1,

27

5 )

G

R

AF

X_

R

E

G

K1

7,

..

.

H4

H3

( 2,

77

5V )

RF

_

R

E

G

L1

6

( 1,

57

5V

)

RE

F_

REG

N5

( 1,

8

/ 3V

)

SI

M_

REG

VS

IM_

E

N

K1

1

VBUS

CONTR.

AD

C15

PE

RIP

H

RE

G

(B

ia

s)

(One Wire Bus

to Neptune)

BPFET

VBUS to BP

Switch

(Main Source

for Atlas)

(from Mini USB Connector)

Main Charge Path

B+ support without Ext Charger
B+ support with Ext Charger

Color definition only for this section !

D903

BB_SAP_TX

BB_SAP_RX

BB_SAP_FS

BB_SAP_CLK

(framesync)

Bluetooth

U400

C7

BLUE_WAKEB

C8

BLUE_HOST_WAKEB

C6

BLUE_RX

E5

BLUE_CTSB
BLUE_RTSB

E7

BLUE_TX

E4
E8

BT_RESET_B

E3

(from/ to Neptune

Serial Audio for Ringtone

and Voice Audio)

PERIPH_REG

B3......

B+

H6

BT_

AN

T

25

Strip Line

Antenna

(on PCB)

F6

VIB

_

R

E

G

(from Neptune)

NeptuneAtlas

Neptune Atlas

USB/ RS232

Communication

(Battery Sense)

(VBUS Sense)

CONV.

D/A

CLK_32KHZ

(from Atlas)

1

(from Atlas)

( 1,3

V

)

(from/ to U400 BT,

Neptune - BT - Neptune

Communication and Wakeup)

Internal

MIC

PCB
Pads

TX_EN_BM

U15

(from Neptune, Tx Mode indication for Atlas)

( 2,

77

5 )

IO

_R

E

G

( 2,

7

75 )

CA

M_

R

E

G

( 5,

5V

)

VB

O

O

S

T

2
3

VBUS

1

4

5

(to Charging Circuit)

G1-G4

(Shield)

CLK_32KHZ

R16

D-

D+

VBUS 5V

Pass FET

VBOOST

VBUS

D2

(PPD device support)

(from J1230)

(to J1300)

to V

ibr

ator

VIB REG

P2

Mo

to

r

REF REG

RF

R

E

G

PE

RI

PH

IO R

E

G

AU

D

IO

REG

IO REG

GR

A

P

H

REG

CAM

E

RA

REG

P18

DIG

REG

4

Microphone

R3

P4

R4

13 Bit

Handset

Amplifier

(to J1300)

Q91

0

VC

O

REG

VC

O_D

R

V

(M

ain Sour

ce-

f

rom Q

904)

( 2

,775

V

)

V

C

O

_RE

G

V2

SIM_PD

T14

CHRGRAW

S

G

Q903 (M4)

Q905 (M1)

G

S

R910

R911

3

Switch

B14

CHRGISNSP

E15

(Current Control)

Q906 (M2)

(only

us

ed i

n

Atlas

)

C6

DISP_LED1

(t

o Ne

p

tune)

(t

o J

2,

J1000, Q2020)

(t

o Neptun

e

am

d J

2

7)

(t

o U250)

(t

o J

2, J

1

000, J

2000)

(t

o AL

+

R

F

))

(t

o U50,U25

0)

Bluetooth

Mini USB

Charger and Power-

source Control

(to Neptune, U200 & U970)

(to Neptune)

(from Atlas)

(from Neptune)

TOUT12

(Bias Voltage from
Neptune)

(Accessory Detection signal)

(from Acesory Connector)

(EXT Power)

(EXT Power)

Det.

Headset

R9

40

3

4

1

SAP

Supply

Amplifier

Alert

Amplifier

Headset

Amplifier

EMU

J1390

NC

ALERT

NC

SD0

SD2

47
45
43

SD3

GND

49

50
48
46
44

CLK_32KHZ_2_7V

GND

GND

SDCLK

GA_SPI_CS

(from Atlas)

2

2

BA

TT

+

M1220

2

3

1

4

B

+

Sens

e

(t

o J

2, J

1000, D1

000

BATTISNS

F13

(Batt Current)

(Charger Current + )

( 1,

8V

)

GS

DR

AM

_RE

G

1

2

U14

CHRGLED

L10

(from J1300)

SYSCLK_EN

P14

(to U100)

B6

DISP_LED2

D6

DISP_LED3

F8

DISP_LED4

K1

6

(2,

7

75V

)

VM

_R

EG

(t

o U250)

VS

IM

RF

R

E

G

(f

ro

m

U800)

(t

o AL

+

R

F

))

(to

A

L

+

R

F

))

J3500, U1

501)

M1221

R17

REF REG

( 1,

2

V

)

RE

F1V

2

(t

o U250)

U901

R985

PERIPH_REG

PE12

(Headset detect Enable from Neptune)

(Bias from Atlas)

(100K Headset

from/ to Neptune)

(Control Bus for ATI

VBUS

SDCMD

(SD Card Command to/from U600)

(from D601)

SD1

(from Atlas)

(LCD Control from Neptune)

(from U1370 for ATI core supply)

(interupt from U600 to Neptune)

(LCD Data from Neptune)

(SD Card Data

from/ to U600

STANDBY

C4

BT_CLK_EN

D7

(to U100)

A7

B6

C5

FL

401

H1
H2

via FL1360)

EL_EN

TP12

TP13

VBOOST

8

3

10

U1370

EL LAMP Driver

E2

BT_CLK

(from U100)

detect Resistor)

Headset detect circuit

R1370

2

5

4

E3

TOUT9

(from U800, shutdown BT)

MK1200

P1261

FL1390

3

4

2

1

VR1

39

0

VR

13

91

VR

13

92

1

Neptune /Atlas

Communication

F1

7

BU

CK

OUT

D

R9

41

1

2

32.768KHz

D9

LEDR1

(to J1300)

C2

A1

B1

input

A1

B1

output

C2

L

H

H

H

L

L

L

X

Z

R1301

R1301

R1301

R1301

LCD_SDATA_DATA7

LCD_CLK_DATA6

1

2

3

4

5

6

7

8

R1300

R1300

R1300

R1300

1

2

3

4

5

6

7

8

CHRGLED

DISP_LED1

DISP_LED2

DISP_LED3

DISP_LED4

(from Atlas)

VBOOST

(from Atlas)

BB_SAP_RX

GSDRAM_REG

(from Atlas)

(LCD Data from Neptune)

(from U600)

J1350

SIM

Connector

1

2

3

4

GND

MSIM_PWR

MSIM_SDCLK

SIM_RST

(from Neptune)

5

6

7

8

SIM_DIO

(from/to Neptune)

SIM_CLK

MSIM_SDCMD

MSIM_SD0

(from Neptune)

J1360

TF Card

Connector

1

2

3

4

5

6

7
8

SD2_OUT

SD3_OUT
SDCMD_OUT

TF_PWR

SDCLK_OUT

GND
SD0_OUT
SD1_OUT

F

L

1

360

7

8

9

10

11

12

6

5

4

3

2

1

SD2

SD3

SDCMD
SDCLK
SD0

SD1

(from FL1360 SD0_OUT)

(from FL1360 SDCLK_OUT)

(from FL1360 SDCMD_OUT)

U970

TF_PWR

C1

B2

GND

A1

PERIPH_REG

C3

B+

A3

SYSCLK_EN

LDO for TF Card

(from Atlas)

(from U970)

(from U600)

Revision Overview
Rev. 1.0: Initial Block Diagram

Servive, Engineering & Optimization

2007.2.27

LEVEL 3 AL Block Diagram

Rev. 1.0

W510

Page 3of 3

W510

41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9

42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10

LCD_DATA4

LCD_DATA1

GRAPH_REG

CAM_REG

LCD_DATA2

IO_REG

LCD_DATA3

LCD_DATA0

LCD_DATA5

HAND_SPKR-
HAND_SPKR+

LEDRE0

BB_SAP_TX

BB_SAP_CLK

BB_SAP_FS

PERIPH_REG

GND

LCD_CS

PCO

LCD_RS
LCD_RD

7
5
3

g1- g4, 1, 2

GND

8
6
4

GND

(from Atlas)

J601

Flip CONNECTOR

Hinge Flex Connector

GND

GA_INT

VBUCK

GND

SD0

SD2

47
45
43

SD3

GND

49

50
48
46
44

ATI_32KHZ

GND

GND

SDCLK

GA_SPI_CS

(from Atlas)

from/ to Neptune)

(Control Bus for ATI

VBUS

SDCMD

(SD Card Command from U600)

(from D601)

SD1

(from Atlas)

(LCD Control from Neptune)

(from U1370 for ATI core supply)

(interupt from U600 to Neptune)

(LCD Data from Neptune)

(SD Card Data

from/ to U600

via FL1360)

LCD_SDATA_DATA7

LCD_CLK_DATA6

CHRGLED

DISP_LED1

DISP_LED2

DISP_LED3

DISP_LED4

(from Atlas)

VBOOST

(from Atlas)

BB_SAP_RX

GSDRAM_REG

(from Atlas)

(LCD Data from Neptune)

(from U600)

FL600

1

4

8

5

TP_HS+

TP_HS

VR601

VR602

GND

GND

D601

VBUS

VBOOST

1

2

3

4

LEDRED

RE

D

GRN

J604

G1- G2,

2

8
7
6

5
4

3

1, 9

GND

PERIPH_REG

VBUCK

CLI_DATA

CLI_CLK

CLI_RS

CLI_RESET

CLI_CS

(from U600)

CLI Display Connector

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10

LCDC_RED5

PERIPH_REG

7
5
3

G1- G4

GND

8
6
4

J600

Main Display Connector

GND

VBUCK

DISP_LED1

DISP_LED2

DISP_LED3

DISP_LED4

VBOOST

2

1

LCDC_RED4

LCDC_RED3

LCDC_RED2

LCDC_RED1

LCDC_RED0

LCDC_GREEN5

LCDC_GREEN4

LCDC_GREEN3

LCDC_GREEN2

LCDC_GREEN1

LCDC_GREEN0

LCDC_BLUE0

LCDC_BLUE1

LCDC_BLUE2

LCDC_BLUE3

LCDC_BLUE4

LCDC_BLUE5

GND

GND

GND

LCDC_OE

LCDC_GS

LCDC_LS

GND

LCDC_DCLK

LCDC_SDI

LCDC_SD

LCDC_CS

LCDC_SCLK

LCDC_RESETB

LCDC_SDO

23
21
19
17
15
13
11
9

24
22
20
18
16
14
12
10

CAM_RESET

CAM_D3

7
5
3

G1- G4

GND

8
6
4

J602

Camera Connector

GND

VBUCK

CAM_PWRDWN

GSDRAM_REG

GND

CAM_VSYNC

2

1

CAM_REG

CAM_HSYNC

CAM_D6

CAM_D4

CAM_D2

CAM_D1

CAM_D0

CAM_SDA

CAM_SCL

GND

CAM_CLK_OUT

CAM_CLK_IN

GND

CAM_D5
CAM_D7

GND

ATI

GPIO

LCDC_CS

LCDC_SDO

LCDC_SCLK

CLI_RESET

CLI_CS

LCDC_RESETB

CLI_CLK

CLI_RS

CLI_DATA

LCDC_SD

GND

LCDC_SDI

GND

CAM_PWRDWN

CAM_RESET

BB_SAP_TX

BB_SAP_CLK

BB_SAP_FS

BB_SAP_RX

B2

C1

B3

B1

D5

D1

D4

E5

E2

F1

G2

G1
H2

H1

L2

W2

V1

V2

V4

SD0

SD2

SD3

SD1

SDCLK

SDCMD

IO_REG

D19

D15

C19

B19

E19

B18

D14

CAM_D3

CAM_D6

CAM_D4

CAM_D2

CAM_D1

CAM_D0

CAM_D5

CAM_D7

CAM_CLK_OUT

CAM_CLK_IN

CAM_VSYNC

CAM_HSYNC

CAM_SDA

CAM_SCL

W9
R6

T6

T7

V6

R7

T8

R8

R9

R5

W5

GND

GND

V8

W8

W6

W7

V7

LCD

LCDC_RED5

LCDC_RED4

LCDC_RED3

LCDC_RED2

LCDC_RED1

LCDC_RED0

LCDC_GREEN5

LCDC_GREEN4

LCDC_GREEN3

LCDC_GREEN2

LCDC_GREEN1

LCDC_GREEN0

LCDC_BLUE0

LCDC_BLUE1

LCDC_BLUE2
LCDC_BLUE3
LCDC_BLUE4

LCDC_BLUE5

LCDC_OE

LCDC_GS

LCDC_LS

LCDC_DCLK

P1

R2

R1

T1

P4

N4

P2

N5

N1

M4

M5

M1

L5

K5

L1

L4

J5

N2

H4

K4

M2

J4

CPU

GA_INT

LCD_DATA4

LCD_DATA1

LCD_DATA2
LCD_DATA3

LCD_DATA0

LCD_DATA5

LCD_CS

LCD_RD

GA_SPI_CS

LCD_SDATA_DATA7

LCD_CLK_DATA6

IO_REG

PCO

ATI_32KHZ

LCD_RS

E14

M19

P19

N19

P15

H16

U19

P16

K15

K16

J16

J15

J19

H13

H15

H19

IO_REG

V19

GRAPH_REG

H10

PERIPH_REG

F12

VBUCK

N8

(for ATI Core)

(for CPU, GPIO)

(for Camera)

Pwr

Mgt

U600

Camera

SD

(Reset)