Servive, Engineering & Optimization

2005.11.07

LEVEL 3 AL Block Diagram

Rev. 1.0

V235

Page 1of 2

TCXO

Switch
Control
Circuit

U80

3

3

2

2

1

1

TX_EN

PA_BAND_SELECT

LNA

LNA

LNA

LNA

Quadrature

Polyphase

Quadrature

Mixer

Filter

Generator

FL100

Quard Saw Filter

6

3

High Band

1900MHz

4

1

and Matching

14

15

12

13

8

9

10

11

LP

LP

2

3

4

5

6

7

8

1

Low Band

900MHz

Low Band

850MHz

12

13

18

17

VRAMP

GSM850/GSM900 IN

DCS/PCS IN

DCS/PCS OUT

GSM850/

VRANGE

B+

7

3

2

4

5
6

1

9

11

GSM900 OUT

DC

Correct

22

21

20

19

27

25

26

14

15

16

GMSK/ EDGE Select

L

oop Fil

ter

RX/TX

Switch

ADC

13 bit

Sync

Filter

Anti

Drop

Anti
Alias

RX/TX

Switch

ADC
13 bit

Sync

Filter

Anti

Drop

Anti

Alias

Chanel

Filter

DAC

12 bit

LPF

Chanel
Filter

DAC
12 bit

LPF

Serial

Interface

Se

ri

al

In

te

rf

ac

e

GMSK

Modulator

EDGE

Modulator

EDGE

FIR

Filter

Anti
Alias

Pre-Distortion
Filter

Divider

PA Control

36

35

34

33

32

1

2

3

4

16

17

19

20

22

23

7

9

10

12

High Band

1800MHz

U50
PA

Antenna Switch

4

1

20

15

16

17

LD

T

O

RF

_C

L

K

RF

_D

A

T

A

R

F

_C

S

CT

RL

_2

RX_

ANT

_E

N

PA

_B

AND_

SE

L

RF

_R

E

G

9,10,32

31 30

29

28

VCO_

R

E

G

VT

C

FIN

11

VT

U150

RF IC

ENR

CLKR

FSR

DRI

VRANGE

IIN

IBIN

QBIN
QIN

41

40
39

38

LDTO

TX

I

MS

MD

I

MC

L

K

45

44

43

42

DAC2

VRAM

P

TX_EN

VCO2 (TX_IN_HB)

VCO1 (TX_IN_LB)

U200

RX/TX IC

from Neptune

22

ANTSW_1

Y806

26MHz

4

2

3

(1800 MHz)

(1900 MHZ)

(850 MHz)

(900 MHz)

900 MHz

850 MHz

1900 MHZ

1800 MHz

(Power Level control from U200)

(to U50)

(PA Disable function)

(High /Low Power Range control from U200)

(t

o

U50 pin 6)

(P

A P

ower

Contr

ol)

J1

Mechanical

Antenna Switch

Output M

ixer

Digital TX

Interface

Reference

Divider

U51

Internal

Antenna

U1702

Control

Serial Data

Interface

23

RX_

A

N

T

_E

N

CNT

RL

_1

CNT

RL

_3

TX

_ST

A

R

T

OSCA

OSCO

OSCM

OSCOM

48
31

30

Os

cila

to

r an

d

C

lock Gener

ator

(N

C

)

5

2

(T

ra

ns

m

itt E

na

ble

)

MS
MDI

MCLK

RF_CLK

RF_DATA

RF_CS

(N

C

)

( VCO Feedback )

(from U200)

(to U50 & U900)

( VCO Fine Tuning)

( VCO Coarse Tuning)

(100KHz)

14

15

DAC1

DAC2

(to U150)

(f

ro

m

U

20

0)

(to U200)

37

6 7

5

GPIO

CP

Phase Det.

(Main IC Control)

( Frontend Control

and Digital Modulation)

ADC

Voltage

Reg.

VCO_REG

RF_REG

PERIPH_REG

24
47

9,18

VCC’s from Atlas

A4

1Mbit RAM

DSP

DSP

UltraLite
104 MHz

DSP Peripherals
accelerator, encryption

Timer, Interupts

Shared Memory

MCU

52 MHz

ARM7

MCU

26 MHz
Oscillator

Memory

Memory

SIM

Interface

External

Interface

Memory

W7

Clock Generator

SPI

Power

NEPTUNE LTE

U800

G12
A13
N10

BaseBand

L1 Timer

V8
U6

U8
V7
W9

SPI

T9

W10

U9

(t

o U150

pin

29)

(from U150)

(t

o U50)

UART / USB

Interface

Keypad

Interface

On

Off

5
4

1

SIM DIO
SIM RST
SIM CLK
SIM_PD

6

VSIM_REG

3

GND

Connector

J1350

SIM

1.8 or 3V
SIM Card

VSIM_EN

VBUCK

REF_REG

(VCC + 1.575V)

(VCC + 1,875V)

(from Atlas )

SIM_REG

(to Atlas)

PERIPH_REG

(VCC + 2.775V)

J4

L1

K3

R1

M1

K2

(from Atlas )

(from Atlas)

2

VSIM_REG

IO_REG

( to Atlas

pin U15)

RX_

AN

T

_E

N

TX

_ST

A

R

T

(f

ro

m U800)

(100KHz)

EGSM: CH 37 -- 942,4Mhz

DCS: CH 700 -- 1842,8MHz

PCS: CH 661 -- 1960MHz

RX MID CHANNELS

GSM: CH 62 -- 947,4 MHz

850: CH190 -- 881,6

MQSPI
Display

U700

EB1B

EB0B

OEB

R_WB

ADDRESS BUS

DATA BUS

K16

J19

G17

T16

BURSTCLK

LBAB

CS2B

ECBB

T19

L16

W19

N18

A1-24

D0-15

32 MB Flash

RESET OUT

F3

C2

E5

F5,D5

J2,H1,H8

G7

C6

G8

F4

K1

P2

LCD_RS

P1

LCD_SDATA_DATA(7)

M4

LCD_CLK_DATA(6)

N3

LCD_CS

L3...

LCD_DATA (0 - 5)

8MB SRam

(from Neptune)

FLASH

VBUCK

L4..

Timer

GPIO

Interface

BaseBand

Port Interface

Serial Audio

(tx)

(rx)

MQSPI

One

Bus

Wire

UART2

Universal

Asynchron.

Rx /Tx

BT

ANT_DET

(VCC from Q200)

PERIPH_REG

R204

OSCA

TCXO

PERIPH_REG

2,3

5

4,6

Q201

U220

OSCM

RF_REG

2,3

5

4,6

Q200

ANTSW_1

(VCC to U80)

OSCO

CS1B

CS0B

D6

V17

T18

STANDBY_GATEB

STANDBY_GATE

OSCM

U804

1
2

4

OSCM

( clock for the DC offset correction

system - 26 MHz)

DMA

Direct

Memory

Access

Controller

V235

(only for GSM mode)

RF2722

24,

4

1

OSCB

SWITCH

SWITCH

FLIP_INTO

C14

VAMB_OUT

E1

Q801

LT_SNS_CTL

1

5

2

Light Sensor

C18

V6

ST

ANDB

YGA

T

E

B

(to J1300)

U1700

U1701

4

2

Reg.

Hall Effect

Switch

PERIPH_REG

6

1

ANT_DET

U12

(Antenna detect signal)

Ambient

U13

BB

_S

A

P

_T

X

BB

_SA

P

_R

X

BB

_SA

P

_F

S

BB

_SA

P

_C

L

K

B13

B12

A12

D13

(f

ra

me

sync

)

(c

lo

ck

)

CL

K 1

3 M

H

z

W13

C15

C16

D15

A16

BB

_SP

I_C

L

K

BB

_SP

I_M

O

S

I

BB

_SP

I_M

ISO

AUL

_C

S

Neptune /Atlas/

Communication

T11

V12

V11

W12

ST

ANDB

Y

G8

ST

A

NDB

Y_

G

A

T

E

CL

K 3

2KHZ

E3

B14

AUL

_I

NT

R

E

SETB

V13

(13 M

H

z)

(W

at

ch

dog)

WD

O

G

OW

B

W11

On

e W

ir

e

da

ta f

ro

m

B

atter

y

USB

_VP

IN

USB

_XRXD_

R

T

S

USB

_VP

OUT

_T

X

D

USB

_VM

IN

_RXD

U

S

B_

TX

E

N

B

USB

_SE

O

B16

A17

*Neptune/ Atlas

USB/ RS232

Communication

(fr

om

A

tla

s)

R

E

SET O

U

T

W5

(t

o U700

)

(from/ to Neptune

Serial Audio for Ringtone

and Voice Audio)

N17

N13

V16

D16

D19

B15

KB

R

0-

7

KB

C0

-1

F3....

G3....

*G

A_

SP

I_

CS

D18

Neptune Display Diver

T10

*G

A

_IN

T

2

4

(f

ro

m

A

tla

s)

U801

Level

(t

o A

tla

s)

KEYPAD

MATRIX

0-9,*,#,

Up, Down

Left-Right,

Center,
Soft L+R,
Menu, Send,
Volume U-D

Smart,

PC

13

A15

VR

505-507
ESD

Customer
Clear

Shift

VA, PTT

SIDE KEYS

(t

o U804)

(to Atla

s)

B17

(from Atlas)

ATI_EXT_RST

U11

CLI_MUX_EN

T8

SPI_CS0

T12

(NC)

TOUT12

U10

(bias for the THERM signal)

(VCC + 2.775V)

(from Atlas)

OSCB

(from Y806)

(Clock Enable)

(Clock Enable)

(Clock Enable)

(from U220)

11
10

(CS for CLI Display)

(asserts RESET to the ATI)

(VCC from Atlas)

(Deep Sleep Timing

(VCC from Atlas)

from Neptune)

(Crystal outputs

to U200)

(buffered 26 MHz

from U200)

(buffered / inverted

26 MHz to U800)

Revision Overview
Rev. 1.0: Initial Block Diagram
Rev. 1.1: Adding Audio Bus Signals to Atlas IC

(Flip Open/Close Detect)

5

(to Neptune U12)

PCS_RX_50

DCS_RX_50

GSM_RX_50

CELL_RX_50

1

2

VBOOST

R1450- R1457

D1450- D1457

LEDKP

BACKLIGHT

LED´s

V30x, V400, V50x, V600

V235

Servive, Engineering & Optimization

2005.11.07

LEVEL 3 AL Block Diagram

Rev. 1.0

V235

Page 2of 2

1
3
5

7
9
11
13

15
17
19
21
23

25
27
29
31

33

2

4
6
8
10
12

14
16
18
20

22
24
26
28

30
32
34

DISP_LED1
DISP_LED2
VBOOST1

CLI_LED2

GND

CLI_LED1

GND

CAM_REG

GND
RESETB

LCD_DATA0
LCD_DATA1
LCD_DATA2
LCD DATA3

LCD DATA4
LCD DATA5
LCD_CLK_DATA6
LCD_SDATA_DATA7

LCD_CS
LCD_RS
BB_SPI_MISO

CLK-32KHZ_2_7V

BB_SPI_MOSI

PC0
GND

(from Neptune - CS for CLI)

(from Neptune)

GND
BB_SPI_CLK

35
37
39

HAND_SPKR_GND
HAND_SPKR+

HAND_SPKR-

g1- g4

GND

36

38
40

GA_INT
RTC_BATT
VIB_REG

(fromNeptune)

(from Atlas)

(to Neptune)

(from Atlas)

(from Atlas)

J1300

FLIP CONNECTOR

Flip Connector

(from Atlas)

PERIPH_REG
IO_REG

GRAPH_REG

VBUCK
GND

(from Atlas)

(from Atlas)

PE14

(from Atlas)

GA_SPI_CS

CLK 13 MHZ

V12

CLK_32KHZ_2_7V

P16

TIMER

WDOG

K10

CNTL.

PRI SPI

LOGIC

Logic

F3

,E1

3...

...

..

Switc

he

r

U1

8

U1

6

T1

8

T1

7

R5

Interface

USB

Y900

V17

D12

RTC_BATT

V16

B+

HAND_SPKR-
HAND_SPKR+

T6
R7

T9

P9

V10
U8

ON1

B

F14

B4

E3

F3

U900

ATLAS UL

ON

LOGIC

OWB

THERM

P13

THERM

BATTISNS

BATT+

D14

F13

GND

CHRGCTRL

B16

VBUS

S

G

D

CHARGE

Charger

BATT CONN.

CNTL.

LED

E12

CODEC

16 BIT

STEREO

(tx) (rx)

ALERT-
ALERT+

STANDBY

F12

(to Neptune and U301 BT)

N1

4

RESETB

(from U800)

Neptune Atlas

Communication

UID

H8

Q904 (M3)

G

S

B+

B12

BATTFET

Battery to BPLUS

URXVP

URCVD

UDA

T

P

V

URXVM

UT

XE

NB

USE

O

VM

USB/RS232

(communication)

B2 C4

F4

B1

B3 E4

MICINM

MIC_BIAS1

Det.

Stereo

B

oos

t 300mA

G1

6

Switc

he

r

B

uck 350mA

F16

( 1

,87

5V

)

VB

UCK

H2

( 2,

77

5V

)

PE

R

IPH_

R

E

G

U6

( 2

,77

5V

)

AUD_

RE

G

M1

8

( 1,

27

5

)

GRAP

H

_RE

G

K1

7

H4

H3

( 2

,77

5V

)

RF

_R

E

G

L1

6

( 1

,57

5V

)

RE

F

_R

E

G

N5

( 1,

8/

3V

)

SIM

_REG

VS

IM

VS

IM

_E

N

K1

1

VBUS

CONTR.

E7

AD

C15

P

E

RIP

H

RE

G

(B

ia

s)

(One Wire Bus

to Neptune)

BPFET

VBUS to BP

Switch

(Main Source

for Atlas)

(from Mini USB Connector)

Main Charge Path
B+ support without Ext Charger
B+ support with Ext Charger

Color definition only for this section !

D903

VIB

_RE

G

(t

o V

ibra

tor

P

ads

ne

ar

(from Neptune)

NeptuneAtlas

*Neptune Atlas

USB/ RS232

Communication

D6

F8

(Battery Sense)

(VBUS Sense)

CONV.

D/A

1

M1261

2
1

(from Atlas)

( 1,

3V

)

POWER/END

Internal

Alert

Pads

TX_START

U15

(from Neptune, Tx Mode indication for Atlas)

( 2

,77

5 )

IO

_RE

G

( 2

,77

5 )

CAM

_R

E

G

( 5,

5V

)

VB

OOS

T

4

3

VBUS

5

2

1

(to Charging Circuit)

G1-G4

(Shield)

UID

CLK_32KHZ

R16

D-
D+

VBUS 5V

Pass FET

VBOOST

VBUS

D2

(PPD device support)

(to J1300)

C9

13

C9

99

to

V

ibr

ator

VI

B REG

P2

B+ Sense

Mo

to

r

M

ini

U

SB Con

ne

ct

or

)

RE

F

RE

G

RF

REG

PER

IP

H

IO

R

E

G

A

UDI

O

REG

IO

R

E

G

G

RAP

H

REG

CAMERA

REG

K2

( 1

,87

5V

)

BT

_R

E

G

BT REG

4

Microphone

R3

P4

R4

13 Bit

Handset

Amplifier

(to J1300)

Q

901

VCO

REG

VCO_

D

R

V

(M

ain Sour

ce

-

fr

om M

3)

( 2,

77

5V

)

VCO_

R

E

G

V2

SIM_PD

T14

CHRGRAW

S

G

D

Q903 (M4)

Q906 (M1)

(I Sense)

G

S

M950

2

3

1

4

R910

R911

D

Switch

B14

CHRGISNS

E15

(Charger output

Sense)

(Current Control)

Q905 (M2)

DISP_LED4

CLI_LED2
DISP_LED3

(only us

ed in Atlas

)

CLI_LED1

F6

C5

LEDKP

(t

o Neptune)

(At

la

s inte

rna

l a

nd

AL

c

ir

cuit)

( Atla

s,

Ne

pt

une

,

U700,

J1300

, L

evel Shif

ter

)

(t

o J

1300)

(t

o Neptune amd

M

1200)

)

(t

o

U15

0,

U200,

Q200)

(t

o U301)

(t

o Atl

as

, Neptune,

J

1300)

(t

o At

las

and J

1300)

(t

o U250

Mini USB

Charger and Power-

source Control

(toJ1300)

(from/ to Neptune and U700)

(toNeptune)

(from Neptune)

TOUT12

(Bias Voltage from

Neptune)

(Accessory Detection signal)

(from Acesory Connector)

(EXT Power)

(EXT Power)

VR1

70

0

VR1

77

9

VR9

50

S14

T10
P6

AUX_MICM

HJACK_SPKR_R -

J1240

HJACK_DET

R9

U2

HJACK_MIC

MICBIAS2

4

2

3

1

Det.

Headset

(ARIGHT_OUT)

(to Keypad LED´s)

(fromNeptune)

R9

13

3

4

1

+ U200)

Keypad Backlight

ESD

RV915

VR1700
RV1702

RV914

(asserts RESET to the ATI)

Headset

Connector

SAP

Supply

Amplifier

Alert

Amplifier

Headset

Amplifier

EMU

L

/

H

/

H

H

/

L

/

L

H

/

H

/

H

H

/

H

/

H

L

/

H

/

H

L

/

H

/

L

MK2000

MIC

VR1

70

0

Q

901

J951

1

2

(to Neptune DISP_LED1)
(to Neptune DISP_LED2)

BB

_SA

P

_T

X

(R

x)

B

B

_S

AP

_RX

(T

x)

B

B

_SA

P

_F

S

BB

_S

A

P

_C

L

K

Revision Overview
Rev. 1.0: Initial Block Diagram
Rev. 1.1: Adding Audio Bus Signals to Atlas IC