Service, Engineering & Optimization

2007.03.06

LEVEL 3 AL Block Diagram

Rev. 1.0

V3_06

Page 1of 2

V3_06

Revision Overview
Rev. 1.0: Initial Block Diagram

OSCO_F

3

3

2

2

1

1

TX_HB

DCS/PCS OUT

GSM850/

BP

7

5

2

9

GSM900 OUT

16

U50_PA

PA + Antenna Switch

21

4 6

ENR

CLKR

FSR

DRI

LDTO

TX

I

MS

MD

I

MC

LK

RA

MP

from Neptune

Y201

26MHz

2,4

1

RX1800

RX1900

RX850

RX900

(P

A Po

we

r Contr

o

l)

J40_RF

Mechanical

Antenna Switch

Internal
Antenna

A1

RX_

AN

T_E

N

CNT

RL

_2

CNT

RL

_3

TX_

S

T

A

R

T

26MHZ_OSCO

OSCM

PERIPH_IO_REG

(N

C)

(T

ra

ns

m

itt E

n

able)

MS
MDI

MCLK

RF_CLK

RF_DATA

RF_CS

( Lock Detect Out)

(to U250)

(U250 Control Bus)

( Frontend Control
and Digital Modulation)

VCO_REG

PERIPH_IO_REG

RF_REG

A4

1Mbit RAM

DSP

DSP

UltraLite
104 MHz

DSP Peripherals
accelerator, encryption
Timer, Interupts

Shared Memory

MCU

52 MHz

ARM7

MCU

26 MHz
Oscillator

Memory

Memory

SIM

Interface

External

Interface

Memory

W7

Clock Generator

SPI

Power

NEPTUNE LTS

U800

G12

A13

N10

VoiceBand

L1 Timer

V8

U6

U8
V7
W9

SPI

T9

W10

U9

UART / USB

Interface

Keypad
Interface

On

Off

2

1

6

SIM DIO

SIM RST

SIM CLK
SIM_PD

3

VSIM

4

GND

Connector

J4

SIM

1.8 or 3V
SIM Card

VSIM_EN

VBUCK

(VCC + 1,875V)

(from Atlas )

VSIM

(to Atlas)

IO_REG

J4
L1

K3

R1
M1

K2

(from Atlas )

(from Atlas )

5

PERIPH_IO_REG

( to

Atlas

)

TX

_S

T

A

R

T

MQSPI
Display

U700

EB1B
EB0B

OEB

R WB

CS1B

ADDRESS BUS

DATA BUS

K16

J19

G17

T16

BURSTCLK

LBAB

CS0B

ECBB

V17

T19
L16

N18

A0-24

D0-15

32 MB Flash

RESET OUT

F3
C2

G8

E5

F5,D5
J2,H1,H8

G7

C6

K1

F4

D6

HS INT

C14

ADC DATA

E1

LT_SNS_CTL

8MB SRam

(from Neptune)

FLASH

U13

BB

_SA

P

_T

X

B

B

_

S

AP

_R

X

BB

_SA

P

_

F

S

BB

_S

A

P

_

C

LK

B13

B12

A12

D13

(fram

es

y

n

c)

(cl

o

ck)

CLK

13 MH

z

W13

C15

C16

D15

A16

BB

_

S

P

I_C

LK

BB

_S

PI_M

O

S

I

B

B

_S

PI_

M

IS

O

AU

L_

CS

Neptune Atlas

Communication

T11

V12

V11

W12

ST

AN

DB

Y_1

_5V

G8

ST

A

N

DB

Y

CL

K 32

KH

Z

E3

B14

AU

L_

INT

RE

SET

B

V13

(13 M

H

z)

(W

a

tchdog)

WD

OG

OW

B

W11

On

e W

ire dat

a from

B

at

te

ry

US

B_V

P

IN

U

S

B

_

XR

XD

_

R

T

S

US

B_V

P

O

U

T

_

TX

D

US

B_V

M

IN_R

XD

U

S

B

_

TX

EN

B

US

B_S

E

0

B16

A17

Neptune Atlas

USB/ RS232

Communication

(to

Atlas

a

n

d

RE

SET

O

U

T

W5

(t

o U700)

(from/ to Neptune

Serial Audio for Ringtone

and Voice Audio)

RX

D2

TX

D2

RT

S

2

CT

S

2

N17

N13

V16

D16

(from/ to U301 BT, J1300

Neptune - BT - Neptune

Communication and Wakeup)

BLU

E_

W

A

KE

B

B

L

UE

_H

OS

T_W

A

K

E

B

D19

B15

KB

R0

, 3-

6

KB

C

1

-2

F3....

F2....

GR

AP

H_S

PI_

C

S

D18

Neptune Display Diver

Timer

GPIO

Interface

BaseBand

Port Interface

Serial Audio

(tx)

(rx)

MQSPI

One

Bus

Wire

UART2

Universal

Asynchron.

Rx /Tx

BT

CS2B

W18

C18

T10

G

RAP

H_

INT

ST

AN

DB

Y_

G

A

TE

B

OS

CM

U802

1

2

4

3

CNT

RL

_1

TX

_E

N

15

14

13

Power and
Antenna
Control

(B

and

s

elect)

8

(Clock enable)

3

TX_LB

(NC)

(f

ro

m Neptune GP

IO

)

2

4

(fro

m A

tl

as

)

VBUCK

E4...

(from

Atlas

)

U801

Level

(t

o Atlas

)

P2

LCD_RS

P1

LCD_SDATA_DATA7

M4

LCD_CLK_DATA6

N3

LCD_CS

L3...

LCD DATA (0 - 5)

(LCD Control via J1300)

VSIM

(from Atlas)

Shift

and B

T

))

(VCC + 1,575V)

REF_REG

E2

A

TI_

RES

E

T

B

_2

_7V

T13

(t

o J

1

3

00)

(VCC + 2.775V)

A11

(VCC + 2.775V)

H1

V5

TOUT12

U10

(Bias output for THERM signal)

(Clock )

(Reset )

(Data In /OUT)

( Frontend Control

and Digital Modulation)

(R

eceive E

n

able)

(T

rans

mit

t E

n

abl

e

)

(Clock )

(Reset )

(Data In /OUT)

(Clock )

(Chip select)

(Data In /OUT)

PA Control

B10

VSENSE

(PA_DET from U50)

1

VSENSE

(PA_DET to U800)

V6

ST

AN

DB

Y_

G

A

TE

B

U802)

(from

/ t

o

At

la

s

T18

( analog Light Sensor value

from J2- Keyboard Connector)

( Bias for Light Sensor

to J2

(K

eyboar

d

M

atr

ix Si

gnals

v

ia J

2

)

ANT_DET_B

(indicates mechanical Antenna connection to U800)

ANT_DET_B

U12

(indicates mechanical Antenna connection to U800)

EL_EN

G11

(EL Backlight Enable via J2)

VRBB1
VRBB2

ESD

U2002

2,5

3

ADIN6

(RF TEMP Sense to Atlas)

OSCM

(Enable)

Temp Sensor

4

R2094

Switch Mode

Cntrl_1

Cntrl_2

Cntrl_3

TX-EN

Low Pwr Standby Mode

RX850

RX900

RX1800

RX1900

TX_LB

TX_HB

1

0

0

0

0

1

0

0

0

1

X

X

0

0

0

X

X

1

1

1

0

0

0

1

1

X

X

X

Logic Table

LNA

LNA

LNA

A2

GMSK/ EDGE Mixer

RX/TX
Switch

ADC
13 bit

Sync
Filter

Anti
Drop

Anti
Alias

RX/TX
Switch

ADC
13 bit

Sync
Filter

Anti
Drop

Anti
Alias

Chanel
Filter

DAC

12 bit

LPF

Chanel
Filter

DAC
12 bit

LPF

Serial
Interface

Ser

ial

Data

In

te

rface

GMSK

Modulator

EDGE

Modulator

EDGE
FIR
Filter

Anti
Alias

Pre-Distortion

Filter

Fractional

PA Control

F8

F7

F6

H7

FIN

IIN

IBIN

QBIN

G4

F4

F5

G3

D7

E8

E7

G8

TX_EN

VCO2 (TX_HB)

VCO1 (TX_LB)

U250_SYN

GSM/ EDGE

O

u

tput M

ixer

Tx Data/

Analog IQ

D8

E5

G7

O

sci

la

to

r and

C

lock Gener

ator

( VCO Feedback )

( VCO Tuning)

(100KHz)

C3

DAC1

C2

D6 G5

E6

General Purpose

Charge Pump

Phase Det.

Analog
Voltage

Reg.

H3

B8,H2

C1,E4

(100KHz)

TRANCEIVER

QIN

B7

D2

Reference
Devider

C5

C6

Polyphase
Filter

DC
Correct

Quadrature
Generator

Quadrature
Mixer

LNA

G1

F1

A3

A5

A6

L

oop F

ilter

SAW/ LNA

Matching

SAW/ LNA

Matching

SAW/ LNA

Matching

SAW/ LNA

Matching

MUX

RX VCO

Divider

Filter

Output

Digital LO

X

TX VCO

Analog/

Digital

Select

CORDIC

Phase

Ampl

DAC2

D4

VCO

Reg

Digital
Voltage

Reg.

(from U1401)

Service, Engineering & Optimization

2007.03.06

LEVEL 3 AL Block Diagram

Rev. 1.0

V3_06

Page 2of 2

Revision Overview
Rev. 1.0: Initial Block Diagram

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7

PERIPH_IO_REG

GRAPH_INT
LCD_SDATA_DATA7

LCD_DATA3
LCD_DATA5

LCD_RS

LCD_CLK_DATA6

KBR6

KBR5
KBR7

EL_EN
REG_3V
GND
GND
HAND_SPKRM
HAND_SPKRP
GND
CLK_32KHZ_2_7V
GND
VBUCK_FLIP
GRAPH_REG

KBR3

LTS_SNS_CNTL

PWR_SW

(from Neptune)

GND
ADC_DATA

6
4
2

KBC0
KBR2
KBR1

G1- G4

GND

5
3
1

KBC1
KBR0
KBC2

(toNeptune)

(to Atlas)

(from Atlas)

(from/ to Neptune)

J2_KEYBRD

Keyboard Flex Connector

LCD_CS
LCD_DATA2

LCD_DATA1
LCD_DATA0
LCD_DATA4

KBR4

(from Atlas)

GND

(clock)

CLK 13 MHZ

V12

CLK_32KHZ_2_7V

P16

TIMER

WDOG

K10

CNTL.

PRI SPI

LOGIC

Logic

F

3

,E

1

3

...

...

..

S

w

itcher

BB_

SP

I_CL

K

BB

_S

P

I_

M

OS

I

B

B

_

S

PI

_M

ISO

AU

L CS

U18

U1

6

T1

8

T1

7

R5

Interface

USB

Y900

V17

D12

RTC_BATT_DNP

V16

BP

HAND_SPKRM

HAND_SPKRP

T6
R7

T9

P9

V10

U8

PW

R_

S

W

F1

4

B4

E3

F3

U900

ATLAS UL

ON

LOGIC

OWB

THERM

P13

THERM

ISNS_PM

BATTP

D14
U14

GND

CHRGCTRL_PM

B16

VBUS

S

G

D

CHARGE

Charger

BATT CONN.

CNTL.

LED

E12

BB

_SA

P

_

F

S

BB

_S

AP_

C

L

K

BB_

SA

P_T

X

BB_

SA

P_R

X

Neptune Atlas

CODEC

16 BIT

STEREO

(tx) (rx)

Communication

ALERTM

ALERTP

STANDBY

F12

(to Neptune and U300 BT)

AU

L_I

N

T

N1

4

RESETB

(from U800)

Neptune Atlas

Communication

USB_ID

H8

Q904 (M3)

G

S

BP

B12

BATTFET_PM

Battery to BPLUS

USB

_

VP

IN

USB

_

XR

XD

_R

T

S

USB

_

VP

OU

T_

TXD

USB

_

VM

IN

_RX

D

U

S

B_

TX

E

N

B

USB

_

SE

0

USB/RS232

(communication)

B2

C4

F4

B1

B3

E4

MICINM

MICBIAS1

Det.

Stereo

B

oos

t 300m

A

G16

S

w

itcher

B

u

c

k

350mA

F16

( 1,

87

5V )

VB

U

C

K

H2

( 2,

77

5V

)

PE

RIP

H

_

IO_

R

E

G

U6

( 2,

77

5V

)

AUD

_

RE

G

M1

8

( 1,

2

75 )

G

R

A

P

H_

RE

G

K17

H4

H3

( 2,

7

75V

)

RF

_RE

G

L16

( 1

,57

5V

)

RE

F_R

E

G

N5

( 1,

8/

3V

)

V_S

IM

VS

IM

V

S

IM

_E

N

K1

1

VBUS

CONTR.

AD

C15

PER

IPH

RE

G

(Bi

as

)

(One Wire Bus

to Neptune)

BPFET_PM

VBUS to BP

Switch

(Main Source

for Atlas)

(from Mini USB Connector)

Main Charge Path

B+ support without Ext Charger
B+ support with Ext Charger

Color definition only for this section !

D903

BB_SAP_TX

BB_SAP_RX

BB_SAP_FS

BB_SAP_CLK

(framesync)

Bluetooth

U300_SYM

32

30

28

27

BLUE_WAKEB

11

BLUE_HOST_WAKEB

9

TXD2

5

CTS2
RTS2

31

RXD2

33
29

RESETB

22

(from Neptune/Atlas)

(from/to Neptune

Serial Audio for Ringtone

and Voice Audio)

PERIPH_IO_REG

10, 18, 19

BTRF_REG

21

BT_FEED

25

Strip Line
Antenna

(on PCB)

Y301

15

16

12

VV

IB

(from Neptune)

NeptuneAtlas

Neptune Atlas

USB/ RS232

Communication

(Battery Sense)

(VBUS Sense)

CONV.

D/A

CLK_32KHZ

(from Atlas)

3

(from Atlas)

( 1,

3V

)

(Neptune/BT

Communication and Wakeup)

Internal MIC

PCB

Pads

TX_START

U15

(from Neptune, Tx Mode indication for Atlas)

( 2,

7

75 )

IO

_R

EG

( 3,

10

V

)

RE

G_

3V

( 5,

5

V

)

VB

OO

ST

2
3

VBUS

1

4

5

(to Charging Circuit)

G1-G4

(Shield)

CLK_32KHZ

R16

DM_TXD

DP_RXD

VBUS 5V

Pass FET

VBOOST

VBUS

D2

(PPD device support)

1

3

(from J2 ??)

to V

ib

rator

VIB

REG

P2

Mo

to

r

REF REG

RF

REG

PE

RI

PH

IO

REG

AUD

IO

REG

IO REG

GR

A

P

H

RE

G

CAM

E

RA

REG

K2

( 1,

87

5V

)

BTR

F_

REG

BT R

E

G

4

Microphone

R3

P4

R4

(t

x)

(rx)

13 Bit

Handset

Amplifier

(to J2)

Q9

10_

DN

P

VCO

REG

VC

O_R

EG

_C

NTL

_

P

M

(M

ain S

our

ce-

f

ro

m

Q904)

( 2,

77

5V

)

VC

O_

RE

G

V2

SIM_PD

T14

CHRGRAW_PM

S

G

D

Q903 (M4)

Q905 (M1)

G

S

R910

R911

D

Switch

B14

CHRGISNSP_PM

E15

(Current Control)

Q906 (M2)

(o

nly us

ed in Atlas

)

E10

LEDB1

(t

o Neptune)

(A

tl

as

in

ter

n

al and

AL

cir

cuit)

( Atlas

, Neptune,

U700

, Q960,U801)

(t

o J

2

)

(t

o N

e

p

tune amd J

4

)

(t

o U250)

(t

o

U300)

(t

o Atlas

, Neptune, Q960)

(t

o U25

0

)

Bluetooth

Mini USB

Charger and Power-

source Control

( to Neptune and U700??)

(from J4)

(from Atlas)

(from Neptune)

TOUT12

(Bias Voltage from
Neptune)

(Accessory Detection signal)

(from Acesory Connector)

(EXT Power)

(EXT Power)

D14

2

6

Det.

Headset

(to Display Backlight via V2)

R

905

3

4

1

ESD

VR922A

VR960

VR950

VR921A

SAP

Supply

Amplifier

Alert

Amplifier

Headset

Amplifier

EMU

V3_06

J1_USB

NC

NC

ALERT

NC

(f

ro

m

J2

)

ESD

VR1400

ATI_RESETB_2_7V
BB_SPI_MISO

46
44
42

BB_SPI_MOSI
BB_SPI_CLK
GRAPH_SPI_CS

50
48

(from/ to Neptune)

49
47
45
43
41

GND
REG_3V
RTC_BAT
IO_REG_FLIP
GND

(from/ to Neptune)

LEDB1

(Bias from Neptune)

(from Atlas)

(from Atlas)

(from Atlas)

(from/ to Atlas)

(from Q960)

(from Q960)

NC

VBUCK

IO_REG

(from Atlas)

NC

(VCC)

C4

C2

A4

C1

A1

B4

A3

C3

Q960

Vi

b

. M

o

to

r

1

2

BA

TT

P

J3_BATTERY

3

2

4

1

VR

50

B

+

S

ens

e

Q9

43

_D

NP

VB

TP

ADR

V

( 3,

00

V )

VC

C_B

T

P

A

M4

3

4

1

(t

o J

2

)

GRAPH_REG_AUL

(o

nly us

ed in Atlas

)

(o

nly us

ed

in At

las

)

ISNS_PM

F13

(Charge Current - )

(Batt Current)

(Charger Current + )

AD

IN6

(f

ro

m U2002

)

(R

F T

E

M

P

Se

ns

e)

T13

SIM Block

J4_SIM

R1201

SIM_CLK

R1214

SIM_RST

R1213

VSIM

GND

R1202

SIM_DIO

U1401

2

R14

0

1

5

HS_INT

4

A2

(clock input for audio bus)

(to J2, peripheral clock)

(from Atlas)

CHRGCOMMON_PM

(32.768KHz)

L10

CHRG_LED_SINK ??

(sensing pt)

P14

OSCM

(inverted output of standby pin??)

H8

USB

_

ID

E3

F3

DP_

RXD

DM

_T

XD

(U

SB

D+

, R

S

323 R

x

)

(U

SB

D-

, R

S

323 T

x

)

D10

LEDG1

??

U950_DNP

4

CTS1

1

2, 5

PE

RIP

H

_

IO_

RE

G

(Flip Open/ Close

Detect)

Hall Effect

Switch

(to U800)

26MHz

(from U800)

(from U800)

(to/from U800)