design
ideas
Edited by Bill Travis and Anne Watson Swager
Push-pull driver provides isolated 5V at 1A
Ron Young, Maxim Integrated Products, Sunnyvale, CA
D1
he circuit in Figure 1 converts a
T1
(MURS120)
(COILTRONICS)
regulated 5V input to an
MBRS130
Figure 1
CTX03-14439
Tisolated 5V output with 1A +
current-output capability. IC1, a push-
pull transformer driver, powers a pair of
+
cross-coupled power MOSFETs in a flip-
5V
100 F
5V AT 1A
+
flop-like configuration. In turn, the
100 F
MOSFETs toggle the primary winding of
a forward transformer. The transformer s MMDF3N03HD
secondary output, after rectification and
D2
300
filtering, provides the isolated 5V supply.
300
MBRS130
(MURS120)
Because the output voltage is unregulat-
ed, its voltage tolerance depends on the
input-voltage range and the range of load
current. With Schottky rectifiers, such as
the MBRS130 for D1 and D2, the circuit
1 8
delivers 5V 10% at 700 to 1000 mA
2 7
from a 5V 5% input with 80% efficien-
MAX253
cy (Figure 2). Using ultrafast-recovery
IC1
3 6 5V
silicon rectifiers, such as the MURS120,
4 5 0.1 F
the circuit delivers 5V 10% at 200 to 500
mA from a 5V 5% input, with 77% ef-
ficiency. (DI #2502)
A simple circuit produces a 5V, 1A isolated output from a 5V regulated input.
To Vote For This Design,
Circle No. 366
90
SCHOTTKY
MBRS130
80
Push-pull driver provides ULTRAFAST
MURS120
70
isolated 5V at 1A ..........................................101
Circuit programs Atmel AVR Cs ............102 60
Circuit adds latch-off current
EFFICIENCY (%)
50
limit to regulator ..........................................104
40
Dual power supply delivers
30
8A with no heat sinks..................................106
20
Power switch provides soft start ..............108
Circuit eliminates PC echoes ....................110
10
Clamping circuit dissipates
0
100 200 300 400 500 600 700 800 900 1000 1100 1200 1300
minimal power..............................................112
IOUT (mA)
Piezo crystal monitors liquid level............112
Figure 2
Switch intelligently controls current ........114
The efficiency of the circuit in Figure 1 depends directly on the forward drops of the output
rectifiers.
www.ednmag.com March 30, 2000 edn 101
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design
ideas
Circuit programs Atmel AVR Cs
Guo-Yin Xu, XuMicro, Houston, TX
tmel AVR Cs feature an enhanced have a built-in SPI (serial-peripheral-in- pin Cs, and the signals from P3.2 to
RISC architecture that purportedly terface) port that you can use to effect se- P3.5 are for eight-pin Cs. Note that you
Aoffer the highest MIPS-per-milliwatt rial programming. The SPI port uses only need pullup resistors for the AT89C4051
capability in the 8-bit C market. Figure the system-clock (SCK), master-output/ port pins P1.0 and P1.1, because these
1 shows an easy-to-build AVR C-pro- slave-input (MOSI), and master-input/ pins normally serve as analog-signal-in-
gramming circuit that can program the slave-output (MISO) pins. The AVR data put lines. Jumper JP1 controls the 5V
40-pin AT90S4414/8515, the 20-pin AT book requires that, to place a C in seri- power supply for 20- and eight-pin Cs.
90S1200/2313, and the eight-pin AT al-programming mode, you must first You should remove the jumper when
90S2323/2343. The programmer uses pull the Reset and SCK pins low (Refer- programming 40-pin Cs, which use a
only three chips. It connects to the host ence 1). Then, the C must execute a hard-wired connection to the 5V power.
PC s serial port via a MAX232 RS-232 programming-enable instruction before The circuit uses two 4-MHz ceramic res-
transceiver, IC1. Power comes from a 9V it can execute any program of erase in- onators: CR2 for 20-pin Cs, and CR/CR3
wall cube and the 78L05 linear regulator, structions. for 40- or eight-pin Cs. Because the
VR1. The AT89C4051 C (IC2) works Hence, you need four pins to control wires for the resonators should be as
with the 11.0592-MHz oscillator, and the programming of a C. For instance, short as possible, the circuit uses no
controls all programming tasks. LED1 in- the control signals from the AT89C4051 switching or jumping mechanisms. In-
dicates the programmer s status. The cir- port pins P1.4 to P1.7 are for 40-pin Cs, stead, it uses one more resonator, CR2
cuit exploits the fact that all AVR Cs the signals from P1.0 to P1.3 are for 20- that s hard-wired to pins 4 and 5 of the
VR1
5V JP1
9V DC 78L05
+ C1 C2 VCC
0.1 F
10 F 1 40
20
Figure 1
VCC R2 R3 2 39
C9
1
10k 10k
40-PIN
RST 0.1 F
3 38
ZIF SOCKET
C3 IC2
R1 4.7 F AT89C4051 4 37
330
5 36
LED1
19 MOSI
P1.7 6 35
18 MISO
7 34
11 P1.6
P3.7
17 SCK
P1.5 8
33
5V
16 RESET
P1.4 9
32
C5
C4 + 10 31
10 F
16
10 F 15 RESET2 VCC2
P1.3 11 1 30
20
2
12 2
19 29 SCK2
1 4 14
P1.2
C6 + C7 13 3 18 MISO2
28
IC1 4.7 F P1.1 13
4.7 F
TO PC SERIAL PORT
MAX232
3 5 14 4 17 27 MOSI2
CR2
COM1
4 MHz
15 5 16 26
12
P1.0
2 7 9 2
RX 16 6 15 25
8 10
J1 3 3
VCC3
RESET3
TX 6
P3.2 17 7 1 8 14 24
6
C8 CR/CR3 18 8 2 7 13 23 SCK3
5
4.7 F 4 MHz
15
MISO3
19 9 22
3 6 12
MOSI3
10
20 4 5 11 21
5
5V
XTAL1
GND
7
P3.3
8
P3.4
OSC1 11.0592 MHz
9
P3.5
GND
10
Exploit the power of Atmel s AVR Cs, using this easy-to-build programmer.
102 edn March 30, 2000 www.ednmag.com
|
+
+
+
+
design
ideas
20-pin C pins 14 and 15 of the ZIF contains the host-PC communication Book, Atmel Corp, August 1999.
socket. This connection does not disturb program. You can download these rou- 2. Xu, Guo-Yin,  8X51 EPROM/flash
the programming of 40-pin Cs. tines from EDN s Web site, www.edn- microcontroller programmer, Circuit
In addition to the hardware in Figure mag.com. Click on  Search Databases Cellar Magazine, April 1998.
1, the programmer also needs associated and then enter the Software Center to
software. A binary file, AVRP1.BIN, holds download the file for Design Idea #2504.
the finished AVR-programmer software, (DI #2504)
burned into the AT89C4051 C by using
an 8X51 EPROM/flash C programmer References To Vote For This Design,
(Reference 2). A DOS file, AVRP1.EXE, 1.  8-bit RISC Microcontrollers Data Circle No. 367
Circuit adds latch-off current limit to regulator
Craig Varga, Linear Technology Corp, Milpitas, CA
n many applications, forcing a high- soft-start capacitor, C9. At this point, the regulator to restart. If you don t need the
current power supply to latch off if a latch-off circuit begins to take over. When reset function, you can eliminate C6, R7,
Isustained fault condition exists can the voltage across C9 decreases to a cou- R10, and Q4.You can then initiate a restart
minimize the likelihood of damage to the ple of volts below VCC, Q2 turns on and by recycling the 5V input power. The only
pc-board traces and the power devices in begins to source current, charging C12. timing requirement is that the latch-off
the supply. Pulse-width-modulation After a time interval depending on the delay be greater than the soft-start rise
(PWM)-control circuits provide no values of R5 and C12, Q5 turns off and time at turn-on. Otherwise, the regulator
latch-off feature, but the circuit in Figure pulls the shutdown pin low, thereby turn- can never start. You can modify the cir-
1 does. The circuit is based on IC1, an ing off the controller. Because this action cuit to work with any other controller,
LTC1430 PWM controller. The current- internally grounds the soft-start pin (to such as the LTC1553, having the soft-start
limiting feature of the IC operates by allow a normal soft-start cycle at turn- function. (DI #2503)
sensing the voltage across the high-side on), the circuit remains latched in the off
MOSFET and compares it with a thresh- state. You can initiate a reset by applying
old voltage developed across R3. If an a fast logic high to the reset line. C6 and
overcurrent condition exists, an internal C7 provide a differential pulse to the base To Vote For This Design,
current source starts to discharge the of Q4, which discharges C12, allowing the Circle No. 368
R1
10
12V
Figure 1
5V
C2
C1
C1 + + 330 F + C3
330 F 330 F 330 F
C8
6.3V
R2
6.3V 6.3V 6.3V
0.1 F
51
OVERCURRENT LATCH-OFF CIRCUIT
IC1
R3
LTC1430 C4
16k Q1
1 F
15
PVCC2 PVCC1 2
IRF7801
14 1
R5 R4
VCC G1
L1
15k
11 13
10k
E1
FSET
IFB
12
+
16 R6
IMAX G2
2.4 H
RESET Q2 1k
8
3
TP0610T SD
PGND
10
5 C8
+
COMP +
Q3
C6 SENS
9 330 F
7
0.01 F SS IRF7801
D1
C9 R8 +SENS C7 6.3V
MBRS130
Q5 0.01 F
13k 4 C10 330 F OUTPUT
R7 6
SGND
FB 6.3V
R9 2N3904 330 F 3.3V AT 7A
10k
C14
Q4 20k
6.3V
1500 pF
2N3904
E2
C11 C13
+
220 pF
C12 R11 22 F
C15
R10
1 F 35V
0.1 F
10k
10k
You can add a latch-off current-limiting feature to a simple pulse-width-modulation controller by adding a few external components.
104 edn March 30, 2000 www.ednmag.com
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design
ideas
Dual power supply delivers 8A with no heat sinks
John Seago, Linear Technology Corp, Milpitas, CA
he circuit in Figure 1 is a high-cur- controlling the duty cycle of the top time, inductor current flows through the
rent dual supply that provides 5 and MOSFET for VOUT1, Q1, so that average commutating diode, D1, to the load.
T3.3V at currents as high as 8A. The input voltage to the buck inductor, L1, is Feedback resistors R3 and R4 connect
circuit uses a fixed-frequency, two-out- equal to the output voltage. The buck in- IC1 s internal error amplifier to the out-
put, current-mode synchronous-buck- ductor and output capacitors C3 to C5 put. Loop-compensation components
controller, IC1, to regulate both 5 and three 330- F capacitors in parallel in- R1, C1, and C2 control the frequency re-
3.3V outputs. The circuit uses separate tegrate and filter the energy pulses from sponse of the error amplifier. The inter-
regulator circuits for each output voltage. Q1 to generate the dc output. After Q1 nal current comparator senses inductor
However, both circuits are identical ex- turns off, the bottom MOSFET for VOUT1, current by the voltage developed across
cept for the lower feedback resistors, R4 Q2, turns on to conduct inductor current the current-sense resistor, R2.
and R7, which determine the 5 and 3.3V to the load. To avoid shoot-through cur- The 3.3 regulator, which produces
output voltages, respectively. rent, a short dead time occurs before each VOUT2, functions exactly like the 5V reg-
IC1 regulates the 5V output, VOUT1, by MOSFET turns on. During this dead ulator. Q3 and Q4 are the top and bottom
Figure 1
47k
0.1 F
10
MMSD-
914
IC1
10
0.1 F
VIN1
LTC1438-ADJ
C11 TO C13+ 5.5 TO 28V
C1 1 28 0.1 F
1M
10
SENSE+1 RUN/SS1 330 F
1000 pF 0.1 F 50V
2 27 50V
1000 pF
BOOST 1
SENSE 1
Q1
3
280k
3 26
R1 C2 R2
VOSENSE1 TGL1
2200 pF 0.01
2.2k
4
VOUT1
ITH1 SW1 25
5V/8A
L1
5 24
R3 1000
POR2
Q2
POR2 VIN 0.1 CMDSH-3 5.2 H
82 pF 1 F
F 35.7k pF
6 23
COSC BG1 10V
C3 TO C5
D1 330 F + R4
7
SGND INTVCC 22 4.7 F 100 pF
11.0k
+
6V, 3
1 F
8 21
10V
LBI PGND
Q3 C8 TO C10
9 20
LB0 BG2
LBO
D2 330 F R7 100 pF
47k
C6, 1000 pF
10
6V, 3 20.0k
EXTVCC 19
SFB1
C7, 2200 pF
1 F
11 18
SW2
ITH2 10V
L2 R6 R8 1000
R5 12
35.7k
VOSENSE2 TGL2 17 CMDSH-3
0.1 F pF
5.2 H
2.2k
0.01
VOUT2
13 16
Q4
BOOST 2 3.3V/8A
SENSE 2
14 15
RUN/SS2
SENSE+2
1000 pF 0.1 F
VIN2
5.5 TO 2.8V
MMSD914
C14 TO C16 +
10
0.1 F
10
330 F
35V
3
0.1 F
NOTES:
C11 TO C13, C14 TO C16=SANYO 35CV330GX.
C3 TO C5, C8 TO C10=KEMET T495X337M006AS.
D1, D2=MOTOROLA MBRD835L.
L1, L2=PULSE ENGINEERING PE-53700.
Q1, Q4=SILICONIX SUD50N03-10.
Q2, Q3=SILICONIX Si4420DY.
R2, R6=IRC LRF2512-01-R010-J.
A single IC regulates both 5 and 3.3V outputs; each output delivers 8A.
106 edn March 30, 2000 www.ednmag.com
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+
design
ideas
MOSFETs, respectively, and L2 is the buck high but goes low when the input voltage of the capacitor connected to the
inductor. D2 is the commutating diode. is low. IC1 includes a complete power-on- RUN/SS pin determines the output volt-
Feedback resistors R7 and R8 connect the reset circuit. At startup, the POR2 pin is age delay and the inductor-current ramp
error amplifier to the output. R5, C6, and low. This pin goes high 65,536 oscillator time, both at a rate of 0.5 sec/ F. Pulling
C7 are the loop-compensation compo- cycles after Channel 2 s output voltage a RUN/SS pin low turns off that output
nents, and R6 is the sense resistor. C8, C9, reaches 95% of its programmed value. voltage. Pulling both RUN/SS pins low
and C10 make up the output capacitor. The POR2 pin goes low if the output shuts down IC1, turns off all internal cir-
The circuit in Figure 1 has some fea- voltage falls 7.5% from nominal. Each cuitry, and limits the input current to 16
tures that add versatility. The low-battery output has a RUN/SS pin that provides A. (DI #2494)
comparator in IC1 flags a low-input-volt- output-voltage delay, output-current To Vote For This Design,
age condition. Normally, the LBO pin is soft-start, and on/off control. The value Circle No. 369
Power switch provides soft start
John Haase, Colorado State University, Fort Collins, CO
n the circuit in Figure 1, series-con- to 2N2906 common-base comparator. proximately 7 msec.You trim the delay by
nected MOSFETs turn on the line When the emitter current approaches selecting a resistance value from Pin 5 to
Ivoltage near the zero-crossing point zero, the collector voltage falls to 4V and raise (pins 5 to 8) or lower (pins 5 to 1)
and off when the 555-timer delay lapses. triggers the delay timer, initiating gate the upper comparator threshold at Pin 6.
That delay ranges from 1 to 7 msec. The drive to the switches. Positive-going pin Thus, load power is from 0 to 90% of
MOSFETs body diodes and the 1N4005 3 of the 555 also removes the trigger maximum (600W). You must use a heat
diodes form a full-wave bridge rectifier threshold by coupling to the diode OR sink for the power MOSFETs. (DI #2506).
that provides a floating 12V-dc level via gate. Because the circuit generates the
the 10-k , 3W resistor. The bridge si- 12V operating voltage only during off- To Vote For This Design,
multaneously delivers the crossing signal time, the limit for maximum delay is ap- Circle No. 370
Figure 1 1N4005 1N4005
N RLOAD L
IRFP264
IRFP264
10 10
CW
6.8k
2N3906 8 4
10k
50k
47k
3W
5
3
TLC555CP
6
+
47 F
2 7
1N5242B
25V
0.1 F
1
100k
470k
NOTE: VL,N=115V AC AT 60 Hz.
This smart switch provides a small initial current for loads with a normally high inrush current.
108 edn March 30, 2000 www.ednmag.com
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design
ideas
Circuit eliminates PC echoes
Hans Krobath, EEC, Nesconset, NY
ong-distance-telephone services 6V and closes with a gate voltage of 0V. within approximately 40 msec to the IC1B
available via the Internet often re- Q3 compensates for the switching-circuit threshold, producing a low-level output
Lquire the PC user to wear head- losses and buffers the output. R9 and R10 and turning on Q2. LED D2 lights when-
phones of a headset to prevent echo provide an appropriate input impedance ever no loudspeaker output is present,
caused by the microphone s picking up to Q3 and limit the output to 5V p-p, thus and the microphone input to the PC be-
the loudspeaker outputs. The circuit in preventing any possible damage to the comes enabled. D1 reduces the Q2 gate
Figure 1 eliminates the echo while using PC s microphone input. voltage to 0V when the IC1B output satu-
the existing PC microphone and speak- IC1, which acts as low-level retrigger- rates. You should set R1 such that ap-
ers for a comfortable conversation. The able monostable multivibrator, controls proximately a 100-mV p-p microphone
interface is between a standard electret the Q2 FET switch. Loudspeaker voltage input just triggers IC1, as indicated by the
condenser microphone and the micro- levels as low as 15 mV from the PC cause LED s extinguishing. This level prevents
phone input of the PC. The loudspeaker comparator IC1A s open-collector output any noise from the PC s loudspeaker out-
output of the PC serves to mute the mi- to discharge C6 via R18. The falling volt- put from falsely triggering the mono-
crophone input. R1 and R2 provide bias- age of C6, passing the threshold of com- stable multivibrator. (DI #2508).
ing for both the electret microphone and parator IC1B, produces a high output that
the Q1 emitter follower. Q2, a p-channel turns off Q2. Any input from the PC s
FET, acts as a switch that opens with the loudspeaker output discharges C6. The To Vote For This Design,
application of a gate voltage greater than absence of an input allows C6 to charge Circle No. 371
12V
Figure 1
R1
R9
C1 + 27k
R10
1.5k
150 pF 2k
Q1
2N3904
J1
Q3
Q2
C2 R4 C3 2N3906
2N5460 0.1 F
0.1 F
10k
S D
C4
R2 R3 0.22 F
J2
R5 R7
FROM PC MIC
20k 1k
1M 10k
R8
R11 R12
360k
R6 2.4k
10k
1M
TO PC MIC INPUT
12V
R21 R22 R23 R24
TALK
220k 10M
10k 4.7k
R15 R20 D2
LED
10M
IC1A R19 220k 5 8
2.2M +
8
LM393N 7
3
+
1 6
IC1B
D1
R14 2 4
LM393N
R18
1N4148
22k
J3
R25
4 1k
150k
C5
R16
C6
0.1 F
X 20k
0.022 F
R13 R17
FROM PC SPEAKER
1k
20k
SET TO 100-mV P-P THRESHOLD
Eliminate annoying echoes from loudspeaker-microphone feedback by using this simple circuit.
110 edn March 30, 2000 www.ednmag.com
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design
ideas
Clamping circuit dissipates minimal power
Carlisle Dolland, Allied Signal Aerospace, Torrance, CA
Q2
he circuit in Figure 1 Q2). For input voltages
D S
VOUT
is a quasi-linear regula- that exceed VR3 s break-
Ttor. It functions as a down voltage by approxi-
C3 D3
Q1
source follower for input G mately 3V, R6 and VR3 dis-
VIN
R6 D2
voltages greater than a preset sipate the energy the
VR3
level, determined by VR3. R1 R2 charge pump supplies. In
R4 R5
For input voltages lower this mode, the circuit
than the preset level, the pass functions as a source fol-
8
VR1 R3 7
4
element, Q2, operates as a lower, and the output
+
C2
6
3
saturated switch. The circuit voltage is approximately
2
_ IC1
comprises an oscillator, a 3V lower than VR3 s
ICM7555MTV
C1
1
charge pump, and a linear breakdown voltage. The
regulator. The linear circuit dissipates minimal
Figure 1
regulator, consisting power. During transients,
of Q1, R1,VR1, and R2, drives the load current deter-
a charge pump comprising This circuit clamps transient voltages and dissipates minimal power. mines the dissipation in
C2, D2, D3, and C3. The Q2. (DI #2499)
charge pump generates a voltage equal to voltage of VR1. For input voltages lower
To Vote For This Design,
the output of the linear regulator for in- than VR1 s breakdown voltage, the out-
Circle No. 372
put voltages greater than the breakdown put voltage is VOUT VIN IOUT (RON of
Piezo crystal monitors liquid level
J Jayapandian, IGCAR, Tamil Nadu, India
he simple and inexpensive circuit
in Figure 1 monitors the liq-
Figure 1
LIQUID
Tuid level in a container. The
piezo crystal, carefully mounted at the
bottom surface of the container, receives
it activation from the 74HCT14 hex
6.14 MHz CRYSTAL DATA BUS
VCC
Schmitt trigger. The crystal generates sta-
ble clock pulses according to its specifi-
CONTAINER
CLOCK 0
74HCT14
cation (for example, 6.14 MHz) when it
is in free air. The crystal-based clock
0TH COUNTER
GATE 0
drives the 0th counter in an 8254 pro-
grammable-counter/timer chip, pro-
1k 1k
FIRST COUNTER
56 pF OUT 1
grammed in Mode 0 as an event count-
8254
er. The first counter of the 8254,
CLOCK 1
programmed in Mode 1 as a retriggerable
SECOND COUNTER
one-shot whose time period is 1 sec, con-
trols the gate of the 0th counter. The first
counter allows the 0th counter to count
CS WR RD A0 A1
for a period of 1 sec. The counts in the air
medium serve as a reference. Depending
By measuring frequency shifts, this circuit provides a measure of liquid level.
on the height of the liquid level, the pres-
sure acting on the surface of the crystal
increases, thereby reducing reference- medium reference gives you the height of To Vote For This Design,
crystal clock frequency. The variation in the liquid level. (DI # 2507) Circle No. 373
clock frequency with respect to the air-
112 edn March 30, 2000 www.ednmag.com
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design
ideas
Switch intelligently controls current
Jim Hartmann, Silent Knight LLC, Maple Grove, MN
V DC
he circuit in Figure 1 can intelli-
gently control ac or dc current
Figure 1
VZC
D1
Twhen connected in series with
D2
D1N4002
OPTIONAL ZERO-
VDUTY
a load. The circuit  steals its power by D1N4002
CROSSING INPUT
turning off the load at a low duty cycle.
Q2
Q1
VCC
2N7002
The switch uses the MOSFETs parasitic
2N7002
body diode to its advantage. While the
RLOAD
+ VREG CONTROL
MOSFETs are off, the body diodes, along
C1 C2
V AC
with D1 and D2, serve as two legs of a
diode bridge. Current flows through the 0
load and the bridge, charging C1 to the
With a control circuit of your choice, you can obtain intelligent control of ac or dc current.
peak ac or dc voltage. The relatively small
control-block supply current continues
to flow through the load when the load the MOSFET s on-resistance. maximum duty cycle is 99.9%. By choos-
is turned off. The circuit has low inser- While the load is turned on, the con- ing MOSFETs and diodes with higher
tion loss because of the MOSFET s bidi- trol block draws current from C1. The cir- current ratings, you can adapt the circuit
rectional nature. The control block con- cuit must periodically recharge C1 by to control high-power loads. Many ap-
nects power to the load by turning briefly turning off the load . You can al- plications are possible lamp dimmers
MOSFETs Q1 and Q2 on. On alternating low the duty cycle to go as high as 99.99% and thermostats, for example. The con-
cycles, either Q1 or Q2 becomes reverse- with a high-current load and a micro- troller can optionally synchronize to the
biased, but current does not flow through power control circuit. The maximum ac zero-crossing point as shown. (DI #
the body diode because the MOSFET can duty cycle is approximately ILOAD/(ICON- 2505)
conduct in either direction. The insertion ILOAD). For example, with a 1A load To Vote For This Design,
TROL
loss is equivalent to the loss in two times and a control-circuit current of 1 mA, the Circle No. 374
Design Idea Entry Blank
Entry blank must accompany all entries. $100 Cash Award for all published Design Ideas. An additional $100 Cash Award for
the winning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine Entry blank must accompany all entries. (A separate entry
275 Washington St, Newton, MA 02458 blank for each author must accompany every entry.) Design
entered must be submitted exclusively to EDN, must not be
I hereby submit my Design Ideas entry.
patented, and must have no patent pending. Design must
Name be original with author(s), must not have been previously
published (limited-distribution house organs excepted), and
Title
must have been constructed and tested. Fully annotate all
circuit diagrams. Please submit text and listings by e-mail
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Company
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In submitting my entry, I agree to abide by the rules of the
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Signed
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114 edn March 30, 2000 www.ednmag.com
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