/// #1
///
/// ***

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:49:31 06/02/2009
// Design Name:
// Module Name: lol
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module lol(xclk, led);
input xclk;
output [11:0]led;


reg [23:0] suma;
reg [11:0] rejestr;

always @(posedge xclk)
suma <= suma + 1;

wire slwclk;
assign slwclk=suma[23];

assign led[0]=slwclk;
assign led[1]=slwclk+1;
assign led[2]=slwclk;
assign led[3]=slwclk+1;
assign led[4]=slwclk;
assign led[5]=slwclk+1;
assign led[6]=slwclk;
assign led[7]=slwclk+1;
assign led[8]=slwclk;
assign led[9]=slwclk+1;
assign led[10]=slwclk;
assign led[11]=slwclk+1;

// always @(posedge suma)
// suma <= suma + 1;

endmodule





/// #2
///
/// ***

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:49:31 06/02/2009
// Design Name:
// Module Name: lol
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module lol(xclk, led);
input xclk;
output [11:0]led;


reg [23:0] suma;
reg [11:0] rejestr;

always @(posedge xclk)
suma <= suma + 1;

wire slwclk;
assign slwclk=suma[23];

wire slw;
assign slw=suma[21];

assign led[0]=slwclk;
assign led[1]=slwclk+1;
assign led[2]=slw;
assign led[3]=slwclk+1;
assign led[4]=slwclk;
assign led[5]=slw;
assign led[6]=slwclk;
assign led[7]=slwclk+1;
assign led[8]=slw;
assign led[9]=slwclk+1;
assign led[10]=slwclk;
assign led[11]=slw;

// always @(posedge suma)
// suma <= suma + 1;

endmodule