----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:06:36 10/19/2011
-- Design Name:
-- Module Name: bin2seg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;



entity stoper is


Port (
anoda : out std_logic_vector (3 downto 0);

led : out std_logic_vector (7 downto 0);

clk : in std_logic ;


switch : in std_logic;
reset : in std_logic);

end stoper;



architecture Behavioral of stoper is


signal takt: std_logic;

signal zn1: std_logic_vector (3 downto 0) := "0000";

signal zn2: std_logic_vector (3 downto 0) := "0001";
signal zn3: std_logic_vector (3 downto 0) := "0010";
signal zn4: std_logic_vector (3 downto 0) := "0011";
signal onoff: std_logic;

function dekoder (bcd : std_logic_vector (3 downto 0)) return std_logic_vector is

variable TEMP : std_logic_vector (6 downto 0);

begin
if (bcd = "0000") then TEMP := "1000000";--0
elsif (bcd = "0001") then TEMP := "1111001";--1
elsif (bcd = "0010") then TEMP := "0100100";--2
elsif (bcd = "0011") then TEMP := "0110000";--3
elsif (bcd = "0100") then TEMP := "0011001";--4
elsif (bcd = "0101") then TEMP := "0010010";--5
elsif (bcd = "0110") then TEMP := "0000010";--6
elsif (bcd = "0111") then TEMP := "1111000";--7
elsif (bcd = "1000") then TEMP := "0000000";--8
elsif (bcd = "1001") then TEMP := "0010000";--9
end if;

return TEMP;
end dekoder;

begin

zegar: process(clk)

variable licz: std_logic_vector (15 downto 0);

begin

if rising_edge (clk) then
licz := licz+1;
if licz = 50000 then
takt <= not takt;
end if;
end if;

end process zegar;

display: process(takt)

variable digit_num : std_logic_vector (1 downto 0) := "00";

begin

if rising_edge (takt) then
if (digit_num = "00") then
anoda <= "0001";
led <= '1' & dekoder (zn1);
elsif (digit_num = "01") then

anoda <= "0010";

led <= '1' & dekoder (zn2);
elsif (digit_num = "10") then

anoda <= "0100";

led <= '1' & dekoder (zn3);
elsif (digit_num = "11") then

anoda <= "1000";

led <= '1' & dekoder (zn4);
end if;

digit_num := digit_num +1;

end if;

end process display;




when rising_edge (switch) then onoff <=not onoff







zliczanie: process(onoff,reset)

Begin
if (reset='1') then
zn1 <= "0000";
zn2 <= "0000";
zn3 <= "0000";
zn4 <= "0000";
end if;

if (onoff=1) then
zn4 <= zn4 + 1;
if(zn4 = 9) then
zn4 <= 0;
zn3 <= zn3 + 1;
if(zn3 = 9) then
zn3 <= 0;
zn2 <= zn2 + 1;
if(zn2 = 9) then
zn2 <= 0;
zn1 <= zn1 + 1;
if(zn1 = 9) then
zn1 <= 0;
end if;
end if;
end if;
end if;
end if;
end process zliczanie;
end Behavioral;



















----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:06:36 10/19/2011
-- Design Name:
-- Module Name: bin2seg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;


entity stoper is

Port (
anoda : out std_logic_vector (3 downto 0);
led : out std_logic_vector (7 downto 0);
clk : in std_logic );

end stoper;

architecture Behavioral of stoper is

signal takt: std_logic;
signal zn1: std_logic_vector (3 downto 0) := "0000";
signal zn2: std_logic_vector (3 downto 0) := "0001";
signal zn3: std_logic_vector (3 downto 0) := "0010";
signal zn4: std_logic_vector (3 downto 0) := "0011";

function dekoder (bcd : std_logic_vector (3 downto 0)) return std_logic_vector is

variable TEMP : std_logic_vector (6 downto 0);

begin
if (bcd = "0000") then TEMP := "1000000";--0
elsif (bcd = "0001") then TEMP := "1111001";--1
elsif (bcd = "0010") then TEMP := "0100100";--2
elsif (bcd = "0011") then TEMP := "0110000";--3
elsif (bcd = "0100") then TEMP := "0011001";--4
elsif (bcd = "0101") then TEMP := "0010010";--5
elsif (bcd = "0110") then TEMP := "0000010";--6
elsif (bcd = "0111") then TEMP := "1111000";--7
elsif (bcd = "1000") then TEMP := "0000000";--8
elsif (bcd = "1001") then TEMP := "0010000";--9
end if;

return TEMP;
end dekoder;

begin

zegar: process(clk)

variable licz: std_logic_vector (15 downto 0);

begin

if rising_edge (clk) then
licz := licz+1;
if licz = 50000 then
takt <= not takt;
end if;
end if;

end process zegar;

display: process(takt)

variable digit_num : std_logic_vector (1 downto 0) := "00";

begin

if rising_edge (takt) then
if (digit_num = "00") then
anoda <= "0001";
led <= '1' & dekoder (zn1);
elsif (digit_num = "01") then
anoda <= "0010";
led <= '1' & dekoder (zn2);
elsif (digit_num = "10") then
anoda <= "0100";
led <= '1' & dekoder (zn3);
elsif (digit_num = "11") then
anoda <= "1000";
led <= '1' & dekoder (zn4);
end if;

digit_num := digit_num +1;

end if;

end process display;



end Behavioral;









----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:01:38 10/17/2011
-- Design Name:
-- Module Name: bcd2led - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bcd2led is
Port ( x0,x1,x2,x3 : in STD_LOGIC;
a,b,c,d,e,f,g,base : out STD_LOGIC);
end bcd2led;

architecture Behavioral of bcd2led is

signal x:std_logic_vector (3 downto 0);
signal y:std_logic_vector (6 downto 0);

begin

base <= '0';
x <= (x3,x2,x1,x0);
(a,b,c,d,e,f,g) <= y;

with x select
y <= "0000001" when "0000",
"1001111" when "0001",
"0010101" when "0010",
"0000110" when "0011",
"1001100" when "0100",
"0100100" when "0101",
"0100000" when "0110",
"0001111" when "0111",
"0000000" when "1000",
"0000100" when "1001",--koniec cyfr
"0001000" when "1010",--a
"0000000" when "1011",--b
"0110001" when "1100",--c
"0000001" when "1101",--d
"0110000" when "1110",--e
"0111000" when others;--f

end Behavioral;










----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:29:26 11/03/2011
-- Design Name:
-- Module Name: licznik - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity licznik is
Port ( clk : in STD_LOGIC;
base : out STD_LOGIC;
led : out STD_LOGIC_VECTOR(6 downto 0));
end licznik;

architecture Behavioral of licznik is

component bcd2led
port ( x : in std_logic_vector(3 downto 0);
y : out std_logic_vector(6 downto 0));
end component;

signal a : std_logic_vector(25 downto 0);
signal b : std_logic_vector(3 downto 0);

begin

qrs : bcd2led port map (b,led);
base <= '1';
process(clk)
begin
if rising_edge(clk) then
a <= a+1;
if a <25000000 then
b <= b+1;
else
a <= (others => '0');
end if;
end if;
end process;
end Behavioral;