design
ideas
Edited by Bill Travis
High-side driver has fault protection
Carl Spearow, Tokyo Electron, Gilbert, AZ
igh-side drivers find common
24V
use in driving grounded so-
Figure 1
Hlenoid coils and other loads.
8
OFF
Short-circuit protection for such drivers IN
5V
SHORT-CIRCUIT TEST
is essential for avoiding damage from 3
SHDN 1
wiring faults and other causes. Polymer IC1 OUT
ON LP2951 (SO-8)
fuses are generally too slow, and discrete
7
FB
current-limiting circuits are large and 1 F
30V
1
LOAD
GND
cumbersome. The circuit in Figure 1 uses
4
a small, low-dropout linear regulator as a
high-side switch and provides inherent
current limiting and thermal shutdown.
The regulator comes in an SO-8 package.
The zener diode provides transient pro- This simple high-side driver provides current limiting as well as transient protection.
tection, and the output capacitor ensures
stability of the circuit. The circuit can
drive a 24V load at 100 mA. These
Figure 2
are adequate specs for many sole-
noid valves, relay coils, and other moder-
ate loads. During a short circuit, the reg-
ulator limits the current to 160 mA. This
current causes the die to overheat and en-
ter a thermal-shutdown state. Upon re-
moval of the short circuit, the device
cools down and resumes normal opera-
edn020822di298011
tion. The top trace in Figure 2 is the out-
Heather
High-side driver has fault protection ......103
Boost 3.3V to 5V with tiny
audio amplifier ............................................104
Add a signal-strength display
to an FM-receiver IC....................................106
Op amp linearizes response
of FET VCA ....................................................108
Convert voltage to potentiometer-
In the bottom trace, the output current limits itself to 160 mA during a short circuit.
wiper setting..................................................110
Make a DAC with a micro-
put voltage during a 1.3-sec short circuit. the IC then toggles on and off until re-
controller s PWM timer ..............................110
The bottom trace is the short-circuit cur- moval of the short circuit.
Publish your Design Idea in EDN. See the
rent, which limits itself at less than 200
What s Up section at www.edn.com.
mA. Note that the regulator goes into Is this the best Design Idea in this
thermal shutdown after 500 msec, and issue? Select at www.edn.com.
www.edn.com September 5, 2002 edn 103
|
design
ideas
Boost 3.3V to 5V with tiny audio amplifier
Wayne Rewinkel, National Semiconductor, Santa Clara, CA
D1 D3
his charge-pump circuit quietly
VIN
converts a 3.3V source to 5V
3.3V
6 + C1
Figure 1
Tat 500 mA (figures 1 and 2).
150 F
VIN 8
16V
National s (www.national.com) LM48-
A2OUT
5
A1OUT
71LD power amplifier makes this design
C2
LM4871LD RT RH1
idea both possible and practical, thanks 150 F
RS 10k 300k
+
16V
3
to its low output resistance, low cost, 0.6
A1+
D2 D4
compact size, and high dissipation capa-
4 RH2
A1
CT
bility. Its output resistance has an average 33k
4.7 nF
2 COUT
CIN
value of 0.6 : 0.5 to ground and 0.7 +
BP
150 F
150 F
CBP 16V
to VIN. Because it is a CMOS IC, each out- SD GND 16V
1 F
1 7
put can swing to its rail, limited only by
the resistance of the output transistor.
The leadless lead-frame package has a
NOTES:
1. D1 AND D2: MBRS12OT3.
footprint smaller than an SO-8 but pro-
2. C1 AND C2 ESR<11 .
vides a JA of 56 C/W when soldered to a
board with 1 sq in. of 1-oz copper ex- You can use a tiny audio amplifier to boost 3.3V to 5V with respectable current capability.
posed. This high thermal conductivity
couples with low output resistance to al- 50% duty cycle at a frequency approxi- 1 provide a circuit that can produce 5V at
low the 4871 to continuously deliver mated by the following equation:
ROUT = 2(RS + RDIODE + ESR +1/Cf )=
nearly 1A from each of its two outputs
1 4RTCT
= 4 µSEC + , 2(0.6 + 0.15 + 0.11 + 0.07) = 1.9 .
while operating at its full rated ambient
f ëÅ‚ öÅ‚
RH1 + RH2
ìÅ‚ ÷Å‚
temperature of 85 C. Internal thermal
ìÅ‚ ÷Å‚
RH2
íÅ‚ Å‚Å‚
shutdown protects the device from over- 0.5A from a 3.3V source at a conversion
f = 44 TO 53 kHz.
loads, and a shutdown pin allows you to efficiency of 78%. If necessary, you can
power down the device to less than 1 A. You can calculate the output voltage obtain tighter regulation figures at slight-
Figure 2 shows the full circuit across COUT from the following equation: ly lower output current by adding a low-
schematic, including the equivalent in- dropout linear regulator, such as the
VOUT = 2
ternal components. Amplifier IC1 is con- LP3961. At a 500-mA load it introduces
(VIN VDIODE IOUTRS IOUT(ESR) IOUT /Cf )
figured as an RC oscillator similar to a a drop of only 150 mV. Its addition pro-
= 2(3.3 0.35 0.3 0.05 0.062) = 5.08V,
555 timer. RT charges CT to the voltage set vides good line and load regulation over
by the resistor divider RH1 and RH2, caus- where IOUT is the average output current, the range IOUT 0 to 500 mA (Figure 3).
ing the amplifier to switch states, aided by VDIODE is the diode voltage drop at IOUT, You can also use the circuits of figures 1
the positive feedback from the RH resis- RS is the source resistance of IC1 and IC2, and 3 to provide 3.3V at 500 mA from a
tors. The remaining internal feedback ESR is that of C1 and C2, and C is the val- 2.5V source.
and biasing resistors connected to IC2 ue of C1 C2.
configure it as a simple inverter with bias The following equation approximates
at mid-supply. The amplifier outputs the effective output resistance at the load:
Is this the best Design Idea in this
switch rail-to-rail out of phase with a Component values as shown in Figure
issue? Select at www.edn.com.
D1 D3
VIN
VOUT
3.3V
Figure 3
D2 D4 VOUT
Figure 2
5V, 5A
3.3V 2 3
VIN VOUT
CIN
C2 COUT
C1
DOUBLER
LP3961EMPX
40k
RT
CIRCUIT
A2OUT
A1OUT
1
SD
COUT
CT 40k
A1 10 F
SD ERR GND
IC2
IC1 BP
A1+ 4 5
+
CBP
100k
RH1
VIN
100k
RH2
You can tighten voltage-regulation specs in Figure 1 s circuit by
This equivalent circuit shows the innards of the LM4871LD audio amplifier. adding a linear regulator.
104 edn September 5, 2002 www.edn.com
|
design
ideas
Add a signal-strength display to an FM-receiver IC
José Miguel-López, RF Center Ltd, Barcelona, Spain
he Philips (www.semiconductors. 180/3 60 kHz. So, you need neither ce- 12 is dc-coupled to an amplifier, IC2.
philips.com) TDA7000 integrates a ramic filters nor complex LC tank cir- Next, an envelope detector, IC3, yields a
Tmonaural FM-radio receiver from cuits to realize the IF filter. A simple ac- dc voltage proportional to the received-
the antenna connection to the audio out- tive filter using op amps can fulfill the signal strength. The Siemens (www.
put. External components include one task. The IC incorporates a correlation siemens.com) TCA965 window discrim-
tunable LC circuit for the local oscillator, muting system that suppresses intersta- inator, IC4, compares this envelope volt-
a few capacitors, two resistors, and a po- tion noise and spurious responses aris- age with a voltage derived from R1, R2,
tentiometer to control the variable-ca- ing from detuning. The muting circuit and R3 for the window s center (and R4
pacitance-diode tuning. The IC has an uses a second mixer. Its output is avail- and R5 for the window s half-width).
FLL (frequency-locked-loop) structure. able at Pin 1; you can use it to drive a de- Three LEDs show the result of the com-
The filtered output of the FM discrimi- tuning indicator. You can add a signal- parison (Low, OK, Good), but the display
nator frequency-modulates the local os- strength display to the TDA7000 using is valid only if the tuning is correct. If it s
cillator to provide negative-feedback the circuit in Figure 1. correct, the voltage at IC1, Pin 1 reaches
modulation. The result is compression of You can obtain the information relat- its maximum value, and the LM311
the signal at the output of the mixer. ed to the intensity of the received signal comparator, IC5, enables the TCA965.
Thus, the IF bandpass filter and the FM at the output of the IF filter (IC1, Pin 12).
discriminator deal with narrowband FM You can easily process this voltage with
signals. For a compression factor of K 3, common op amps, because the IF signal Is this the best Design Idea in this
the original FM bandwidth reduces to is centered on 70 kHz. The voltage at Pin issue? Select at www.edn.com.
R1 R2 R3
5V
9V
20k 5k 20k
10 nF
R5 R4
Figure 1
220k
4.7k
10 nF 100 nF 220 pF 150 pF
180 pF
9V
GOOD
11
9 2
4 15 18
IC2 8
12 + OK
1k
IC3
8 1/2
+ 6 13
1N4148
TL082
7 1/2
_ 7
LOW
TL082
3.3 nF
_
14
9
22 nF IC4 LEDs
10
5V
TCA965
3
20k
330 pF
1
1k
2.2 F 100k
IC1
5V
150
3.3 nF TDA7000
4.7 nF
nF
11
2.2 nF
1
14
9V
330 pF
17
2
39 pF
+
13 IC5
1.8
22k
LM311
12k
nF
_
16 5 6
9V
TO AUDIO
L1
AMPLIFIER
10k
56 nH
BB809
10 nF
100k
10k
9V
IC6 5V
7805
10 F 10 nF
You can easily add a signal-strength indicator to the Philips TDA7000 FM-receiver IC.
106 edn September 5, 2002 www.edn.com
|
design
ideas
Op amp linearizes response of FET VCA
Mike Irwin, Shawville, PQ, Canada
ets find common use
VC
in VCAs (voltage-
Figure 1 O TO 5V
Fcontrolled ampli-
R6
15V
50k
fiers) and attenuators, in
R5
which the FET serves as a vari- 50k
C4 R1 5
+
able resistance. A control volt-
7
R7
10 nF 300k
R2 IC1B
age applied to the gate sets the
FILM 50k
6
1k

channel resistance and overall
R8
50k
circuit gain. You frequently
R3
2
2.2k
need to select individual FETs
VREF=50 mV

1
because of wide spreads in IC1A C2
VDS=50 mV
3 C3
+ 10 F
FET characteristics. The cir-
220 pF
NONPOLAR
ID
CERAMIC
cuit in Figure 1 uses a master-
ELECTROLYTIC
R4
slave servo technique with a
4.7k
R9
Q1A D D Q1B
matched-FET pair to imple-
R13
220k
470k
ment voltage-controlled vari- 2
G G

C5
AUDIO OUT
VGS IC2
able gain. This gain is a linear
3
10 nF
6
+ 6V P-P
IN6263
function of the applied con- D1 S S FILM
SCHOTTKY
2N3958 AUDIO IN
trol voltage, VC. In contrast
DUAL FET 6V P-P
R12 R10
with variable-gain circuits us-
R11 100k C1
470k
100 nF
150
ing a single FET as the gain-
FILM
control element, the circuit in
Figure 1 exhibits minimum
gain for VC 0V and features a

linear increase in gain with in- This voltage-controlled amplifier has a dynamic range of 55 to 0 dB.
creasing VC. The self-biasing
operation of the circuit also compensates in combination with R12, reduce distor-
for unit-to-unit variations in the FET tion at higher signal levels. With the val-
characteristics, thereby making device se- ues shown, the gain increases linearly
lection less critical. from 55 to 0 dB as VC varies from 0 to
The circuit maintains the drain volt- 5V. The circuit accepts a 6V p-p input
age, VDS, of Q1A at a low value (VREF 50 signal. Figure 2 shows the result of mod-
mV) to ensure that the FET operates in ulating a 500-Hz sine wave with a 0 to 4V
the resistive region of its ID versus VDS triangle wave.
characteristic curve. Op amp IC1A servos For best performance, IC1 should be a
the VGS of Q1A to maintain VDS at VREF, low-offset, low-input-current unit, such
while Q1A sinks the current from as the OP-290. IC2 should be a high-gain-
A 0 to 4V triangle wave linearly
Figure 2
the Howland current source bandwidth-product, low-noise amplifier,
modulates the 500-Hz audio input.
IC1B. The sourced current is ID(mA) such as the NE5534. You can successful-
VC/R5(k ), where VC is the control ly use inexpensive units, such as the
voltage. The channel resistance, RD, in sets the gain: Gain 1 R9/RD 1 R9/ LF353 and LF351, at reduced gains. You
kilohms is then RD VREF/ID 0.05/ID (VREF R5/VC). can also operate the circuit from 5V
0.05 R5/VC. The same VGS applies to Q1B The maximum gain is 1 R9/R0. R0 is supplies (with R1 changed to 100 k ), us-
through R12. Because Q1 is a well- the minimum channel resistance for ing an OP-290 for IC1 and a TL031 for
matched monolithic dual FET, Q1A and VGS 0V, approximately 450 for the IC2. The maximum supply current for
Q1B have identical channel resistance, RD. 2N3958. The minimum gain is unity, 5V operation is 0.33 mA, showing that
VGS varies from approximately 370 mV when the FET does not conduct (VGS low-power operation is possible.
(which D1 limits to prevent gate-source VPINCHOFF). The circuit attenuates the au-
conduction) to VP (approximately 1.7V dio-input signal level to lower than 10
for the 2N3958) as VC varies from 0 to 5V. mV p-p. This attenuation minimizes dis-
IC2 is a variable-gain, noninverting am- tortion in the FET and also sets the clip- Is this the best Design Idea in this
plifier, in which the controlled RD of Q1B ping level at the output of IC2. R13 and C5,
issue? Select at www.edn.com.
108 edn September 5, 2002 www.edn.com
|
design
ideas
Convert voltage to potentiometer-wiper setting
Chuck Wojslaw, Catalyst Semiconductor, Sunnyvale, CA, and
Chris Wojslaw, Conexant Systems, Newport Beach, CA
he circuit in Figure 1 con-
5V 6.8k
verts an analog input 5V
0.01 F
1%
Figure 1
Tvoltage, VIN, to a pro-
8
8
portional wiper setting of a DPP 100k
7 5
10k 2
U/D
(digitally programmable poten-
+
IC1
5V
IC5 3
VIN 0.1 F
LM33IA 3
tiometer). The potentiometer s
CAT5114
0 TO 1V 1
+
IC4
INC
wiper setting, which varies from
1,6
7
VPULSES
CS 5
position 0 through 31, corre-
6
10k
4 2
sponds to the input voltage,
RS
100k
1 F 15k
which varies from 0 to 1V dc.
1%
1%
47
The CAT5114, IC5, is a 32-tap
5V
potentiometer with an incre-
ment/decrement interface. VIN
8
R1 280k
typically models the output volt-
10k 3
1%
VGATE
age of a sensor whose value sets 1%
7,6
IC2
IC3
a parameter of an analog circuit
LM555
2
5
in the signal-processing portion
C1
of a system. The basic principle
0.01 F 0.1 F 1
0.01 F
of the circuit is to convert the in-
CALIBRATE
VTRIG
(MIC)
put voltage to a number of puls-
es and let each pulse advance the
potentiometer s wiper within a
certain period of time. IC1 is a You can convert an analog voltage to a wiper setting in a digitally programmable potentiometer.
voltage-to-frequency converter.
This circuit converts the 0 to 1V dc input sor-generated logic signal. The 31-msec up. When the DPP powers up, the IC re-
voltage to an output frequency, VPULSES, gating signal is chosen to correspond to calls wiper setting 00 from nonvolatile
that varies from 0 to 1 kHz. the highest tap position of the poten- memory. When you depress the calibrate
This free-running oscillator advances tiometer at the highest frequency of the switch, the wiper increments from 00 to
the wiper of the potentiometer for only voltage-to-frequency converter. For a a setting corresponding to the input volt-
31 msec, established by VGATE and the 100-tap potentiometer, the gating signal age, VIN . You can use the three-terminal
AND function of IC4. VGATE is the output measures 99 msec for the same sensitivi- resistive network of the potentiometer to
of the one-shot multivibrator, IC2. The ty of the voltage-to-frequency converter. control the gain of an amplifier (shown
one-shot receives its trigger from a cali- You can trim the 15-k resistor, RS, to in broken lines in Figure 1), a parameter
brate switch or an external signal. The match the timing of the 331 converter to of a filter, or the coefficient of a mathe-
hex inverters of IC3 debounce the cali- the pulse width of the 555. matical operator.
brate switch. R1C1 differentiate the volt- Tap position 00 of the digitally con-
age-level shift generated by the switch to trolled potentiometer is stored in the
provide a nominal 100- sec trigger, DPP s nonvolatile memory and the po- Is this the best Design Idea in this
VTRIG, to IC2.VTRIG could also be a proces- tentiometer s up/down control is set to issue? Select at www.edn.com.
Make a DAC with a microcontroller s PWM timer
Mike Mitchell, Texas Instruments Inc
any embedded-microcontroller erating the required analog signals. You and a dc voltage. A PWM signal is a dig-
applications require generation of can use PWM signals to create both dc ital signal with fixed frequency but vary-
Manalog signals. An integrated or and ac analog signals. This Design Idea ing duty cycle. If the duty cycle of the
stand-alone DAC fills the role. However, shows how to use a PWM timer to si- PWM signal varies with time and you fil-
you can often use PWM signals for gen- multaneously create a sinusoid, a ramp, ter the PWM signal, the output of the fil-
110 edn September 5, 2002 www.edn.com
|
design
ideas
ter is an analog signal (Figure 1). If you the counter reaches the CCR0 value. This
MSP430
build a PWM DAC in this manner, its scheme provides positive pulses equiva-
MICRO-
CONTROLLER
resolution is equivalent to the resolution lent to the value in CCRx on each re-
of the PWM signal you use to create the spective output. If you use the timer in 8-
PWM ANALOG
OUTPUT FILTER
DAC. The PWM output signal requires bit mode, the reset/set output mode is
a frequency that is equivalent to the up- unavailable for the PWM outputs be-
date rate of the DAC, because cause the reset/set mode requires CCR0.
Figure 1
each change in PWM duty cycle The timer s clock rate is 2.048 MHz. Fig-
A PWM signal passing through a filter yields
is the equivalent of one DAC sample. The ure 3 shows the sine and ramp wave-
frequency the PWM timer requires de- and analog signal.
forms. The sine wave in this example uses
pends on the required PWM signal fre- 32 samples per cycle. The sample values
quency and the desired resolution. The giving the counter an effective 8-bit are in a table at the beginning of the pro-
required frequency is FCLOCK FPWM 2n, length.You can find this register and oth- gram. A pointer points to the next value
where FCLOCK is the required PWM-timer ers in a DAC demonstration program for in the sine table, so that, at the end of
frequency, FPWM is the PWM-signal fre- the MSP430 microcontroller. You can each PWM cycle, the new value of the
quency, and n is the desired DAC reso- download the program from the Web ver- sine wave is written to the capture/com-
lution in bits. sion of this Design Idea at www.edn.com. pare register of the PWM timer.
Figure 2 depicts a circuit that delivers CCR1 and output TB1 produce the The ramp in this example does not re-
a 250-Hz sine wave, a 125-Hz ramp, and sine wave. CCR2 and TB2 generate the quire a table of data values. Rather, the
a dc signal. The desired sampling rate is ramp, and CCR3 and TB3 yield the dc ramp simply increments the duty cycle
8 kHz (32 samples for each sine-wave cy- value. For each output, the output mode for each cycle of the PWM signal until it
cle (16 oversampled), and 64 samples is the reset/set mode. In this mode, each reaches the maximum and then starts
for each ramp cycle (32 oversampled)). output resets when the counter reaches over at the minimum duty cycle. This
These figures result in a required PWM- the respective CCRx value and sets when gradual increase in PWM-signal duty cy-
signal frequency of 8 kHz and a cle results in a ramp voltage
VCC
MSP430F149IPM
required PWM clock fre- when the signal passes through
Figure 2
quency of 2.048 MHz. It is a filter. You control the dc lev-
DVCC
AVCC R1 R2
usually best for the PWM signal el by simply setting and not
2k 1M
frequency to be much higher than changing the value of the
P4.1/TB1
XIN
C1
C2
the desired bandwidth of the sig- PWM-signal duty cycle. The dc
32,768 Hz 0.1 F
200 pF
nals to be produced. Generally, the level is directly proportional to
XOUT/TCLK
2k 1M
higher the PWM frequency, the the duty cycle of the PWM sig-
P4.2/TB2
lower the order of filter required nal. Figure 2 shows the recon-
0.1 F 200 pF
DVSS
and the easier it is to build a suit- struction filters used for each
able filter. This design uses Timer signal in this example. The fil-
AVSS P4.3/TB3 330k
B of the MSP430 in 16-bit mode ter for the ac signals is a sim-
DC
and in  up mode, in which the ple two-pole, stacked-RC filter,
0.05 F
counter counts up to the contents which is simple and has no ac-
of capture/compare register 0 tive components. This type of
(CCR0) and then restarts at zero. A microcontroller and some passive filters produce a sine wave, a filter necessitates a higher sam-
CCR0 is loaded with 255, thereby ramp, and a dc signal. pling rate than would be re-
Figure 3
(a)
(b)
The microcontroller s PWM timer produces an ac signal (a) and a dc signal (b) of a sine wave and a ramp with 8-bit resolution.
112 edn September 5, 2002 www.edn.com
|
design
ideas
quired if the filter had a higher order. starts the timer. Finally, the MSP430
RESET
With the type of filter shown in Fig- goes into low-power mode
Figure 4
ure 2, you should use at least a 16 0 (LPM0) to conserve pow-
DISABLE WATCHDOG
oversampling rate. TIMER_B er. The CPU wakes up to handle
TIMER, INITIALIZE I/O
CCIFGO
PORTS, AND SET UP
INCREMENT AN AND
The filter yields its best response each CCIFG0 interrupt from the
INTERRUPT
CLOCK SYSTEM
SINE-TABLE POINTER
when R2 R1. Also, setting the cut- AND MOVE NEW PWM timer and then re-enters
VALUE TO CCR1
off frequency too close to the band- LPM0. (See references 1, 2, and 3
CALL DELAY LOOP FOR
CRYSTAL STABILIZATION
width edge causes a fair amount of at- for more information on the DCO
tenuation. To reduce the amount of and the MSP430 family.)
INCREMENT AN AND
CALL SOFTWARE
RAMP VALUE AND
attenuation in the filter, set the cutoff
FREQUENCY-LOCK LOOP
MOVE TO CCR2
FOR DCO STABILIZATION
frequency above the bandwidth edge References
but much lower than the frequency of 1. MSP430x13x/14x data sheet,
SET UP TIMER_B AND
RETURN FROM
the PWM signal. The filter for the dc Texas Instruments document SLAS-
START PWM GENERATION
INTERRUPT
value serves for charge storage rather 272.
than ac-signal filtering. Therefore, it 2. MSP430x1xx Family User s
ENTER LPMO
uses a simple, single-pole RC filter. Guide, Texas Instruments docu-
Figure 4 shows the software flow for This software flow diagram shows how the PWM timer ment SLAU049.
the DAC. After a reset, the routine generates the sine and ramp signals. 3.  Controlling  the DCO of the
stops the watchdog timer, configures MSP430x11x, Texas Instruments
the output ports, and sets up the clock Next, the routine calls the calibration document SLAA074.
system. Next, the software calls a delay to routine to set the operating frequency to
allow the 32,768-Hz crystal to stabilize to 2.048 MHz. After the DCO calibration,
calibrate the DCO (digitally controlled the program sets up Timer_B, CCR1 and Is this the best Design Idea in this
oscillator). CCR2 for PWM generation and then issue? Select at www.edn.com.
114 edn September 5, 2002 www.edn.com
|