S E M I C O N D U C T O R CA3140
BiMOS Operational Amplifier
with MOSFET Input/Bipolar Output
April 1994
Features Description
" MOSFET Input Stage The CA3140A and CA3140 are integrated circuit operational amplifiers
that combine the advantages of high voltage PMOS transistors with
- Very High Input Impedance (ZIN) -1.5T&! (Typ.)
high voltage bipolar transistors on a single monolithic chip. Because of
- Very Low Input Current (Il) -10pA (Typ.) at Ä…15V
this unique combination of technologies, this device can now provide
- Wide Common Mode Input Voltage Range
designers, for the first time, with the special performance features of
(VlCR) - Can be Swung 0.5V Below Negative
the CA3130 CMOS operational amplifiers and the versatility of the 741
Supply Voltage Rail
series of industry standard operational amplifiers.
- Output Swing Complements Input Common
The CA3140A and CA3140 BiMOS operational amplifiers feature gate
Mode Range
protected MOSFET (PMOS) transistors in the input circuit to provide
very high input impedance, very low input current, and high speed per-
" Directly Replaces Industry Type 741 in Most
formance. The CA3140A and CA3140 operate at supply voltage from
Applications
4V to 36V (either single or dual supply). These operational amplifiers
are internally phase compensated to achieve stable operation in unity
Applications
gain follower operation, and additionally, have access terminal for a
" Ground-Referenced Single Supply Amplifiers in
supplementary external capacitor if additional frequency roll-off is
Automobile and Portable Instrumentation
desired. Terminals are also provided for use in applications requiring
input offset voltage nulling. The use of PMOS field effect transistors in
" Sample and Hold Amplifiers
the input stage results in common mode input voltage capability down
" Long Duration Timers/Multivibrators
to 0.5V below the negative supply terminal, an important attribute for
(µseconds-Minutes-Hours)
single supply applications. The output stage uses bipolar transistors
and includes built-in protection against damage from load terminal
" Photocurrent Instrumentation
short circuiting to either supply rail or to ground.
" Peak Detectors
The CA3140 Series has the same 8-lead pinout used for the  741 and
" Active Filters
other industry standard op amps. The CA3140A and CA3140 are
intended for operation at supply voltages up to 36V (Ä…18V).
" Comparators
" Interface in 5V TTL Systems and Other Low
Ordering Information
Supply Voltage Systems
PART NUMBER TEMP. RANGE PACKAGE
" All Standard Operational Amplifier Applications
CA3140AE -55oC to +125oC 8 Lead Plastic DIP
" Function Generators
CA3140AM -55oC to +125oC 8 Lead SOIC
" Tone Controls
CA3140AS -55oC to +125oC 8 Pin Can, Lead Formed
" Power Supplies
CA3140AT -55oC to +125oC 8 Pin Can
" Portable Instruments
CA3140BT -55oC to +125oC 8 Pin Can
CA3140E -55oC to +125oC 8 Lead Plastic DIP
" Intrusion Alarm Systems
CA3140M -55oC to +125oC 8 Lead SOIC
CA3140M96 -55oC to +125oC 8 Lead SOIC*
CA3140T -55oC to +125oC 8 Pin Can
* Denotes Tape and Reel
Pinouts
CA3140 (TO-5 STYLE CAN) CA3140 (PDIP, SOIC)
TOP VIEW TOP VIEW
TAB
STROBE
OFFSET
8
1 8
STROBE
NULL
OFFSET
1 7 V+
NULL
2
7
INV. INPUT V+


INV.
2 6 OUTPUT
+
NON-INV.
+
INPUT 3 6 OUTPUT
INPUT
OFFSET
3 5 OFFSET
NON-INV.
V- 4
5
NULL
NULL
INPUT 4
V- AND CASE
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
File Number 957.2
Copyright © Harris Corporation 1993
2-123
Specifications CA3140, CA3140A
Absolute Maximum Ratings Operating Conditions
DC Supply Voltage (Between V+ and V- Terminals). . . . . . . . . . 36V OperatingTemperature Range (All Types). . . . . . . . -55oC to +125oC
Differential Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 8V Storage Temperature Range (All Types). . . . . . . . . -65oC to +150oC
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . .(V+ +8V) To (V- -0.5V)
Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short Circuit Duration * . . . . . . . . . . . . . . . . . . . . . . Indefinite
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Junction Temperature (Plastic Package) . . . . . . . . . . . . . . . +150oC
Lead Temperature (Soldering 10 Sec.). . . . . . . . . . . . . . . . . +300oC
* Short circuit may be applied to ground or to either supply.
CAUTION: Stresses above those listed in  Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications V+ = +15V, V- = -15V, TA = +25oC
PARAMETERS SYMBOL TEST CONDITIONS CA3140A CA3140 UNITS
Input Offset Voltage Adjustment Resistor Typical Value of Resistor 18 4.7 k&!
Between Term. 4 and 5 or 4
and 1 to Adjust Max. VI0
Input Resistance RI 1.5 1.5 T&!
Input Capacitance CI 44 pF
Output Resistance RO 60 60 &!
Equivalent Wideband Input Noise Voltage eN BW = 140kHz 48 48 µV
(See Figure 35) RS = 1 M&!
Equivalent Input Noise Voltage (See Figure 7) eN f = 1kHz RS = 100&! 40 40 nV/"Hz
f = 10 kHz 12 12 nV/"Hz
Short Circuit Current to Opposite Supply
Source IOM+40 40 mA
Sink IOM-18 18 mA
Gain-Bandwidth Product, (See Figures 2 & 15) fT 4.5 4.5 MHz
Slew Rate, (See Figure 3) SR 9 9 V/µs
Sink Current From Terminal 8 To Terminal 4 to Swing 220 220 µA
Output Low
Transient Response: RL = 2k&!
CL = 100pF
Rise Time tR 0.08 0.08 µs
Overshoot (See Figure 34) OS 10 10 %
Settling Time at 10 VP-P, (See Figure 14) tS RL = 2k&!
CL = 100pF
1mV Voltage Follower 4.5 4.5 µs
10mV 1.4 1.4 µs
2-124
Specifications CA3140, CA3140A
Electrical Specifications For Equipment Design. At V+ = 15V, V- = 15V, TA = +25oC, Unless Otherwise Specified
LIMITS
CA3140A CA3140
PARAMETERS SYMBOL MIN TYP MAX MIN TYP MAX UNITS
Input Offset Voltage |VIO| - 2 5 - 5 15 mV
Input Offset Current |IIO| - 0.5 20 - 0.5 30 pA
Input Current II - 10 40 - 10 50 pA
Large Signal Voltage Gain (Note 1) AOL 20 l00 - 20 100 - kV/V
(See Figures 1, 15)
86 100 - 86 100 - dB
Common Mode Rejection Ratio CMRR - 32 320 - 32 320 µV/V
(See Figure 6)
70 90 - 70 90 - dB
Common Mode Input Voltage Range VICR -15 -15.5 12 -15 -15.5 11 V
(See Figure 17) to to
+12.5 +12.5
Power-Supply Rejection Ratio, PSRR - 100 150 - 100 150 µV/V
"VIO/"VS (See Figure 8)
76 80 - 76 80 - dB
Max. Output Voltage (Note 2) VOM+ +12 13 - +12 13 - V
(See Figures 10, 17)
VOM- -14 -14.4 - -14 -14.4 - V
Supply Current (See Figure 4) I+ - 4 6 - 4 6 mA
Device Dissipation PD - 120 180 - 120 180 mW
Input Offset Voltage Temp. Drift, - 6 - - 8 - µV/o C
"VIO/"T
NOTES:
1. At VO = 26Vp-p, +12V, 14V and RL = 2k&!.
2. At RL = 2k&!.
Electrical Specifications For Design Guidance. At V+ = 5 V, V- = 0V, TA = +25oC
PARAMETERS SYMBOL CA3140A CA3140 UNITS
Input Offset Voltage |VIO|2 5 mV
Input Offset Current |IIO| 0.1 0.1 pA
Input Current II 22 pA
Input Resistance RI 11 T&!
Large Signal Voltage Gain AOL 100 100 kV/V
(See Figures 1, 15)
100 100 dB
2-125
Specifications CA3140, CA3140A
Electrical Specifications For Design Guidance. At V+ = 5 V, V- = 0V, TA = +25oC (Continued)
PARAMETERS SYMBOL CA3140A CA3140 UNITS
Common Mode Rejection Ratio, CMRR 32 32 µV/V
90 90 dB
Common Mode Input Voltage Range (See Figure 17) VICR -0.5 -0.5 V
2.6 2.6 V
Power Supply Rejection Ratio PSRR 100 100 µV/V
"VI0/"VS
80 80 dB
Maximum Output Voltage (See Figures 10, 17) VOM+3 3 V
VOM- 0.13 0.13 V
Maximum Output Current:
Source IOM+ 10 10 mA
IOM-
Sink 1 1 mA
Slew Rate (See Figure 3) SR 7 7 V/µs
Gain-Bandwidth Product (See Figure 2) fT 3.7 3.7 MHz
Supply Current (See Figure 4) I+ 1.6 1.6 mA
Device Dissipation PD 88 mW
Sink Current from Term. 8 to Term. 4 to Swing Output Low 200 200 µA
2-126
CA3140A, CA3140
Block Diagram
2mA 4mA
7 V+
BIAS CIRCUIT
CURRENT SOURCES
AND REGULATOR
200µA 1.6mA 200µA 2µA 2mA
+
3
A H"
6
INPUT OUTPUT
A H" 10 A H" 1
10,000
-
2
C1
12pF
4 V-
5 1 8 STROBE
OFFSET
NULL
Schematic Diagram
BIAS CIRCUIT INPUT STAGE SECOND STAGE OUTPUT STAGE DYNAMIC CURRENT SINK
7 V+
C1
D7
R13
5k
Q20
Q3
R9
Q1 Q2
50&!
D8
R10
Q4
1k
Q6 Q5
R14
20k
R12
Q19 R11
12k
20&!
Q7
Q21
Q17
R1 R8
1k
8k Q8
Q18
6 OUTPUT
D2
D3 D4
D5
INVERTING
2
INPUT
- Q9 Q10
+
NON-INVERTING
3
INPUT C1
R2 R3
500&! 500&!
12pF
Q15 Q16
Q14
Q13
Q11 Q12
D6
R4
R5 R6 R7
500&!
500&! 50&! 30&!
5 1 8 4
OFFSET NULL STROBE V-
ALL RESISTANCE VALUES ARE IN &!
2-127
CA3140A, CA3140
Circuit Description
As shown in the block diagram, the input terminals may be When the CA3140 is operating such that output terminal 6 is
operated down to 0.5V below the negative supply rail. Two sourcing current, transistor Q18 functions as an emitter-
class A amplifier stages provide the voltage gain, and a follower to source current from the V+ bus (terminal 7), via
unique class AB amplifier stage provides the current gain D7, R9, and R11. Under these conditions, the collector
necessary to drive low-impedance loads. potential of Q13 is sufficiently high to permit the necessary
flow of base current to emitter follower Q17 which, in turn,
A biasing circuit provides control of cascoded constant
drives Q18.
current flow circuits in the first and second stages. The
CA3140 includes an on chip phase compensating capacitor When the CA3140 is operating such that output terminal 6 is
that is sufficient for the unity gain voltage follower sinking current to the V- bus, transistor Q16 is the current
configuration. sinking element. Transistor Q16 is mirror connected to D6,
R7, with current fed by way of Q21, R12, and Q20. Transistor
Input Stages
Q20, in turn, is biased by current flow through R13, zener
D8, and R14. The dynamic current sink is controlled by
The schematic diagram consists of a differential input stage
voltage level sensing. For purposes of explanation, it is
using PMOS field-effect transistors (Q9, Q10) working into a
assumed that output terminal 6 is quiescently established at
mirror pair of bipolar transistors (Q11, Q12) functioning as
the potential midpoint between the V+ and V- supply rails.
load resistors together with resistors R2 through R5. The
When output current sinking mode operation is required, the
mirror pair transistors also function as a differential-to-single-
collector potential of transistor Q13 is driven below its
ended converter to provide base current drive to the second
quiescent level, thereby causing Q17, Q18 to decrease the
stage bipolar transistor (Q13). Offset nulling, when desired,
output voltage at terminal 6. Thus, the gate terminal of
can be effected with a 10k&! potentiometer connected across
PMOS transistor Q21 is displaced toward the V- bus, thereby
terminals 1 and 5 and with its slider arm connected to
reducing the channel resistance of Q21. As a consequence,
terminal 4. Cascode connected bipolar transistors Q2, Q5
there is an incremental increase in current flow through Q20,
are the constant current source for the input stage. The base
R12, Q21, D6, R7, and the base of Q16. As a result, Q16
biasing circuit for the constant current source is described
sinks current from terminal 6 in direct response to the
subsequently. The small diodes D3, D4, D5 provide gate
incremental change in output voltage caused by Q18. This
oxide protection against high voltage transients, e.g., static
sink current flows regardless of load; any excess current is
electricity.
internally supplied by the emitter-follower Q18. Short circuit
protection of the output circuit is provided by Q19, which is
Second Stage
driven into conduction by the high voltage drop developed
Most of the voltage gain in the CA3140 is provided by the
across R11 under output short circuit conditions. Under
second amplifier stage, consisting of bipolar transistor Q13
these conditions, the collector of Q19 diverts current from
and its cascode connected load resistance provided by
Q4 so as to reduce the base current drive from Q17, thereby
bipolar transistors Q3, Q4. On-chip phase compensation,
limiting current flow in Q18 to the short circuited load
sufficient for a majority of the applications is provided by C1.
terminal.
Additional Miller-Effect compensation (roll off) can be
Bias Circuit
accomplished, when desired, by simply connecting a small
capacitor between terminals 1 and 8. Terminal 8 is also used
Quiescent current in all stages (except the dynamic current
to strobe the output stage into quiescence. When terminal 8
sink) of the CA3140 is dependent upon bias current flow in
is tied to the negative supply rail (terminal 4) by mechanical
R1. The function of the bias circuit is to establish and
or electrical means, the output terminal 6 swings low, i.e.,
maintain constant current flow through D1, Q6, Q8 and D2.
approximately to terminal 4 potential.
D1 is a diode connected transistor mirror connected in
parallel with the base emitter junctions of Q1, Q2, and Q3.
Output Stage
D1 may be considered as a current sampling diode that
The CA3140 Series circuits employ a broad band output
senses the emitter current of Q6 and automatically adjusts
stage that can sink loads to the negative supply to
the base current of Q6 (via Q1) to maintain a constant
complement the capability of the PMOS input stage when
current through Q6, Q8, D2. The base currents in Q2, Q3
operating near the negative rail. Quiescent current in the
are also determined by constant current flow D1.
emitter-follower cascade circuit (Q17, Q18) is established by
Furthermore, current in diode connected transistor Q2
transistors (Q14, Q15) whose base currents are  mirrored to
establishes the currents in transistors Q14 and Q15.
current flowing through diode D2 in the bias circuit section.
2-128
CA3140, CA3140A
Metallization Mask Layout
65
0 10 20 30 40 50 60
61
60
50
40
58-66
30
(1.473-1.676)
20
10
0
4-10
(0.102-0.254)
62-70
(1.575-1.778)
Dimensions in parenthesis are in millimeters and are derived
from the basic inch dimensions as indicated. Grid graduations
are in mils (10-3 inch).
The photographs and dimensions represent a chip when it is
part of the wafer. When the wafer is cut into chips, the cleavage
angles are 57o instead of 90ż with respect to the face of the
chip. Therefore, the isolated chip is actually 7 mils (0.17mm)
larger in both dimensions.
Typical Performance Curves
20
RL = 2k&! RL = 2k&!
CL = 100pF
10
TA = -55oC
8
+25oC
+25oC
125
+125oC
6
+125oC
TA = -55oC
100
5
75
4
50
3
2
25
0 1
0 5 10 15 20 25 0 5 10 15 20 25
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 1. OPEN LOOP VOLTAGE GAIN vs SUPPLY FIGURE 2. GAIN BANDWIDTH PRODUCT vs SUPPLY
VOLTAGE AND TEMPERATURE VOLTAGE AND TEMPERATURE
2-129
OPEN-LOOP VOLTAGE GAIN (dB)
GAIN BANDWIDTH PRODUCT (MHz)
CA3140, CA3140A
Typical Performance Curves (Continued)
RL = 2k&! RL = "
CL = 100pF
7
TA = -55oC
6
+25oC
+25oC
5
+125oC
+125oC
20
TA = -55oC
4
15
3
10
2
5
1
0
0
0 5 10 15 20 25
0 5 10 15 20 25
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
FIGURE 3. SLEW RATE vs SUPPLY VOLTAGE AND FIGURE 4. QUIESCENT SUPPLY CURRENT vs SUPPLY
TEMPERATURE VOLTAGE AND TEMPERATURE
SUPPLY VOLTAGE: V+ = 15V, V- = -15V 120
SUPPLY VOLTAGE: V+ = 15V, V- = -15V
TA = +25oC
TA = +25oC
25
100
20
80
CA3140B
15
60
CA3140, CA3140A
10
40
5 20
0 0
2 4 6 8 2 4 6 8 2
101 102 103 104 105 106 107
10K 100K 1M 4M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. MAXIMUM OUTPUT VOLTAGE SWING vs FIGURE 6. COMMON MODE REJECTION RATIO vs FREQUENCY
FREQUENCY
1000
SUPPLY VOLTAGE: V+ = 15V, V- = -15V
8
SUPPLY VOLTAGE: V+ = 15V, V- = -15V
6
TA = +25oC
TA = +25oC
4
100
CA3140B
2
+PSRR
CA3140,
80
100
8
CA3140A
6
4
60
2
40
10 -PSRR
8
6
4
20
POWER SUPPLY REJECTION RATIO
2
(PSRR) = "VIO/"VS
0
1
101 102 103 104 105 106 107
1 101 102 103 104 105
FREQUENCY (Hz) FREQUENCY (Hz)
FIGURE 7. EQUIVALENT INPUT NOISE VOLTAGE vs FIGURE 8. POWER SUPPLY REJECTION RATIO vs FREQUENCY
FREQUENCY
2-130
SLEW RATE (V/
µ
s)
QUIESCENT SUPPLY CURRENT (mA)
P-P
OUTPUT SWING (V
)
COMMON-MODE REJECTION RATIO (dB)
POWER SUPPLY REJECTION RATIO (dB)
EQUIVALENT INPUT NOISE VOLTAGE (nV
"
Hz)
CA3140, CA3140A
Figure 10 shows output current sinking capabilities of the
Applications Considerations
CA3140 at various supply voltages. Output voltage swing to
the negative supply rail permits this device to operate both
Wide dynamic range of input and output characteristics with
power transistors and thyristors directly without the need for
the most desirable high input impedance characteristics is
level shifting circuitry usually associated with the 741 series
achieved in the CA3140 by the use of an unique design based
of operational amplifiers.
upon the PMOS Bipolar process. Input common mode voltage
range and output swing capabilities are complementary,
Figure 13 shows some typical configurations. Note that a
allowing operation with the single supply down to 4V.
series resistor, RL, is used in both cases to limit the drive
available to the driven device. Moreover, it is recommended
The wide dynamic range of these parameters also means
that this device is suitable for many single supply applica- that a series diode and shunt diode be used at the thyristor
input to prevent large negative transient surges that can
tions, such as, for example, where one input is driven below
appear at the gate of thyristors, from damaging the inte-
the potential of terminal 4 and the phase sense of the output
grated circuit.
signal must be maintained  a most important consideration
in comparator applications.
Output Circuit Considerations 7
TA = +125oC
FOR TO-5 PACKAGES
Excellent interfacing with TTL circuitry is easily achieved
6
with a single 6.2V zener diode connected to terminal 8 as
DIFFERENTIAL DC VOLTAGE
shown in Figure 9. This connection assures that the maxi- (ACROSS TERMS 2 AND 3) = 2V
5
OUTPUT STAGE TOGGLED
mum output signal swing will not go more positive than the
zener voltage minus two base-to-emitter voltage drops within
4
the CA3140. These voltages are independent of the operat-
ing supply voltage. 3
2
V+
DIFFERENTIAL DC VOLTAGE
5V TO 36V
(ACROSS TERMS 2 AND 3) = 0V
LOGIC 1
7
OUTPUT VOLTAGE = V+ / 2
SUPPLY
8
6.2V
2
5V
0
0 500 1000 1500 2000 2500 3000 3500 4000 4500
H"5V
CA3140 6
TYPICAL
TIME (HOURS)
TTL GATE
3
4
FIGURE 11. TYPICAL INCREMENTAL OFFSET VOLTAGE SHIFT
vs OPERATING LIFE
Offset Voltage Nulling
FIGURE 9. ZENER CLAMPING DIODE CONNECTED TO TERMI- The input offset voltage can be nulled by connecting a 10k&!
NALS 8 AND 4 TO LIMIT CA3140 OUTPUT SWING
potentiometer between terminals 1 and 5 and returning its
TO TTL LEVELS
wiper arm to terminal 4, see Figure 12(A). This technique,
however, gives more adjustment range than required and
therefore, a considerable portion of the potentiometer rota-
10008
SUPPLY VOLTAGE (V-) = 0V
tion is not fully utilized. Typical values of series resistors that
6
TA = +25oC
may be placed at either end of the potentiometer, see Figure
4
12(B), to optimize its utilization range are given in the table
2
 Electrical Specifications shown in this bulletin.
1008 SUPPLY VOLTAGE (V+) = +5V +15V
An alternate system is shown in Figure 12(C). This circuit
6
+30V
uses only one additional resistor of approximately the value
4
shown in the table. For potentiometers, in which the resis-
2
tance does not drop to zero &! at either end of rotation, a
108 value of resistance 10% lower than the values shown in the
6
table should be used.
4
Low Voltage Operation
2
Operation at total supply voltages as low as 4V is possible
1
2 4 6 8 2 4 6 8 2 4 6 8
with the CA3140. A current regulator based upon the PMOS
0.01 0.1 1.0 10
threshold voltage maintains reasonable constant operating
LOAD (SINKING) CURRENT (mA)
current and hence consistent performance down to these
lower voltages.
FIGURE 10. VOLTAGE ACROSS OUTPUT TRANSISTORS Q15
AND Q16 vs LOAD CURRENT
The low voltage limitation occurs when the upper extreme of
the input common mode voltage range extends down to the
2-131
OFFSET-VOLTAGE SHIFT (mV)
SATURATION VOLTAGE (mV)
OUTPUT STAGE TRANSISTOR (Q15, Q16)
CA3140, CA3140A
V+ V+ V+
2 7 2 7 2 7
CA3140 6 CA3140 6 CA3140 6
3 4 3 4 3 4
5 5 5
1 1 1
10k&! 10k&!
10k&!
V- V-
V-
(A) BASIC (B) IMPROVED (C) SIMPLER
RESOLUTION IMPROVED
RESOLUTION
FIGURE 12. THREE OFFSET VOLTAGE NULLING METHODS
V+ +HV
RS
7
LOAD
2
LOAD
30V
NO LOAD
CA3140 6
MT2
7
120VAC RL
2
3
4
CA3140 6
MT1
RL
3
4
FIGURE 13. METHODS OF UTILIZING THE VCE(SAT) SINKING CURRENT CAPABILITY OF THE CA3140 SERIES
FOLLOWER
+15V
7
0.1µF
3
SIMULATED
LOAD RESISTANCE (RL) = 2k&!
10k&! LOAD
LOAD CAPACITANCE (CL) = 100pF
CA3140 6
SUPPLY VOLTAGE: V+ = +15V, V- = -15V
100pF 2k&!
2
TA = +25oC
4
0.1µF
10
1mV 1mV
-15V
8
10mV 10mV
6
2k&!
4
0.05µF
2
FOLLOWER
0
INVERTING
INVERTING
-2 5k&!
-4
+15V
-6
1mV 1mV
7
-8
10mV 10mV
0.1µF
2
SIMULATED
-10 5k&!
LOAD
2 4 6 8 2 4 6 8
0.1 1.0 10
CA3140 6
200&!
SETTLING TIME (µs)
100pF 2k&!
3
4
(A)
0.1µF
5.11k&!
4.99k&!
-15V
SETTLING POINT
D1 D2
IN914 IN914
(B) TEST CIRCUITS
FIGURE 14. INPUT VOLTAGE vs SETTLING TIME
2-132
INPUT VOLTAGE (V)
CA3140, CA3140A
voltage at terminal 4. This limit is reached at a total supply amplifiers. The exceptionally fast settling time characteristics
voltage just below 4V. The output voltage range also begins are largely due to the high combination of high gain and wide
to extend down to the negative supply rail, but is slightly bandwidth of the CA3140; as shown in Figure 15.
higher than that of the input. Figure 17 shows these
Input Circuit Considerations
characteristics and shows that with 2V dual supplies, the
lower extreme of the input common mode voltage range is
As mentioned previously, the amplifier inputs can be driven
below ground potential.
below the terminal 4 potential, but a series current limiting
resistor is recommended to limit the maximum input terminal
Bandwidth and Slew Rate
current to less than 1mA to prevent damage to the input pro-
For those cases where bandwidth reduction is desired, for tection circuitry.
example, broadband noise reduction, an external capacitor
Moreover, some current limiting resistance should be
connected between terminals 1 and 8 can reduce the open
provided between the inverting input and the output when
loop -3dB bandwidth. The slew rate will, however, also be
the CA3140 is used as a unity gain voltage follower. This
proportionally reduced by using this additional capacitor.
resistance prevents the possibility of extremely large input
Thus, a 20% reduction in bandwidth by this technique will
signal transients from forcing a signal through the input
also reduce the slew rate by about 20%.
protection network and directly driving the internal constant
Figure 14 shows the typical settling time required to reach current source which could result in positive feedback via the
1mV or 10mV of the final value for various levels of large output terminal. A 3.9k&! resistor is sufficient.
signal inputs for the voltage follower and inverting unity gain
10K
8
SUPPLY VOLTAGE: V+ = 15V, V- = -15V
-75 6
SUPPLY VOLTAGE: V+ = 15V, V- = -15V
4
-90
TA = +25oC
RL = 2k&!, 2
-105
100
CL = 0pF
ĆOL
1K
8
-120
6
-135 4
80
2
-150
100
60
8
6
4
RL = 2k&!,
CL = 100pF
40 2
10
8
6
20
4
2
0
1
101 102 103 104 105 106 107 108
-60 -40 -20 0 20 40 60 80 100 120 140
FREQUENCY (Hz)
AMBIENT TEMPERATURE (oC)
FIGURE 15. OPEN LOOP VOLTAGE GAIN AND PHASE vs FIGURE 16. INPUT CURRENT vs AMBIENT TEMPERATURE
FREQUENCY
RL = "
0
1.5
+VICR AT TA = +125oC
-VICR AT TA = +125oC
-0.5
1.0
+VOUT AT TA = +125oC
+VICR AT TA = +25oC
-VICR AT TA = +25oC
+VOUT AT TA = +25oC
-1.0
0.5
+VICR AT TA = -55oC -VOUT FOR TA = -VICR AT TA = -55oC
+VOUT AT TA = -55oC
-55oC to +125oC
-1.5
0
-2.0
-0.5
-2.5
-1.0
-3.0
-1.5
0 5 10 15 20 25 0 5 10 15 20 25
SUPPLY VOLTAGE (V+, V-) SUPPLY VOLTAGE (V+, V-)
FIGURE 17. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE AND
TEMPERATURE
2-133
(DEGREES)
OPEN LOOP PHASE
INPUT CURRENT (pA)
OPEN LOOP VOLTAGE GAIN (dB)
FROM TERMINAL 4 (V-)
FROM TERMINAL 7 (V+)
INPUT AND OUTPUT VOLTAGE EXCURSIONS
INPUT AND OUTPUT VOLTAGE EXCURSIONS
CA3140, CA3140A
The typical input current is in the order of 10pA when the the Frequency Adjustment Control. This low-driving
inputs are centered at nominal device dissipation. As the impedance requirement is easily met by using a CA3140
output supplies load current, device dissipation will increase, connected as a voltage follower. Moreover, a meter may be
raising the chip temperature and resulting in increased input placed across the input to the CA3080A to give a logarithmic
current. Figure 16 shows typical input terminal current ver- analog indication of the function generators frequency.
sus ambient temperature for the CA3140.
Analog frequency readout is readily accomplished by the
It is well known that MOSFET devices can exhibit slight
means described above because the output current of the
changes in characteristics (for example, small changes in
CA3080A varies approximately one decade for each 60mV
input offset voltage) due to the application of large differen- change in the applied voltage, VABC (voltage between
tial input voltages that are sustained over long periods at ele- terminals 5 and 4 of the CA3080A of the function generator).
vated temperatures.
Therefore, six decades represent 360mV change in VABC.
Both applied voltage and temperature accelerate these
Now, only the reference voltage must be established to set
changes. The process is reversible and offset voltage shifts
the lower limit on the meter. The three remaining transistors
of the opposite polarity reverse the offset. Figure 11 shows
from the CA3086 Array used in the sweep generator are
the typical offset voltage change as a function of various
used for this reference voltage. In addition, this reference
stress voltages at the maximum rating of +125oC (for TO-5);
generator arrangement tends to track ambient temperature
at lower temperatures (TO-5 and plastic), for example, at
variations, and thus compensates for the effects of the nor-
+85oC, this change in voltage is considerably less. In typical
mal negative temperature coefficient of the CA3080A VABC
linear applications, where the differential voltage is small and
terminal voltage.
symmetrical, these incremental changes are of about the
same magnitude as those encountered in an operational Another output voltage from the reference generator is used
amplifier employing a bipolar transistor input stage. to insure temperature tracking of the lower end of the
Frequency Adjustment Potentiometer. A large series
Super Sweep Function Generator
resistance simulates a current source, assuring similar
temperature coefficients at both ends of the Frequency
A function generator having a wide tuning range is shown in
Adjustment Control.
Figure 18. The 1,000,000/1 adjustment range is accom-
plished by a single variable potentiometer or by an auxiliary
To calibrate this circuit, set the Frequency Adjustment
sweeping signal. The CA3140 functions as a non-inverting
Potentiometer at its low end. Then adjust the Minimum
readout amplifier of the triangular signal developed across
Frequency Calibration Control for the lowest frequency. To
the integrating capacitor network connected to the output of
establish the upper frequency limit, set the Frequency
the CA3080A current source.
Adjustment Potentiometer to its upper end and then adjust
the Maximum Frequency Calibration Control for the
Buffered triangular output signals are then applied to a sec-
maximum frequency. Because there is interaction among
ond CA3080 functioning as a high speed hysteresis switch.
these controls, repetition of the adjustment procedure may
Output from the switch is returned directly back to the input
be necessary. Two adjustments are used for the meter. The
of the CA3080A current source, thereby, completing the pos-
meter sensitivity control sets the meter scale width of each
itive feedback loop
decade, while the meter position control adjusts the pointer
on the scale with negligible effect on the sensitivity
The triangular output level is determined by the four 1N914
adjustment. Thus, the meter sensitivity adjustment control
level limiting diodes of the second CA3080 and the resistor
1
calibrates the meter so that it deflects /6 of full scale for
divider network connected to terminal No. 2 (input) of the
each decade change in frequency.
CA3080. These diodes establish the input trip level to this
switching stage and, therefore, indirectly determine the
Sine Wave Shaper
amplitude of the output triangle.
The circuit shown in Figure 20 uses a CA3140 as a voltage
Compensation for propagation delays around the entire loop
follower in combination with diodes from the CA3019 Array
is provided by one adjustment on the input of the CA3080.
to convert the triangular signal from the function generator to
This adjustment, which provides for a constant generator
a sine-wave output signal having typically less than 2% THD.
amplitude output, is most easily made while the generator is
The basic zero crossing slope is established by the 10k&!
sweeping. High frequency ramp linearity is adjusted by the
potentiometer connected between terminals 2 and 6 of the
single 7-to-6pF capacitor in the output of the CA3080A.
CA3140 and the 9.1k&! resistor and 10k&! potentiometer
It must be emphasized that only the CA3080A is
from terminal 2 to ground. Two break points are established
characterized for maximum output linearity in the current
by diodes D1 through D4. Positive feedback via D5 and D6
generator function.
establishes the zero slope at the maximum and minimum
levels of the sine wave. This technique is necessary because
Meter Driver and Buffer Amplifier
the voltage follower configuration approaches unity gain
rather than the zero gain required to shape the sine wave at
Figure 19 shows the CA3140 connected as a meter driver
the two extremes.
and buffer amplifier. Low driving impedance is required of
the CA3080A current source to assure smooth operation of
2-134
CA3140, CA3140A
CENTERING
+15V
10k&!
-15V
HIGH
7.5k&!
+15V +15V
FREQUENCY
910
62k&! 10k&!
LEVEL
0.1
360&!
k&!
7-60pF
7
µF
3
+ 7
15k&!
5
EXTERNAL
6 +
CA3080A 3
7
360&!
OUTPUT
51
-
2 - 7-60
CA3140 2
6
pF
4
6
11k&! CA3080
2 -
pF
5
+
11k&!
10k&! 3
2M&! 4
HIGH
2.7k&!
4
SYMMETRY -15V 0.1
FREQ.
EXTERNAL
-15V
+15V
SHAPE µF
-15V -15V
OUTPUT
13k&! TO OUTPUT
2k&!
100k&!
AMPLIFIER
FROM BUFFER METER
FREQUENCY
5.1
TO
DRIVER (OPTIONAL)
ADJUSTMENT k&!
120&! 10k&!
39&! SINE WAVE
SHAPER
IN914
-15V +15V OUTPUT
AMPLIFIER
THIS NETWORK IS USED WHEN THE
OPTIONAL BUFFER CIRCUIT IS NOT USED
(A) CIRCUIT
FREQUENCY
ADJUSTMENT
+15V
(B1) FUNCTION GENERATOR SWEEPING METER DRIVER
POWER
AND BUFFER
SUPPLY Ä…15V
Top Trace: Output at junction of 2.7&! and 51&! resistors
AMPLIFIER M
-15V
5V/Div and 500ms/Div
Center Trace: External output of triangular function generator
FUNCTION
2V/Div and 500ms/Div GENERATOR
Bottom Trace: Output of  Log generator; 10V/Div and 500ms/Div
WIDEBAND
LINE DRIVER
SINE WAVE
SHAPER
51&!
GATE DC LEVEL
FINE SWEEP
ADJUST
SWEEP
RATE GENERATOR
OFF INT.
EXTERNAL
INPUT
COARSE
V- EXT.
RATE
SWEEP
LENGTH
V-
(B2) FUNCTION GENERATOR WITH FIXED FREQUENCIES
(C) INTERCONNECTIONS
1V/Div and 1sec/Div
Three tone test signals, highest frequency e"0.5MHz. Note the slight
asymmetry at the three second/cycle signal. This asymmetry is due
to slightly different positive and negative integration from the
CA3080A and from the pc board and component leakages at the
100pA level.
FIGURE 18. FUNCTION GENERATOR
2-135
CA3140, CA3140A
FREQUENCY
500k&!
CALIBRATION
MAXIMUM
620k&!
FREQUENCY
7
51k&!
+15V -15V
ADJUSTMENT
TO CA3080A
3
+
10k&!
OF FUNCTION
CA3080A
0.1µF
CA3140 6 GENERATOR
5.6
SWEEP IN
7 7.5
(FIGURE 18)
k&!
3M&! - +
3
2
4 k&!
4.7k&!
5.1k&!
CA3140 6
4 5
TO
2 -
SUBSTRATE
+15V WIDEBAND
4
2k&! METER
620&!
0.1µF OF CA3019 OUTPUT
SENSITIVITY
12 AMPLIFIER
0.1µF
ADJUSTMENT 7
1k&!
k&!
FREQUENCY 2.4k&! 10k&!
-15V
200µA
CALIBRATION +15V
R3 10k&!
M
METER
MINIMUM
EXTERNAL
2.5 1M&!
100
OUTPUT
k&! 11
k&!
D1 D4
9.1k&!
9
510&! -15V
6 5 8 2
510&!
R1
8 10 14
10k&!
2k&! 430&!
D6
D3 D2
6 12
9 1
R2
METER
3.6k&! 1k&!
7 POSITION
13
3 4
ADJUSTMENT
D5
3
/5 OF CA3086 CA3019
DIODE ARRAY
-15V
FIGURE 19. METER DRIVER AND BUFFER AMPLIFIER FIGURE 20. SINE WAVE SHAPER
750k&!
 LOG
100k&!
18M&!
IN914 SAWTOOTH
FINE
100k&!
1M&!
RATE
22M&!
IN914
SAWTOOTH 8.2k&!
SAWTOOTH AND
SYMMETRY
+15V
0.47µF
RAMP LOW LEVEL
SET (-14.5V)
0.047µF
COARSE
50k&!
RATE
4700pF
75k&!
470pF
51k&!
SAWTOOTH
+15V
0.1
 LOG +15V
µF
+15V
7
2 -
36k&!
TRIANGLE
7
CA3140 6 3 -
10k&! GATE
CA3140 6
PULSE
+
100k&!
3
4
OUTPUT
30k&!
+
0.1 TO OUTPUT 2
4
AMPLIFIER
µF 50k&!
-15V
LOG
-15V
10k&!
RATE
EXTERNAL OUTPUT
ADJUST
43k&!
10k&! TO FUNCTION GENERATOR  SWEEP IN
SWEEP WIDTH
-15V
+15V
7
+
3
CA3140 6
- 51k&! 6.8k&! 91k&!
10k&!
2 4
LOGVIO 1 5
TRIANGLE
25k&!
5 1
SAWTOOTH
3.9&!
TRANSISTORS
FROM CA3086
4 2
-15V
ARRAY
 LOG
100&!
390&! 3
FIGURE 21. SWEEPING GENERATOR
2-136
CA3140, CA3140A
This circuit can be adjusted most easily with a distortion
analyzer, but a good first approximation can be made by
comparing the output signal with that of a sine wave
VOLTAGE
ADJUSTMENT
REFERENCE
generator. The initial slope is adjusted with the
VOLTAGE
7
potentiometer R1, followed by an adjustment of R2. The final 3
+
REGULATED
slope is established by adjusting R3, thereby adding
INPUT CA3140 6
OUTPUT
additional segments that are contributed by these diodes. -
2
4
Because there is some interaction among these controls,
repetition of the adjustment procedure may be necessary.
Sweeping Generator
FIGURE 23. BASIC SINGLE SUPPLY VOLTAGE REGULATOR
Figure 21 shows a sweeping generator. Three CA3140's are
SHOWING VOLTAGE FOLLOWER CONFIGURATION
used in this circuit. One CA3140 is used as an integrator, a
second device is used as a hysteresis switch that deter-
Essentially, the regulators, shown in Figures 24 and 25, are
mines the starting and stopping points of the sweep. A third
connected as non inverting power operational amplifiers with
CA3140 is used as a logarithmic shaping network for the log
a gain of 3.2. An 8V reference input yields a maximum out-
function. Rates and slopes, as well as sawtooth, triangle,
put voltage slightly greater than 25V. As a voltage follower,
and logarithmic sweeps are generated by this circuit.
when the reference input goes to 0V the output will be 0V.
Because the offset voltage is also multiplied by the 3.2 gain
Wideband Output Amplifier
factor, a potentiometer is needed to null the offset voltage.
Figure 22 shows a high slew rate, wideband amplifier
Series pass transistors with high ICBO levels will also prevent
suitable for use as a 50&! transmission line driver. This
the output voltage from reaching zero because there is a
circuit, when used in conjunction with the function generator
finite voltage drop (VCEsat) across the output of the CA3140
and sine wave shaper circuits shown in Figures 18 and 20
(see Figure 10). This saturation voltage level may indeed set
provides 18V peak-to-peak output open circuited, or 9V
the lowest voltage obtainable.
peak-to-peak output when terminated in 50&!. The slew rate
required of this amplifier is 28V/µs (18V peak-to-peak x Ä„ x The high impedance presented by terminal 8 is advanta-
0.5MHz). geous in effecting current limiting. Thus, only a small signal
transistor is required for the current-limit sensing amplifier.
Resistive decoupling is provided for this transistor to mini-
+15V
mize damage to it or the CA3140 in the event of unusual
+ 2.2
50µF
input or output transients on the supply rail.
SIGNAL
2N3053
- 25V k&!
LEVEL
ADJUSTMENT
Figures 24 and 25, show circuits in which a D2201 high
7 speed diode is used for the current sensor. This diode was
2.5k&! + OUT
3 IN914 2.7&!
51&!
chosen for its slightly higher forward voltage drop character-
CA3140 6
200&! 2W
IN914 2.7&!
istic, thus giving greater sensitivity. It must be emphasized
- 4
2
8
that heat sinking of this diode is essential to minimize varia-
1
- 50µF
25V
tion of the current trip point due to internal heating of the
+ 2.2
2N4037
OUTPUT
k&!
2.4pF
DC LEVEL diode. That is, 1A at 1V forward drop represents one watt
+15V
ADJUSTMENT 2pF
3k&!
-15V which can result in significant regenerative changes in the
current trip point as the diode temperature rises. Placing the
-15V
small signal reference amplifier in the proximity of the current
1.8k&! NOMINAL BANDWIDTH = 10MHz
200&!
tr = 35ns
sensing diode also helps minimize the variability in the trip
level due to the negative temperature coefficient of the
diode. In spite of those limitations, the current limiting point
FIGURE 22. WIDEBAND OUTPUT AMPLIFIER
can easily be adjusted over the range from 10mA to 1A with
a single adjustment potentiometer. If the temperature stabil-
Power Supplies
ity of the current limiting system is a serious consideration,
the more usual current sampling resistor type of circuitry
High input impedance, common mode capability down to the
should be employed.
negative supply and high output drive current capability are
key factors in the design of wide range output voltage
A power Darlington transistor (in a heat sink TO-3 case), is used
supplies that use a single input voltage to provide a
as the series pass element for the conventional current limiting
regulated output voltage that can be adjusted from
system, Figure 24, because high power Darlington dissipation
essentially 0V to 24V.
will be encountered at low output voltage and high currents.
Unlike many regulator systems using comparators having a A small heat sink VERSAWATT transistor is used as the
bipolar transistor input stage, a high impedance reference series pass element in the fold back current system, Figure
voltage divider from a single supply can be used in 25, since dissipation levels will only approach 10W. In this
connection with the CA3140 (see Figure 23). system, the D2201 diode is used for current sampling. Fold-
2-137
CA3140, CA3140A
back is provided by the 3k&! and 100k&! divider network con- Both regulators, Figures 24 and 25, provide better than 0.02%
nected to the base of the current sensing transistor. load regulation. Because there is constant loop gain at all volt-
age settings, the regulation also remains constant. Line regu-
2N6385 CURRENT
lation is 0.1% per volt. Hum and noise voltage is less than
POWER DARLINGTON LIMITING
OUTPUT
ADJUST
200µV as read with a meter having a 10MHz bandwidth.
0.1 Ò! 24V
D2201
AT 1A
+30V 3 2
Figure 28 (a) shows the turn ON and turn OFF characteris-
75&! tics of both regulators. The slow turn on rise is due to the
1k&! 1k&!
1
slow rate of rise of the reference voltage. Figure 26 (B)
1k&!
2
3k&!
shows the transient response of the regulator with the
2N2102
switching of a 20&! load at 20V output.
3
100&!
1k&!
1 8
56pF 180k&!
7
2
1k&!
6 CA3140
82k&!
+
5
3
2.7k&! 10µF
- 1
100k&!
4
INPUT
VOLTAGE
+
+ ADJUST
2.2k&! 250µF
5µF
50k&!
- -
100k&!
1
10 11 2 14
12
3
9
0.01µF
5
8 7 13
6 4
CA3086
1k&!
(A) SUPPLY TURN-ON AND TURNOFF CHARACTERISTICS
62k&!
5V/Div and -1s/Div
HUM AND NOISE OUTPUT <200µVRMS LOAD REGULATION
(MEASUREMENT BANDWIDTH ~10MHz) (NO LOAD TO FULL LOAD)
LINE REGULATION 0.1%/VOLT <0.02%
FIGURE 24. REGULATED POWER SUPPLY
OUTPUT Ò! 0V TO 25V
 FOLDBACK CURRENT
25V AT 1A
LIMITER
 FOLDS BACK
2N5294
D2201
TO 40mA
+30V 2 3
1k&! 200&!
1
100k&! 3k&!
100k&!
2N2102
1k&!
8
56pF 180k&!
7
2
1k&!
6 CA3140
82k&!
+
5 (B) TRANSIENT RESPONSE
3
2.7k&! 10µF
- 1
100k&!
4
Top Trace: Output voltage
INPUT
200mV/Div and 5µs/Div
VOLTAGE
+
+ ADJUST
250µF
2.2k&!
5µF
50k&!
Bottom Trace: Collector of load switching transistor, load = 1A
- -
100k&!
5V/Div and 5µs/Div
1
10 11 2 14
FIGURE 26. WAVEFORMS OF DYNAMIC CHARACTERISTICS
12
3
9
OF POWER SUPPLY CURRENTS SHOWN IN FIG-
0.01µF
5
URES 24 AND 25
8 7 13
6 4
CA3086
Tone Control Circuits
1k&!
High slew rate, wide bandwidth, high output voltage capabil-
62k&!
ity and high input impedance are all characteristics required
HUM AND NOISE OUTPUT <200µVRMS LOAD REGULATION
of tone control amplifiers. Two tone control circuits that
(MEASUREMENT BANDWIDTH ~10MHz) (NO LOAD TO FULL LOAD)
LINE REGULATION 0.1%/VOLT <0.02%
exploit these characteristics of the CA3140 are shown in Fig-
ures 27 and 28.
FIGURE 25. REGULATED POWER SUPPLY WITH  FOLDBACK
CURRENT LIMITING
2-138
CA3140, CA3140A
The first circuit, shown in Figure 28, is the Baxandall tone Figure 27 shows another tone control circuit with similar
control circuit which provides unity gain at midband and uses boost and cut specifications. The wideband gain of this cir-
standard linear potentiometers. The high input impedance of cuit is equal to the ultimate boost or cut plus one, which in
the CA3140 makes possible the use of low-cost, low-value, this case is a gain of eleven. For 20dB boost and cut, the
small size capacitors, as well as reduced load of the driving input loading of this circuit is essentially equal to the value of
stage. the resistance from terminal No. 3 to ground. A detailed
analysis of this circuit is given in  An IC Operational
Bass treble boost and cut are Ä…15dB at 100Hz and 10kHz,
TransconductanceAmplifier (OTA) With Power Capability by
respectively. Full peak-to-peak output is available up to at
L. Kaplan and H. Wittlinger, IEEE Transactions on Broadcast
least 20kHz due to the high slew rate of the CA3140. The
and Television Receivers, Vol. BTR-18, No. 3, August, 1972.
amplifier gain is 3dB down from its  flat position at 70kHz.
FOR SINGLE SUPPLY
20dB Flat Position Gain
+30V
2.2M&! Ä…15dB Bass and Treble Boost and Cut at
100Hz and 10kHz, respectively
7
25VP-P output at 20kHz
0.005µF
0.1µF
3 +
-3dB at 24kHz from 1kHz reference
6
5.1 CA3140
M&!
2 -
4
FOR DUAL SUPPLIES
BOOST TREBLE CUT
200k&!
+15V
0.012µF 0.001µF
(LINEAR)
7
0.1 100
0.005µF
0.1µF
100pF
2.2M&! 18k&!
pF
µF 3 +
CA3140 6
5.1M&!
-
2
4
0.1µF
0.022µF 0.0022µF
-15V
2µF
- +
10k&! 1M&! 100k&!
TONE CONTROL NETWORK
CCW (LOG)
BOOST BASS CUT
TONE CONTROL NETWORK
FIGURE 27. TONE CONTROL CIRCUIT USING CA3130 SERIES (20dB MIDBAND GAIN)
FOR SINGLE SUPPLY
BOOST BASS CUT
(LINEAR)
0.047µF
240k&! 5M&! 240k&!
FOR DUAL SUPPLIES
2.2M&! +32V
750 750
+15V
pF pF
0.1
7
µF 7
0.1µF
3 +
3 +
0.1 22 CA3140
6
CA3140 6
0.047µF
µF M&!
2 -
TONE CONTROL
2.2M&! -
2
NETWORK
4
4
0.1µF
20pF
-15V
Ä…15dB Bass and Treble Boost and Cut at
51k&! 5M&! 51k&!
(LINEAR) 100Hz and 10kHz, respectively
BOOST TREBLE CUT 25VP-P output at 20kHz
TONE CONTROL NETWORK
-3dB at 70kHz from 1kHz reference
0dB Flat Position Gain
FIGURE 28. BAXANDALL TONE CONTROL CIRCUIT USING CA3140 SERIES
2-139
CA3140, CA3140A
Wien Bridge Oscillator OUTPUT
19VP-P TO 22VP-P
+15V
THD <0.3%
Another application of the CA3140 that makes excellent use
R2
of its high input impedance, high slew rate, and high voltage
C2 1000pF 7
0.1µF
qualities is the Wien Bridge sine wave oscillator. A basic Wien
CA3109
3 +
8 9
DIODE
Bridge oscillator is shown in Figure 29. When R1 = R2 = R and
CA3140 6
ARRAY
C1 = C2 = C, the frequency equation reduces to the familiar
R1 C1 - SUBSTRATE
2
1
OF CA3019 1
1000
f = /2 Ä„ RC and the gain required for oscillation, AOSC is
4
6 2
pF
0.1µF
equal to 3. Note that if C2 is increased by a factor of four and
3
7
R2 is reduced by a factor of four, the gain required for
0.1µF
-15V
oscillation becomes 1.5, thus permitting a potentially higher
7.5k&!
5 4
operating frequency closer to the gain bandwidth product of
R1 = R2 = R
the CA3140.
50Hz, R = 3.3M&!
3.6k&!
100Hz, R = 1.6M&!
C2 R2
1kHz, R = 160M&!
NOTES:
1
500&!
f = ---------------------------- 10kHz, R = 16M&!
30kHz, R = 5.1M&!
2Ä„ R1C1R2C2
+
OUTPUT
FIGURE 30. WIEN BRIDGE OSCILLATOR CIRCUIT USING
C1 R2
- AOS = 1 + ------ + ------
- -
CA3140 SERIES
C2 R1
Rf
Simple Sample-and-Hold System
Rf
C1
R1
Figure 31 shows a very simple sample-and-hold system
RS ACL = 1 + -------
RS using the CA3140 as the readout amplifier for the storage
capacitor. The CA3080A serves as both input buffer ampli-
fier and low feed-through transmission switch.* System off-
set nulling is accomplished with the CA3140 via its offset
FIGURE 29. BASIC WIEN BRIDGE OSCILLATOR CIRCUIT US-
nulling terminals. A typical simulated load of 2k&! and 30pF
ING AN OPERATIONAL AMPLIFIER
is shown in the schematic.
Oscillator stabilization takes on many forms. It must be
0 SAMPLE
30k&!
precisely set, otherwise the amplitude will either diminish or
STROBE
reach some form of limiting with high levels of distortion. The -15 HOLD
IN914
element, RS, is commonly replaced with some variable
resistance element. Thus, through some control means, the
+15V
value of RS is adjusted to maintain constant oscillator output.
IN914 +15V
5
A FET channel resistance, a thermistor, a lamp bulb, or other
0.1µF
3.5k&!
2k&!
7
+ 7
device whose resistance is made to increase as the output INPUT 3
+
CA3080A 6 3
amplitude is increased are a few of the elements often
CA3140 6
2 -
utilized.
4
2 -
0.1
4
1 µF
0.1µF
Figure 30 shows another means of stabilizing the oscillator
5
with a zener diode shunting the feedback resistor (Rf of 2k&! 100k&!
-15V
2k&!
Figure 29). As the output signal amplitude increases, the
-15V
200pF
zener diode impedance decreases resulting in more
200pF
feedback with consequent reduction in gain; thus stabilizing
2k&!
400&!
the amplitude of the output signal. Furthermore, this
0.1µF
combination of a monolithic zener diode and bridge rectifier
30pF
SIMULATED LOAD
circuit tends to provide a zero temperature coefficient for this
NOT REQUIRED
regulating system. Because this bridge rectifier system has
no time constant, i.e., thermal time constant for the lamp
FIGURE 31. SAMPLE AND HOLD CIRCUIT
bulb, and RC time constant for filters often used in detector
In this circuit, the storage compensation capacitance (C1) is
networks, there is no lower frequency limit. For example,
only 200pF. Larger value capacitors provide longer  hold
with 1µF polycarbonate capacitors and 22M&! for the
periods but with slower slew rates. The slew rate
frequency determining network, the operating frequency is
0.007Hz.
dv i-
------ = -- = 0.5mA D 200pF = 2.5V D µs
dt c
As the frequency is increased, the output amplitude must be
reduced to prevent the output signal from becoming slew- * ICAN-6668  Applications of the CA3080 and CA 3080A High Per-
formance Operational Transconductance Amplifiers .
rate limited. An output frequency of 180kHz will reach a slew
rate of approximately 9V/µs when its amplitude is 16V peak- Pulse  droop during the hold interval is 170pA/200pF which
to-peak.
is = 0.85µV/µs; (i.e., 170pA/200pF). In this case, 170pA
2-140
CA3140, CA3140A
represents the typical leakage current of the CA3080A when Current Amplifier
strobed off. If C1 were increased to 2000 pF, the  hold-droop
The low input terminal current needed to drive the CA3140
rate will decrease to 0.085µV/µs, but the slew rate would
makes it ideal for use in current amplifier applications such
decrease to 0.25V/µs. The parallel diode network connected
as the one shown in Figure 33.* In this circuit, low current is
between terminal 3 of the CA3080A and terminal 6 of the
supplied at the input potential as the power supply to load
CA3140 prevents large input signal feedthrough across the
resistor RL. This load current is increased by the multiplica-
input terminals of the CA3080A to the 200pF storage capacitor
tion factor R2/R1, when the load current is monitored by the
when the CA3080A is strobed off. Figure 32 shows dynamic
power supply meter M. Thus, if the load current is 100nA,
characteristic waveforms of this sample-and-hold system.
with values shown, the load current presented to the supply
will be 100µA; a much easier current to measure in many
systems.
R1
10k&!
+15V
R2
IL
0.1µF
R1
7
3 +
R2
CA3140 6
M
IL
10M&!
0.1µF
2 -
4
POWER 1
Top Trace: Output; 50mV/Div and 200ns/Div
5
SUPPLY RL
Bottom Trace: Input; 50mV/Div and 200ns/Div
100k&!
4.3k&!
-15V
FIGURE 33. BASIC CURRENT AMPLIFIER FOR LOW CURRENT
MEASUREMENT SYSTEMS
Note that the input and output voltages are transferred at the
same potential and only the output current is multiplied by
the scale factor.
The dotted components show a method of decoupling the
LARGE SIGNAL RESPONSE AND SETTLING TIME
circuit from the effects of high output load capacitance and
Top Trace: Output Signal; 5V/Div and 2µs/Div
the potential oscillation in this situation. Essentially, the
Center Trace: Difference of Input and Output Signals through
necessary high frequency feedback is provided by the
Tektronix Amplifier 7A13; 5mV/Div and 2µs/Div
capacitor with the dotted series resistor providing load
Bottom Trace: Input Signal; 5V/Div and 2µs/Div
decoupling.
Figure 34 shows a single supply, absolute value, ideal full-
wave rectifier with associated waveforms. During positive
excursions, the input signal is fed through the feedback
network directly to the output. Simultaneously, the positive
excursion of the input signal also drives the output terminal
(No. 6) of the inverting amplifier in a negative going
excursion such that the 1N914 diode effectively disconnects
the amplifier from the signal path. During a negative going
excursion of the input signal, the CA3140 functions as a
normal inverting amplifier with a gain equal to -R2/R1. When
the equality of the two equations shown in Figure 34 is
satisfied, the full wave output is symmetrical.
SAMPLING RESPONSE
*  Operational Amplifiers Design and Applications , J. G. Graeme,
Top Trace: Output; 100mV/Div and 500ns/Div
McGraw-Hill Book Company, page 308 -  Negative Immittance
Converter Circuits .
Bottom Trace: Input; 20V/Div and 500ns/Div
FIGURE 32. SAMPLE AND HOLD SYSTEM DYNAMIC CHARAC-
TERISTICS WAVEFORMS
2-141
CA3140, CA3140A
+15V
R2
5k&!
+15V
0.1µF
7
100k&!
SIMULATED
R1 0.1µF
3 LOAD
+
7
2
-
CA3140 6
10k&!
CA3140 6
2 -
1N914
100pF 2k&!
3 +
4 4
5
10k&!
1
8
R3
0.1µF
PEAK
ADJUST
-15V
100k&!
10k&!
BW (-3dB) = 4.5MHz
OFFSET
SR = 9V/µs
ADJUST
2k&!
R2 R3
GAIN = ------ = X = ---------------------------------
- -
R1 R1 + R2 + R3 0.05µF
2
ëÅ‚ öÅ‚
X + X
ìÅ‚
R3 = ----------------÷Å‚ R1
íÅ‚ 1  X Å‚Å‚
5k&! R2
- -
FORX = 0.5 ------------ = ------
10k&! R1
0.75
ëÅ‚
-Å‚Å‚
R3 = 10k&! ---------öÅ‚ = 15k&!
íÅ‚
0.5
20Vp-p Input BW(-3dB) = 290kHz, DCOutput (Avg) = 3.2V
(A) SMALL SIGNAL RESPONSE
OUTPUT
50mV/Div and 200ns/Div
0
Top Trace: Output; 50mV/Div and 200ns/Div
INPUT
Bottom Trace: Input; 50mV/Div and 200ns/Div
0
FIGURE 34. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL
WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS
+15V
0.01µF
RS 7
3
+
NOISE VOLTAGE
1M&!
CA3140 6
OUTPUT
2 -
4 (B) INPUT-OUTPUT DIFFERENCE SIGNAL
30.1k&! SHOWING SETTLING TIME
0.01µF
(measurement made with Tektronix 7A13 differential amplifier)
-15V
Top Trace: Output Signal; 5V/Div and 5µs/Div
BW (-3dB) = 140kHz
1k&!
Center Trace: Difference Signal; 5mV/Div and 5µs/Div
TOTAL NOISE VOLTAGE
(REFERRED TO INPUT ) = 48µV TYP. Bottom Trace: Input Signal; 5V/Div and 5µs/Div
FIGURE 35. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR FIGURE 36. SPLIT SUPPLY VOLTAGE FOLLOWER TEST CIR-
WIDEBAND NOISE MEASUREMENT CUIT AND ASSOCIATED WAVEFORMS
2-142