CMOS 300 MHz Quadrature
a
a
Complete-DDS
PRELIMINARY TECHNICAL DATA
AD9854
Automatic Bi-directional Frequency Sweep
SIN (X)/X Correction
FEATURES
Simplified Control Interface:
300 MHz Internal Clock Rate
10 MHz Serial, 2 or 3-wire SPI compatible or
Dual12-bit Quadrature Output DACs
100 MHz Parallel 8-Bit Byte Programming
Ultra High-speed, 3ps RMS Jitter Comparator
+3.3 V Single Supply
Excellent Dynamic Performance:
Multiple Power-Down Functions
Ä…
80 dB SFDR @ 100 MHz (Ä… 1 MHz) Aout
Single-Ended or Differential Input Reference Clock
× ×
4× - 20× Programmable Reference Clock Multiplier
Small 80 -pin LQFP Packaging
Dual 48-bit Programmable Frequency Registers
Dual 14-bit Programmable Phase Offset Registers
APPLICATIONS
12-bit Amplitude Modulation and Programmable Shaped
Agile, Quadrature L.O. Frequency Synthesis
On-Off Keying Function
Programmable Clock Generator
Single pin FSK and PSK data interface
FM Chirp Source for Radar and Scanning Systems
Linear or Non-Linear FM Chirp Functions with Single
Test and Measurement Equipment
Pin Frequency  Hold Function
Commercial & Amateur RF exciter
Frequency-Ramped FSK
AD9854 Block Diagram
DAC R
SET
Digital Multiplier's
300 MHz DDS
Diff/Single Inverse
12-Bit "I"
Sinc
I Analog Out
Select
Filter
DAC
4X - 20X
Reference
Ref. Clock
Clock In
Multiplier
Inverse
12-Bit "Q"or
Phase Offset/ MUX
Sinc
Q
Modulation
Filter Analog Out
System Control DAC
Clock
Ramp-up/Down
Shaped on-off
FSK/BPSK/HOLD
Frequency Tuning Word/Phase Word Clock/Logic &
Data In
Multiplexer & Ramp Start Stop Logic Multiplexer Keying
AD9854
12-bit
14-bit Phase
48-bit Frequency AM
12-bit Control DAC Data
Offset/
Bi-directional Tuning Word MOD
Modulation
I/O Update
Analog In
PROGRAMMING REGISTERS
+
Read
Comparator
Programmable Rate
I/O Port Buffers
I/O PORT BUFFERS
and Update Clocks
Clock Out
Write -
Master
Serial/Parallel +Vs Gnd
6-bit Address 8-bit Parallel
Reset
Select
or Serial Load
Programming
lines
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog devices for its use, nor for any infringements of
patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
7/16/99 REV.PRA
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Converter
Phase
Frequency
Accumulator
Accumulator
Sine-to-Amplitude
AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
GENERAL DESCRIPTION
The AD9854 digital synthesizer is a highly integrated device that desired. When configured with the on-board comparator, the 12-
uses advanced DDS technology, coupled with (2) internal high- bit control DAC facilitates pulse-width modulation (PWM) and
speed, high performance quadrature D/A converters and static duty cycle control, in the high-speed clock generator
comparator to form a digitally-programmable I & Q synthesizer application. Two 12-bit digital multipliers permit programmable
function. When referenced to an accurate clock source, the amplitude modulation, shaped on-off keying and precise amp-
AD9854 generates a highly stable, frequency, phase and litude control of the quadrature outputs. The AD9854
s
amplitude programmable sine and cosine outputs that can be used programmable 4× - 20× REFCLK Multiplier circuit generates the
as an agile L.O. in communications, radar, and many other 300 MHz clock internally from a lower frequency external
applications. The AD9854's innovative high-speed DDS core reference clock. This saves the user the expense and difficulty of
provides 48-bit frequency resolution (1 microHertz tuning steps). implementing a 300 MHz clock source. Direct 300 MHz clocking
Phase truncation to 17-bits assures excellent digital SFDR. The is also accommodated with either single-ended or differential
AD9854's circuit architecture allows the generation of inputs. Single-pin conventional FSK and the enhanced spectral
simultaneous quadrature outputs at frequencies up to 150 MHz, qualities of ramped FSK are supported. The AD9854 uses

which can be digitally tuned at a rate of up to 100 million new advanced .35 micron CMOS technology to provide this high level
frequencies per second. The (externally filtered) sine wave output of functionality on a single +3.3 V supply.
can be converted to a square wave by the internal comparator for
agile clock generator applications. The device provides 14-bits of The AD9854 is available in a space-saving 80-pin QFP surface
digitally-controlled phase modulation and single-pin PSK. The mount package. The AD9854 is pin-for-pin compatible with the
on-board 12-bit I & Q DACs, coupled with the innovative DDS AD9852 single-tone synthesizer. It is specified to operate over
architecture, provide excellent wideband and narrowband output the extended industrial temperature range of -40°to +85°
C.
SFDR. The Q-DAC can also be configured as a user-
programmable control DAC if the quadrature function is not
Preliminary Pin Assignments
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60 AVDD
D7 1
PIN 1 59
D6 2 AGND
IDENTIFIER
58 nc
3
D5
57
nc
4
D4
56 DAC Rset
D3 5
55
DACBP
6
D2
54 AVDD
D1
7
AD9854
53
AGND
D0 8
TOP VIEW 52
DVDD 9 IOUT2
(Not to Scale)
51 IOUT2B
10
DVDD
80-PIN LQFP 14 x 14 x 1.4
DGND 50 AVDD
11
49 IOUT1B
DGND 12
48
nc IOUT1
13
47
A5 14 AGND
46
15 AGND
A4
45
AGND
16
A3
44
AVDD
17
A2/IO RESET
43 VINN
A1/SDO 18
42 VINP
19
A0/SDIO
41
AGND
20
I/O UD
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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Master RESET
AVDD
DVDD
DVDD
DGND
DGND
DGND
DGND
DVDD
DVDD
DGND
S/P SELECT
REFCLOCK
AGND
AGND
AGND
nc
Diff Clk Enable
REFCLOCKB
PLL Filter
nc
AVDD
AVDD
DGND
AGND
AVDD
AVDD
DVDD
DVDD
DVDD
DGND
DGND
AGND
VOUT
AGND
AGND
RDB/CSB
WRB/SCLK
AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS1
Maximum Junction Temp. ....................................+150° C Storage Temperature ............................ -65° C to +165° C
Vs ............................................................ +4 V Operating Temp. .................................. -40° C to +85° C
Digital Inputs ................................ -0.7 V to +Vs Lead Temp. (10 sec. soldering) ........................... +300° C
Digital Output Current ............................... 5 mA Maximum Clock Frequency& & & & & & & & TBD MHz
AD9854 PRELIMINARY ELECTRICAL SPECIFICATIONS (VS=+3.3 V Ä…5%, RSET=3.9 k&!
Ä… &!,
External reference clock frequency = 30 MHz with REFCLK Multiplier enabled at 10×
×) unless otherwise noted.
___________________________________________________________________________________________________
Parameter Temp Test Level Min Typ Max Units
REF CLOCK INPUT CHARACTERISTICS2
Internal Clock Frequency Range FULL VI 5 300 MHz
External REF Clock Frequency Range:
REFCLK Multiplier Enabled FULL VI 5 75 MHz
REFCLK Multiplier Disabled FULL VI 5 300 MHz
Duty Cycle +25°C V 50 %
Input Capacitance +25°C IV 3 pF
Input Impedance +25°C IV 100 M&!
Common-mode Voltage Range (Differential Mode) +25°C TBD V
VIH (Single-ended Mode) +25°C TBD V
VIL (Single-ended Mode) +25°C TBD V
DAC STATIC OUTPUT CHARACTERISTICS
Output Update Speed FULL I 300 MSPS
Resolution +25°C IV 12 Bits
I & Q Full-Scale Output Current +25°C IV 5 10 20 mA
I & Q DAC DC Gain Imbalance +25°C V <1 %
Gain error +25°C I -10 +10 %FS
Output Offset +25°C I 10 uA
Differential Non-linearity +25°C I .5 lsb
Integral Non-linearity +25°C I 1 lsb
Output Impedance +25°C I 100 k&!
Voltage Compliance Range +25°C I -0.5 +1.0 V
DAC DYNAMIC OUTPUT CHARACTERISTICS
I & Q DAC Quadrature Phase Error +25°C V <.1 degrees
Wideband SFDR:
1 to 20 MHz Aout +25°C V TBD 70 dBC
20 to 40 MHz Aout +25°C V TBD 65 dBC
40 to 60 MHz Aout +25°C V TBD 60 dBC
60 to 80 MHz Aout +25°C V TBD 55 dBC
80 to 100 MHz Aout +25°C V TBD 55 dBC
100 to 120 MHz Aout +25°C V TBD 55 dBC
Narrowband SFDR:
10 MHz Aout (Ä… 1 MHz) +25°C V TBD TBD dBC
10 MHz Aout (Ä… 250 kHz) +25°C V TBD TBD dBC
10 MHz Aout (Ä… 50 kHz) +25°C V TBD TBD dBC
10 MHz Aout (Ä… 10 kHz) +25°C V TBD TBD dBC
30 MHz Aout (Ä… 1 MHz) +25°C V TBD TBD dBC
30 MHz Aout (Ä… 250 kHz) +25°C V TBD TBD dBC
30 MHz Aout (Ä… 50 kHz) +25°C V TBD TBD dBC
30 MHz Aout (Ä… 10 kHz) +25°C V TBD TBD dBC
50 MHz Aout (Ä… 1 MHz) +25°C V TBD TBD dBC
50 MHz Aout (Ä… 250 kHz) +25°C V TBD TBD dBC
50 MHz Aout (Ä… 50 kHz) +25°C V TBD TBD dBC
50 MHz Aout (Ä… 10 kHz) +25°C V TBD TBD dBC
70 MHz Aout (Ä… 1 MHz) +25°C V TBD TBD dBC
70 MHz Aout (Ä… 250 kHz) +25°C V TBD TBD dBC
70 MHz Aout (Ä… 50 kHz) +25°C V TBD TBD dBC
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AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
AD9854 PRELIMINARY ELECTRICAL SPECIFICATIONS (VS=+3.3 V Ä…5%, RSET=3.9 k&!
Ä… &!,
External reference clock frequency = 30 MHz with REFCLK Multiplier enabled at 10×
×) unless otherwise noted.
Parameter Temp Test Level AD9854 Units
Min Typ Max
DAC Narrowband SFDR continued:
70 MHz Aout (Ä… 10 kHz) +25°C V TBD TBD dBC
90 MHz Aout (Ä… 1 MHz) +25°C V TBD TBD dBC
90 MHz Aout (Ä… 250 kHz) +25°C V TBD TBD dBC
90 MHz Aout (Ä… 50 kHz) +25°C V TBD TBD dBC
90 MHz Aout (Ä… 10 kHz) +25°C V TBD TBD dBC
110 MHz Aout (Ä… 1 MHz) +25°C V TBD TBD dBC
110 MHz Aout (Ä… 250 kHz) +25°C V TBD TBD dBC
110 MHz Aout (Ä… 50 kHz) +25°C V TBD TBD dBC
11 0MHz Aout (Ä… 10 kHz) +25°C V TBD TBD dBC
DAC SIGNAL-TO-NOISE RATIO (calculated) +25°C TBD dB
Residual Phase Noise (Freq TBD)
1 kHz Offset +25°C TBD dBc/Hz
10 kHz Offset +25°C TBD dBc/Hz
100 kHz Offset +25°C TBD dBc/Hz
Pipeline Delays
TBD +25°C TBD SysClk Cycles
Phase Accumulator & DSP Algorithm +25°C TBD SysClk Cycles
Inverse Sinc Filter +25°C TBD SysClk Cycles
Digital Multiplier +25°C TBD SysClk Cycles
MASTER RESET DURATION +25°C 10 SysClk Cycles
DIGITAL (AM) MULTIPLIER DYNAMIC RANGE +25°C TBD dB
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance +25°C V 3 pF
Input Resistance +25°C IV 500 k&!
Ä…
Input Current +25°C I 12 µA
Hysteresis +25°C IV 10 mV
Input Voltage Range +25°C IV 0 VDD V
COMPARATOR OUTPUT CHARACTERISTICS
Logic "1" voltage, high Z load FULL VI +2.7 V
Logic "0" voltage, high Z load FULL VI +0.4 V
Output Power, 50-ohm load, 100 MHz toggle rate +25°C IV 10 dBm
Propagation Delay +25°C IV 3 ns
Ä…
Output Duty Cycle Error3 +25°C IV 5 %
Rise/Fall Time +25°C IV 1 ns
Toggle Rate, high Z load +25°C IV 300 MHz
Toggle Rate, 50-ohm load +25°C IV 400 MHz
Output Jitter4 +25°C IV 3 ps RMS
COMPARATOR NARROWBAND SFDR5
10 MHz (Ä… 1 MHz) +25°C V TBD TBD dBC
10 MHz (Ä… 250 kHz) +25°C V TBD TBD dBC
10 MHz (Ä… 50 kHz) +25°C V TBD TBD dBC
10 MHz (Ä… 10 kHz) +25°C V TBD TBD dBC
70 MHz (Ä… 1 MHz) +25°C V TBD TBD dBC
70 MHz (Ä… 250 kHz) +25°C V TBD TBD dBC
70 MHz (Ä… 50 kHz) +25°C V TBD TBD dBC
70 MHz (Ä… 10 kHz) +25°C V TBD TBD dBC
110 MHz (Ä… 1 MHz) +25°C V TBD TBD dBC
110 MHz (Ä… 250 kHz) +25°C V TBD TBD dBC
110 MHz (Ä… 50 kHz) +25°C V TBD TBD dBC
110MHz (Ä… 10 kHz) +25°C V TBD TBD dBC
7/16/99 REV.PRA
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AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
AD9854 PRELIMINARY ELECTRICAL SPECIFICATIONS (VS=+3.3 V Ä…5%, RSET=3.9 k&!
Ä… &!,
External reference clock frequency = 30 MHz with REFCLK Multiplier enabled at 10×
×) unless otherwise noted.
 CLOCK GENERATOR OUTPUT JITTER5 @
5 MHz +25°C IV 20 ps RMS
10 MHz +25°C IV 20 ps RMS
40 MHz +25°C IV 20 ps RMS
80 MHz +25°C IV 20 ps RMS
120 MHz +25°C IV 20 ps RMS
CMOS LOGIC INPUTS
Logic "1" Voltage +25°C I 2.7 V
Logic "0" Voltage +25°C I 0.4 V
Ä…
Logic "1" Current +25°C IV 12 uA
Ä…
Logic "0" Current +25°C IV 12 uA
Input Capacitance +25°C V 3 pF
POWER SUPPLY
+Vs Current6 +25°C I 1000 mA
+Vs Current7 +25°C 600 mA
PDiss 6 +25°C 3.3 W
PDiss 7 +25°C 2 W
PDISS Power-down Mode +25°C I 10 mW
NOTES
5
1 Comparator input originates from DDS section via
Absolute maximum ratings are limiting values, to be
external 7-pole elliptic LPF. Single-ended input, .5V p-p.
applied individually, and beyond which the serviceability
Comparator output terminated 50 Ohms.
of the circuit may be impaired. Functional operability
under any of these conditions is not necessarily implied.
6
All functions engaged
Exposure of absolute maximum rating conditions for
extended periods of time may affect device reliability.
7
All functions except inverse sinc and digital multipliers
2
engaged.
The reference clock inputs are configured to accept a 1 V
p-p (minimum) dc offset sine wave centered at ½ the
applied Vdd or a 3 V TTL-level pulse input.
EXPLANATION OF TEST LEVELS
Test Level
3
Change in duty cycle from 1 to 100 MHz with 1V p-p
I - 100% Production Tested.
sine wave input and .5V threshold.
III - Sample Tested Only.
IV - Parameter is guaranteed by design and
4
Represents comparator s inherent jitter contribution.
characterization testing.
Input signal is a 1 volt, 40 MHz square wave.
V - Parameter is a typical value only.
Measurement device Wavecrest DTS  2075.
VI - All devices are 100% production tested at +25°C.
100% production tested at temperature extremes for
military temperature devices; guaranteed by design
and characterization testing for industrial devices.
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9854AST
AD9854ASQ
AD9854/PCB
7/16/99 REV.PRA
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AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
Table I. AD9854 PIN FUNCTION DESCRIPTIONS
REFCLK Pin 69. Single-ended reference clock input or one of two differential clock signals. Normal 3.3V CMOS logic
levels or 1V p-p sine wave centered about +1.6V.
REFCLKB Pin 68. The complementary (180 degrees out of phase) differential clock signal. User should tie this pin high
or low when single-ended clock mode is selected. Same signal levels as REFCLK above.
DIFF CLK Pin 64. Digital input to select either differential (logic high) or single-ended (logic low) reference clock mode.
ENABLE In the single-ended mode, pin 68 above is switched out of the clock path, and pin 69 assumes total control of
the REFCLK function. In differential mode, both pins 68 and 69 work together to provide REFCLK function.
DAC RSET Pin 56. Common connection for both I and Q DAC s to set the full-scale output current. RSET = 39.9/Iout.
Normal RSET range is from 8k (5 mA) to 2k (20 mA).
DACBP Pin 55. Common by-pass capacitor connection for both I and Q DAC s. A .01 µF chip cap from this pin to
AVDD improves harmonic distortion and SFDR slightly. No connect is permissible (slight SFDR degradation).
AGND Pins 33, 34, 39, 40, 41, 45, 46, 47, 53, 59, 62, 66, 67. Connections for analog circuitry ground return. Same
potential as DGND
DGND Pins 11, 12, 26, 27, 28, 72, 75, 76, 77, 78 . Connections for digital circuitry ground return. Same potential as
AGND
AVDD Pins 31, 32, 37, 38, 44, 50, 54, 60, 65. Connections for the analog circuitry supply voltage. Nominally 3.3
volts more positive than AGND and DGND.
DVDD Pins 9, 10, 23, 24, 25, 73, 74, 79, 80. Connections for the digital circuitry supply voltage. Nominally 3.3 volts
more positive than AGND and DGND.
MASTER Pin 71. Initializes the serial/parallel programming bus to prepare for user programming; sets programming
RESET registers to a  do-nothing state defined by the default values seen in the Register Layout table. Active on
logic high . Asserting MASTER RESET is essential for proper operation upon power-up.
IOUT1 Pin 48. Unipolar current output of the I or Sine DAC.
IOUT1B Pin 49. Complementary unipolar current output of the I or Sine DAC.
IOUT2 Pin 52. Unipolar current output of the Q or Cosine DAC. This DAC can be programmed to accept external 12-
bit data in lieu of internal Cosine data. This allows the AD9854 to emulate the AD9852 control DAC function.
IOUT2B Pin 51. Complementary unipolar current output of the Q or Cosine or  control DAC.
VINP Pin 42. Voltage input positive. The internal high-speed comparator s non-inverting input.
VINN Pin 43. Voltage input negative. The internal high-speed comparator s inverting input.
VOUT Pin 36. Internal high-speed comparator s non-inverted output pin. Designed to drive 10 dBm to 50-ohm load
as well as standard CMOS logic levels.
nc Pins 13, 35, 57, 58, 63. No internal connection.
D7  D0 Pins 1  8. 8-bit bi-directional parallel programming data inputs. Used only in Parallel Programming mode.
WRB Pin 21. Write parallel data to programming registers. Shared function with SCLK below.
RDB Pin 22. Read parallel data from programming registers. Shared function with CSB below.
A5  A0 Pins 14  19. 6-bit parallel address inputs for Program Registers. Used only in Parallel Programming mode.
A0, A1 and A2 have a second function when the Serial Programming mode is selected. See immediately
below.
SDIO Pin 19. Bi-directional serial data input/output for use in 2-wire serial communication mode.
SDO Pin 18. Uni-directional serial data output for use in 3-wire serial communication mode.
I/O RESET Pin 17. Allows a RESET of the serial communications bus that is unresponsive due to improper programming
protocol. Resetting the serial bus in this manner does not affect previous programming nor does it invoke the
 default programming values seen in the Register Layout table. Active HIGH.
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AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
Table I. AD9854 PIN FUNCTION DESCRIPTIONS& CONTINUED
SCLK Pin 21. Serial clock signal associated with the serial programming bus. Data is registered on the rising edge.
This pin is shared with WRB when the parallel mode is selected.
CSB Pin 22. Chip-select signal associated with the serial programming bus. Active LOW. This pin is shared with
RDB when the parallel mode is selected.
S/P Pin 70. Selects between Serial Programming mode (logic LOW) and Parallel Programming mode (logic HIGH)
SELECT
I/O UD Pin 20. Bi-directional frequency update signal. Direction is selected in Control Register. If selected as an
input, a rising edge will transfer the contents of the programming registers to the internal works of the IC for
processing. If I/O UD is selected as an output, an output pulse (low to high) of 8 system clock cycle duration
indicates that an internal frequency update has occurred.
FSK/BPSK/ Pin 29. Multi-function pin according the mode of operation selected in the programming control register. If in
HOLD the FSK mode logic low selects F1, logic high selects F2. If in the BPSK mode, logic low selects phase 1, logic
high selects phase 2. If in the CHIRP mode, logic high engages the HOLD function which will cause the
frequency accumulator to halt at its current location. To resume or commence CHIRP, logic low is asserted.
SHAPED Pin 30. Must first be selected in the programming control register to function. A logic high will cause the I &
KEYING Q DAC outputs to ramp-up from zero-scale to full-scale amplitude at a pre-programmed rate. Logic low causes
the full-scale output to ramp-down to zero-scale at the pre-programmed rate.
PLL Pin 61. Connection for external series RC loop filter to Vdd. Recommended component values 1.3k and .01µF.
FILTER
Synthesizer Functional Description logic high. The update clock down-counter function
operates at the system clock/2 (150 MHz maximum)
Internal & External Update Clock  This function is and counts down from a 32-bit binary value
comprised of a bi-directional I/O pin, Pin 20, and a (programmed by the user). When the count reaches 0,
programmable 32-bit down-counter. In order for an automatic I/O Update of the DDS output or
programming changes to be transferred from the I/O functions is generated. The update clock is routed
Buffer registers to the active core of the DDS, a clock internally and externally on Pin 20 to allow users to
signal (low to high edge) must be externally supplied synchronize programming of update information with
to Pin 20 or internally generated by the 32-bit Update the update clock rate. The time period between update
Clock. pulses is given as (N+1) *(SYSTEM CLOCK
PERIOD/2), where N is the 32-bit value programmed
An externally generated Update Clock is internally by the user. Allowable range of N is from 1 to (232 
synchronized with the system clock to prevent partial 1). The internally generated Update pulse output on
transfer of program register information due to Pin 20 has a fixed duration of ten system clock cycles
violation of data setup or hold times. This mode gives
the user complete control of when updated program Shaped On-Off Keying Allows user to control the
information becomes effective. The default mode is set ramp-up and ramp-down time of an  on-off emission
for internal update clock (Int Update Clk control from the I and Q DACs. This function is used in  burst
register bit is logic high). To switch to external update transmissions of digital data to reduce the adverse
clock mode, the Int Update Clk register bit must be set spectral impact of short, abrupt bursts of data. Users
to logic low. The internal update mode generates must first enable the digital multipliers by setting the
automatic, periodic update pulses whose time period is OSK EN bit (control register address 20 hex) to logic
set by the user. high in the control register. Otherwise, if OSK EN bit
is set low, the digital multipliers responsible for
An internally generated Update Clock can be amplitude-control are by-passed and the I and Q DAC
established by programming the 32-bit Update Clock outputs are set to full-scale amplitude.
registers (address 16-19 hex) and setting the Int
Update Clk (address 1F hex) control register bit to
7/16/99 REV.PRA
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AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
Abrupt on-off keying
Shaped on-off keying
In addition to setting the OSK EN bit, a second control Next, the transition time from zero-scale to full-scale
bit, OSK INT (also at address 20 hex) must be set to must be programmed. The transition time is a function
logic high. Logic high selects the linear internal of two fixed elements and one variable. The variable
control of the output ramp-up or ramp-down function. element is the programmable 8-bit RAMP RATE
A logic low in the OSK INT bit switches control of the COUNTER.. This is a down-counter being clocked at
digital multipliers to user programmable 12-bit the system clock rate (300 MHz max.) that outputs one
registers allowing users to dynamically shape the pulse whenever the counter reaches zero. This pulse is
amplitude transition in practically any fashion. These routed to a 12-bit counter that increments one LSB for
12-bit registers, labeled  Output Shape Key I and every pulse received. The outputs of the 12-bit counter
Output Shape Key Q are located at address s 21 are connected to the 12-bit digital multiplier. When the
through 24 hex in the register layout table. The digital multiplier has a value of all zero s at its inputs,
maximum output amplitude is a function of the Rset the input signal is multiplier by zero, producing zero-
resistor and is not programmable; however, in the OSK scale. When the multiplier has a value of all one s, the
INT mode users can program any amplitude between input signal is multiplied by a value of 1, producing
zero and full-scale as the maximum output level. full-scale. There are 4094 remaining fractional
multiplier values that will produce output amplitudes
corresponding to their binary values.
OSK EN = 0
OSK EN = 0
(Bypass Multiplier)
DIGITIAL
SRC QDAC = 0
SIGNAL IN
12
12
Q DAC
12 BIT DIGITAL
MULTIPLIER
OSK EN = 1
OSK EN = 1
SRC QDAC = 1
12-bit QDAC
register (User
12
programmable)
User Programmable 12-
12
bit Q-channel multiplier
"Output Shape Key Q
OSK INT = 1
Mult" register OSK INT = 0
12
12-BIT 8-BIT DOWN SYSTEM
1
COUNTER COUNTER CLOCK
SHAPED KEYING PIN
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AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
Above: Block diagram of Q-pathway of the digital multiplier section responsible for Shaped Keying function.
The I-pathway is similar except no alternate 12-bit Q-DAC source register is provided.
The two fixed elements are the clock period of the DAC output amplitude variations over frequency to
system clock (that drives the Ramp Rate Counter) and achieve flat amplitude response from dc to Nyquist.
the 4096 amplitude steps between zero-scale and full- Digital multipliers follow the inverse sinc filters to
scale. To give an example, assume that the System allow amplitude control, amplitude modulation and
Clock of the AD9854 is 100 MHz (10 ns period). If amplitude shaped keying. The inverse sinc filters
the Ramp Rate Counter is programmed for a minimum (address 20 hex, Bypass Inv Sinc bit)) and digital
count of 1, it will take two system clock periods (one multipliers (address 20 hex, OSK EN bit) can be
rising edge loads the count-down value, the next edge bypassed for power conservation by setting those bits
decrements the counter from 1 to zero). The high. Both DACs can be powered-down by setting the
relationship of the 8-bit count-down value to the time
DAC PD bit high (address 1D of control register)
period between output pulses is given as: (N+1) * when not needed.
SYSTEM CLOCK PERIOD, where N is the 8-bit
count-down value. It will take 4096 of these pulses to I-DAC outputs are designated as IOUT1 and IOUT1B,
advance the 12-bit up-counter from zero-scale to full- pins 48 and 49 respectively. Q-DAC outputs are
scale. Therefore, the minimum shaped keying ramp designated as IOUT2 AND IOUT2B, pins 52 and 51
time for a 100 MHz system clock is 4096 * 2 * 10 ns respectively.
= approximately 82 microseconds. The maximum
ramp time will be 4096 * 256 * 10 ns * 4096 =
Control DAC  The 12- bit Q DAC can be
approximately 10.5 msec.
reconfigured to perform as a  control or auxiliary
DAC as in the AD9852. The control DAC output can
Finally, changing the logic stage of pin 30,  shaped
provide DC control levels to external circuitry, AC
keying will automatically perform the programmed
signals or enable pulse-width modulation (PWM), or
output envelope functions when OSK INT is high. A
duty cycle control, of the on-board comparator when
logic high on Pin 30 causes the outputs to linearly
appropriately configured in the clock generator
ramp-up to full-scale amplitude and hold until the logic
application. When the SRC QDAC bit in control
level is changed to low causing the outputs to ramp-
register (address 1F hex) is set high, the Q-DAC inputs
down to zero-scale.
are switched from internal 12-bit Q data source
(default setting) to external 12-bit data supplied by the
I & Q DACs  the 300 MSPS (maximum) sine and
user through the serial or parallel interface to the 12-bit
cosine wave outputs of the DDS. Their maximum
Q DAC register (address 26 and 27 hex) at 100 MHz
output amplitudes are set by the DAC RSET resistor at
(maximum) data rate. This DAC is clocked at the
pin 56. These are current-out DACs with a full-scale
system clock, 300 MSPS (maximum), and has the
maximum output of 20 mA; however, a nominal 10
same maximum output current capability as that of the
mA output current provides best spurious-free dynamic
I DAC. The single RSET resistor on the AD9854 sets
range (SFDR) performance. The value of RSET =
the full-scale output current for both DACs. The
39.93/Iout, where Iout is in amps. DAC output
control DAC can be separately powered-down for
compliance specification limits the maximum voltage
power conservation when not needed by setting the Q
developed at the outputs to -.5 to +1V. Voltages
DAC POWER-DOWN bit high (address 1D hex).
developed beyond this limitation will cause excessive
DAC distortion and possibly permanent damage. The
Control DAC outputs are designated as IOUT2 and
user must choose a proper load impedance to limit the
IOUT2B, pins 52 and 51 respectively.
output voltage swing to <= compliance limits. Both
DAC outputs should be terminated equally for best
Inverse SINC function  this filter pre-compensates
SFDR, especially at higher output frequencies where
input data to both DACs for the SIN (X)/X roll-off
harmonic distortion is at its worst.
function to allow wide bandwidth signals (such as
QPSK) to be output from the DACs without
Both DACs are preceded by inverse SIN (X)/X filters
appreciable amplitude variations that will cause
(a.k.a. inverse sinc filters) that pre-compensate for
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increased EVM (error vector magnitude). The inverse Inverse sinc is engaged by default and is bypassed by
SINC function may be by-passed to significantly bringing the  Bypass Inv Sinc bit high in control
reduce power consumption, especially at higher clock register 20 (hex) in the Register Layout Table.
speeds. When the Q-DAC is configured as a  control
DAC, the inverse sinc function does not apply.
Fundamental output power decreases
Fundamental output power is
with increasing frequency
 flat from dc to ½ FCLK
Normal Sin x/x power envelope Inverse Sin x/x (inverse sinc) filter engaged
REFCLK Multiplier  this is a programmable PLL Use of this function allows users to input as little as 15
reference clock multiplier that allows the user to select MHz to produce a 300 MHz system clock. Five bits in
an integer clock multiplying value over the range of 4× control register 1E hex set the multiplier value as
to 20× by which the REFCLK input will be multiplied. follows:
Multiplier Ref Mult 4 Ref Mult 3 Ref Mult 2 Ref Mult 1 Ref Mult 0
Value
4 0 0 1 0 0
5 0 0 1 0 1
6 0 0 1 1 0
7 0 0 1 1 1
8 0 1 0 0 0
9 0 1 0 0 1
10 0 1 0 1 0
11 0 1 0 1 1
12 0 1 1 0 0
13 0 1 1 0 1
14 0 1 1 1 0
15 0 1 1 1 1
16 1 0 0 0 0
17 1 0 0 0 1
18 1 0 0 1 0
19 1 0 0 1 1
20 1 0 1 0 0
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The PLL function can be bypassed to allow direct (REFCLKB) should be tied low or high but not left
clocking of the AD9854 from an external clock source. floating.
The system clock for the AD9854 is either the output
of the REFCLK Multiplier (if it is engaged) or the Parallel/Serial programming mode - setting pin 70
REFCLK inputs. REFCLK may be either a single- high invokes parallel mode, whereas setting pin 70 low
ended or differential input by setting pin 64, Diff Clk will invoke the serial programming mode. Refer to the
Enable, low or high respectively. extensive description of the serial and parallel
programming protocol elsewhere in this data sheet.
A  PLL Range bit in the control register (address 1E
Two control bits located at address 20 hex in the
hex) allows the VCO  gain to be increased (logic
Register Layout table apply only to the serial
high) or decreased (logic low). Decreased gain means
programming mode.
that the VCO becomes less responsive to changes in
control voltage. Increased gain makes the VCO more LSB First when high dictates that serial data will be
responsive to changes in control voltage and will loaded starting with the LSB of the word. When low
increase the VCO frequency range. Any noise on the (the default value) serial data is loaded starting with
VCO control voltage line will cause an increase in the MSB of the word. SDO Active when high
phase noise of the oscillator. If the VCO gain is indicates that the SDO pin, Pin 18, is dedicated to
increased, then phase noise will increase as well. The reading back data from the AD9854 registers. When
default value of this bit is logic high  highest gain  to SDO Active is low (default value), this indicates that
accommodate a maximum clock speed of 300 MHz. If the SDIO pin, Pin 19 acts as a bi-directional serial data
the system clock is to be less than 200 MHz, it is best input and output pin and Pin 18 has no function in the
to set this bit low for best phase noise performance. serial mode.
Pin 61. PLL Filter, is the connection for an external Modes of Operation  single-tone, FSK, ramped
RC loop filter consisting of a 1.3k resistor in series FSK, CHIRP and PSK modes are selected according to
with a .01 µF capacitor tied to 3.3 volts. The filter is three MODE bits in control register 1F (hex) in the
user supplied and must be present for proper REFCLK Register Layout Table. The following table applies:
Multiplier functioning. The filter is connected directly
to the PLL phase detector charge pump output stage. M[2] M[1] M[0] FUNCTION INVOKED
Users should exercise care to avoid injecting noise onto
0 0 0 Single-tone
this line that controls the VCO output frequency.
0 0 1 Frequency-shift keying (FSK)
0 1 0 Ramped FSK
When REFCLK multiplier is not needed it can be
0 1 1 CHIRP
powered-down by setting the PLL POWER-DOWN
bit high or by-passed by setting the  Bypass PLL bit
1 0 0 Phase-shift keying (BPSK)
high in control register address 1D and 1E (hex)
respectively.
Each mode will initially use the default conditions that
are invoked upon power-up and Master Reset. The
Differential REFCLK Enable: Bringing pin 64 high
default conditions setup a  do-nothing state at the
enables the differential clock mode. In this mode,
DAC outputs (0 Hz, 0 degrees phase, minimum
REFCLK and REFCLKB (pins 69 and 68) are
amplitude. A brief discussion of each mode, associated
assumed to carry clock signals (3.3V CMOS logic
programming registers and control bits follows:
levels or 1V p-p dc offset (to ½ Vdd) sine waves)
whose phases differ by 180 degrees. Differential clock
Single-Tone Mode: This is the default mode
signals are preferred over single-ended clocking of the
after a master reset. The frequency is
AD9854/52.
determined by the 48-bit Frequency Tuning
Word 1 register at address 4  9 hex, and the
When pin 64 (Diff Clk Enable) is tied low, REFCLK
phase is set in 14-bit Phase Adjust Register 1
(pin 69) is the only active clock input. This is referred
at address 0-1 hex. I & Q output amplitude
to as the single-ended mode. In this mode, pin 68
can be adjusted in 12-bit registers located at
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register address 21  24 hex. Default values
of frequency, phase and amplitude are all zero. BPSK Mode: Abbreviation for binary, bi-
To set the output amplitudes to full-scale (not phase or bipolar-phase-shift-keying. Nearly
adjustable) change the OSK EN, address 20 identical to the FSK mode except P1 (14-bit
hex, bit to logic low (see amplitude discussion phase tuning word 1, register address 0  1
under previous Shaped Keying heading). hex) and P2 (phase tuning word 2, register
address 2  3 hex) are selected according to
As with all Analog Devices DDS s, the value the logic state of Pin 29. The output
of the frequency tuning word is determined frequency is set in frequency tuning word 1
using the following equation: FTW = registers. The 14-bit phase values range from
(desired output frequency * 2N)/SYSCLK. all 0 s = 0 degrees offset to all 1 s = 359.978
Where N is the phase accumulator resolution degrees offset. The value of 1 LSB is
(48 bits in this instance), frequency is 360/16384 or .022033691 degrees. Phase
expressed in Hertz, and the FTW, frequency offsets apply equally to both the I and Q
tuning word, is a decimal number. Once a outputs (unless the Q DAC is configured as an
decimal number has been found, it must be auxiliary DAC)
converted to binary format  a series of 48
binary-weighted 1 s OR 0 s. he fundamental Ramped FSK: A method of FSK
output frequency range is from dc to ½ whereby changes from F1 to F2 are
SYSCLK. not instantaneous but instead are
accomplished in a frequency sweep or
Phase adjust Register #2 and Frequency  ramping fashion. This means that
Tuning Word #2 are not accessible in this many intermediate frequencies may be
mode. Pin 29,  FSK, BPSK,HOLD , has no output in addition to the primary F1
effect. and F2. The purpose of ramped FSK
is to provide better bandwidth
The I and Q DAC s are always 90 degrees containment by  softening the
out-of-phase. Changing the value in the Phase instantaneous frequency changes with
Adjust Register 1 as suggested above will gradual changes. The dwell time at F1
change the phase of both I and Q DAC s and F2 can be much greater than those
simultaneously and by the same amount so that of the intermediate frequencies or
both are at some phase offset relative to some equal to the time spent at each of the
other event. intermediate frequencies. Unlike
unramped FSK, ramped FSK requires
Changes in frequency are phase continuous  the lowest frequency to be loaded into
that is, the new frequency uses the last phase F1 registers and the highest frequency
of the old frequency as a reference point to into F2 registers.
compute the first new frequency phase.
Several registers must be programmed to
FSK Mode: When selected, the output instruct the DDS regarding the resolution of
frequency of the DDS is a function of the intermediate frequency steps and the time spent
values loaded into Frequency Tuning Word at each step.
registers 1 & 2 AND the logic level of Pin 29.
A logic low on Pin 29 (FSK/BPSK/HOLD) Register addresses 1A  1C hex comprise the
chooses F1 (frequency tuning word 1, address Ramp Rate Clock register. This is a
4  9 hex) and a logic high chooses F2 count-down counter that outputs a pulse
(frequency tuning word 2, register address A  whenever the count reaches zero. This counter
F hex). Changes in frequency are practically is being clocked at the System Clock Rate, 300
instantaneous and phase continuous. Other MHz maximum, and it operates exactly as the
than F2 and Pin 29 becoming active, this mode 8-bit ramp rate counter described in the
is identical to single-tone. previous section labeled  Shaped On-Off
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Keying . The output of this counter is time it receives a pulse from the ramp rate
clocking the 48-bit Frequency Accumulator clock. The output of this accumulator is added
shown as  Accu 1 below. The Ramp Rate to or subtracted from the F1 or F2 frequency
Clock determines the time spent at each word which is fed to the input of the 48-bit
intermediate frequency between F1 and F2. Phase Accumulator that forms the numerical
The  dwell time spent at F1 and F2 is phase steps for the sine and cosine wave
determined by the duration that the FSK input output. In this fashion, the output frequency is
pin, pin 29, is held high or low after the ramped-up and down according to the state of
destination frequency has been reached. Pin 29 and the speed at which this happens is a
function of the 20-bit ramp rate clock. Once
Register addresses 10  15 hex are for the 48- the destination frequency is achieved, the ramp
bit  Delta Frequency Word . This 48-bit rate clock is stopped and this halts the
word is accumulated (added to itself) every frequency accumulation process.
ADDER Out
Accu 2
Accu 1
48-Bit Delta-
Frequency
Word
Frequency Frequency
Tuning Tuning
Word 1 Word 2
20-Bit
System
Ramp Rate
Clock
Clock
FSK
(pin 29)
The control register contains a Triangle Bit at counter on-the-fly (during the ramping from
register address 1F. Setting the bit high causes F1 to F2). To create non-linear frequency
an automatic ramp-up and ramp-down changes it is necessary to combine several
between F1 and F2 without having to toggle linear ramps in a piece-wise fashion whose
Pin 29. This uses the ramp-rate-clock time slopes are different. This is done by starting a
period and the delta-frequency-word step size linear ramp at some rate or  slope and then
to form a continuously sweeping linear ramp changing the slope (by changing the ramp rate
from F1 to F2 and back to F1. This is not clock or delta frequency word or both) as often
FSK or ramped FSK; it is an easily as necessary to form the desired non-linear
implemented function that users may find frequency response before the destination
useful for linear frequency sweeping of the frequency has been reached. These changes
DDS output. can be precisely timed using the 32-bit
Internal Update Clock (see detailed
To make the linear, ramped FSK mode even
description elsewhere in this data sheet).
more flexible, users can change the 48-bit delta
frequency word and/or the 20-bit ramp-rate
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Finally, two more control bits are available to allow triggerable one-shot event. As long as
CLR ACC1 bit is logic high, a zeroing of
even more options. CLR ACC1,
the frequency accumulator output will
occur on every Update Clock rising edge.
register address 1F hex, if set high will clear
After the accumulator has been zeroed, it
the frequency accumulator (Acc 1) output with
will resume normal accumulation
a one-shot pulse of one system clock duration.
functions using all-zeros as the beginning
The effect is to interrupt the current ramp,
point. This bit defaults to logic low, which
reset the frequency back to the start point, F1,
prevents zeroing of the frequency
and then continue to ramp up at the previous
accumulator from this source.
rate. Next, CLR ACC2 control bit (register
address 1F hex) is available to clear the phase
2) CLR ACC2 control bit causes the output
accumulator (ACC 2). When this bit is set
of the 48-bit Phase Accumulator to be zero ed.
high, the output of ACC2 is set to zero
This causes the output frequency to go to 0
resulting in 0 Hz output from the DDS at a
Hertz as long as this control bit is set to logic
phase angle existing just before the CLR
high. In addition, this results in a zeroing of
ACC2 bit was set to logic high. As long as
the Frequency Accumulator. The condition
this bit is set high, the phase accumulator will
persists for both accumulators until the CLR
be cleared and 0 Hertz will be output. To
ACC2 bit is returned to logic low (default
resume normal DDS operation, CLR ACC2
value). Upon return to logic low, the DDS
must be logic low.
output will return to the frequency
programmed into Frequency Tuning Word 1
FM CHIRP  Allows precise, internally
registers (F1) and the chirp will resume as
generated linear or non-linear FM over a user
previously programmed.
defined frequency range, duration, frequency
resolution and sweep direction(s). The user
3) The UPDATE CLK control bit allows
programs a start or base frequency into
precisely timed Update Clock pulses to be
Frequency Tuning Word 1 (register address 4
internally generated according to the setting of
 9 hex), the frequency step resolution into the
the 32-bit Update Clock down-counter
48-bit Delta Frequency Word (register address
described on page 6. Between internally
10  15 hex) and rate of change into the 20-bit
generated update clock pulses, the user can
Ramp Rate Clock (Register address 1A  1C).
write changes to the program registers that will
Chirp stops on a HOLD command, logic high
take effect upon receipt of a new update pulse.
on Pin 29, or when a value of 0 is loaded as a
Pin 20, I/O UD, will be pulsed high for 10
Delta Frequency Word. In this state, the output
system clock cycles as evidence that an
frequency remains at the frequency just before
internal update has occurred. This is
the halting action was asserted.
especially useful for non-linear Chirp where
intensive programming of various registers is
Several control bits permit numerous options
required.
in the Chirp mode. Any of these options may
use either linear or non-linear frequency
4) OSK EN and the OSK INT control bits
progression. The control bits that provide these
allow users to control the amplitude of the
options are: CLR ACC1, CLR ACC2, INT
DDS output either directly via the parallel or
UPDATE CLK, OSK EN, OSK INT. The
serial port and automatically using the 8-bit
following is a brief description of what these
Ramp Rate down-counter and 12 bit up-
control bits do:
counter. The registers associated with these
control bits and logic states controlling these
1) CLR ACC1 control bit causes the output
bits are covered in the  Shaped On-Off
of the 48-bit Frequency Accumulator to be
Keying section of this preliminary data sheet.
set to zero for one system clock period.
The effect is to return the Chirp signal to
its origin (F1). This is similar to a re-
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As with the ramped FSK mode, a non-linear chirp is
created by constructing the progression in a piece-wise c) Stop and abruptly terminate the transmission using
fashion. the CLR ACC 2 bit.
Chirp operation of the AD9854 is less automated than
the ramped FSK mode particularly regarding the d) Continue chirp by reversing direction and returning
destination frequency, which is not actually specified in to the same or another destination frequency in a
the programming registers. It is incumbent upon the linear or user-directed manner. If this involves
user to know when the destination frequency has been going down in frequency then a negative 48-bit
achieved. The value of the 48-bit Delta Frequency Delta Frequency Word (the MSB is set to  1 )
Word(s) and the 20-bit Ramp Rate Clock value(s) are must be loaded into registers 10  15 hex. Any
all that are needed to calculate when the destination decreasing frequency step of the Delta Frequency
frequency will occur. It is up to the user to determine Word requires the MSB to be set to logic high.
what occurs when the destination frequency is reached.
Here are a few of the choices: e) Continue chirp by immediately returning to the F1
beginning frequency in a saw tooth fashion and
a) Stop and hold at the destination frequency using repeat the previous chirp process again. This is
the HOLD pin, Pin29, or by loading zero into the where CLR ACC1 control bit is used. An
Frequency Accumulator register of ACC 1. Either automatic chirp can be setup using the 32 bit
method will work. Update Clock to issue CLR ACC1 commands at
precise time intervals.
b) Stop, hold and then ramp-down the output
amplitude using the digital multiplier stages and The figure below shows how the various chirp
the Shaped Keying pin, Pin30, or via program registers, accumulators, etc. are connected.
register control (address s 21  24 hex).
Accu 2
Accu 1
48-Bit Delta-
Frequency
Word
I/O Port Buffers  100 MHz, 8-bit parallel or 10 program instructions supplied by the user or until
MHz serial loading, SPI compatible. The programming power is removed. An I/O Update clocks-in the data
mode is selected externally via the serial/parallel (S/P from the I/O Buffers to the DDS Programming
Select) pin. I/O Buffers can be written to, or read from, Registers where it is executed.
according to the signals supplied to the Read
(RDB)and Write pins (WRB) and the 6-bit address AM  amplitude modulation of the I & Q DACs is
(A0  A5) in the parallel mode or to CSB, SCLK and possible using the I/O port to control 12-bit digital
SDIO pins in the Serial mode. Data in the I/O Port multiplier stages that precede the DACs. The
Buffers is stored until overwritten by changes in multipliers can also be used to set the DAC outputs
7/16/99 REV.PRA
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between zero and full-scale for static amplitude register is periodically incremented at a rate set by the
adjustment. Both I and Q DAC amplitudes are 20-bit ramp rate clock (150 MHz maximum).
individually programmable. See the  Shaped On-Off
Keying description for more information. This Forty-eight-bit Delta Phase Register  is
function does not apply to the Q DAC when configured programmed with a 48-bit Frequency Tuning Word
as a Control DAC. In this instance, the user is in that is input to the 48-bit Phase Accumulator (ACCU
control of the Control DAC output level via the 12-bit 2) and determines the output frequency of the DDS in
QDAC register at address 26 and 27 hex of the the single-tone mode. When ramped-FSK or Chirp are
programming registers selected, this register is sent to a digital adder where it
is summed with the output of ACCU 1 before being
High Speed Comparator  optimized for high speed, input to ACCU 2. Therefore, the signal sent to ACCU
> 300 MHz toggle rate, low jitter, sensitive input, 2 may be either static or changing at a rate of up to
built-in hysteresis and an output level of one Volt p-p 150 million 48-bit frequency tuning words per second.
minimum into 50 ohms or CMOS logic levels into high
impedance loads. The comparator can be separately Power-Down - Several individual stages, when not
powered-down to conserve power. This comparator is needed, can be powered-down to reduce power
used in  clock generator applications to square-up a consumption via the programming registers while still
bandpass or lowpass filtered sine wave. maintaining functionality of desired stages. These
stages are identified in the Register Layout table,
Eight-bit Ramp Rate Clock  when Shaped On-Off address 1D hex. Power-down is achieved by setting
Keying is engaged, this down-counter takes the system the specified bits to logic high. A logic low indicates
clock (300 MHz maximum), and divides it by an 8-bit that the stages are powered-up
binary value (programmed by the user) to produce a
user-defined clock. The clock outputs one pulse every Furthermore, and perhaps most significantly, two
time the counter counts down to zero. This clock is intensely digital stages, the Inverse Sinc filters and the
used to set the rate-of-change of the 12-bit digital Digital Multiplier stages can be bypassed to achieve
multipliers of the I & Q DACs to perform an output significant power reduction through programming of
shaping function. the control registers in address 20 hex. Again, logic
high will cause the stage to be by-passed. Of
Twenty-bit Ramp Rate Clock  when selected, this particular importance is the Inverse Sinc filter. When
down-counter takes the system clock (300 MHz clocked at the maximum 300 MHz, this stage
maximum) and divides it by a 20-bit binary value consumes 1.5 watts. If low power consumption is a
(programmed by the user) to produce a user-defined critical factor then bypassing of the Inverse Sinc filter
clock. The clock outputs one pulse every time the will save 1.5 watts.
counter counts down to zero. This clock is used to set
the rate-of-frequency-change of the ramped FSK or A full power-down occurs when all five PD Bits in
FM CHIRP modes. See Figure 1. control register 1D hex are set to logic high. This
reduces power consumption to approximately 10 mW
Forty-eight-bit Delta Frequency Register  is used (3 ma).
only in the CHIRP and ramped FSK modes. This
register is loaded with a 48-bit word that represents the Master RESET  logic high active, must be held high
frequency increment value of Frequency Accumulator for a minimum of 10 system clock cycles. Causes the
(ACCU 1) whose output will be added to a frequency communications bus to be initialized and loads default
that is set in either F1 or F2 frequency registers. This values listed in the Register Layout table.
AD9854 PRELIMINARY TECHNICAL DATA
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Above: AD9854 and AD9852 Package dimensions
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Parallel Serial AD9854/52 Register Layout
Address Address
Hex Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default
Value
00 0 Phase Adjust Register #1 <13:8> (Bits 15, 14 open) Phase 1 00h
01 Phase Adjust Register #1 <7:0>
02 1 Phase Adjust Register #2 <13:8:> (Bits 15, 14 open) Phase 2 00h
03 Phase Adjust Register #2 <7:0>
04 2 Frequency Tuning Word 1 <47:0> Frequency 1 000000h
05 Frequency Tuning Word 1 <39:32>
06 Frequency Tuning Word 1 <31:24>
07 Frequency Tuning Word 1 <23:16>
08 Frequency Tuning Word 1 <15:8>
09 Frequency Tuning Word 1 <7:0>
0A 3 Frequency Tuning Word 2 <47:40> Frequency 2 000000h
0B Frequency Tuning Word 2 <39:32>
0C Frequency Tuning Word 2 <31:24>
0D Frequency Tuning Word 2 <23:16>
0E Frequency Tuning Word 2 <15:8>
0F Frequency Tuning Word 2 <7:0>
10 4 Delta Frequency Word <47:40> 00000h
11 Delta Frequency Word <39:32>
12 Delta Frequency Word <31:24>
13 Delta Frequency Word <23:16>
14 Delta Frequency Word <15:8>
15 Delta Frequency Word <7:0>
16 5 Update Clock <31:24> 64(dec)
17 Update Clock <23:16>
18 Update Clock <15:8>
19 Update Clock <7:0>
1A 6 Ramp Rate Clock <19:16> (Bits 23, 22, 21, 20 open) 000h
1B Ramp Rate Clock <15:8>
1C Ramp Rate Clock <7:0>
Open Open Open CompPD PLL PD QDAC DAC PD DIG PD
1D 7 00h
PD
Open PLL Bypass Ref Mult Ref Mult Ref Mult Ref Mult Ref Mult
64h
1E
Range PLL 4 3 2 1 0
CLR CLR Triangle SRC Mode 2 Mode 1 Mode 0 Int Update
01h
1F
Acc Acc 2 QDAC Clk
1
20
Open Bypas OSK EN OSK Open Open LSB First SDO
20h
s Inv INT Active
Sinc
21 8 Output Shape Key 1 Mult <11:8> (Bits 15, 14, 13, 12 open) 000h
22 Output Shape Key 1 Mult <7:0>
23 9 Output Shape Key Q Mult <11:8> (Bits 15, 14, 13, 12 open) 000h
24 Output Shape Key Q Mult <7:0>
25 A Output Shape Key Ramp Rate <7:0> 128(dec)
26 B QDAC <11:8> (Bits 15, 14, 13, 12 open) 00h
27 QDAC <7:0>
Table 1: Register Layout. Shaded bits above comprise the  Control Register
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Programming the AD9854/52
Regardless of mode, the IO port data is written to a
The AD9854/52 Register Layout, shown in Table 1, buffer memory that does NOT affect operation of the
contains the information that programs the chip for the part until the contents of the buffer memory is
desired functionality. While many applications will transferred to the register bank. This transfer of
require very little programming to configure the information occurs synchronous to the system clock
AD9854/52, some will make use of all 12 registers that and occurs in one of two ways, 1) internally controlled
are accessible. The AD9854/52 supports an 8-bit at a rate programmable by the user or, 2) externally
parallel IO operation or a SPI compatible serial IO controlled by the user. IO operations can occur in the
operation. All registers accessible can be written and absence of REFCLK but the data cannot be moved
read back in either IO operating mode. from the buffer memory to the register bank without
An external pin, SPSELECT, is used to configure the REFCLK. See the Update Clock Operation section of
IO mode. Systems that use the parallel IO mode must this document for details.
tie the SPSELECT pin to VDD. Systems that operate
in the serial IO mode must tie the SPSELECT pin to
GND.
AD9854/52 IO Port Block Diagram
buf_phAdjust1<13:0> phAdjust1<13:0>
buf_phAdjust2<13:0> phAdjust2<13:0>
buf_ftw1<47:0> ftw1<47:0>
Addr<5:0>
buf_ftw2<47:0> ftw2<47:0>
buf_delPh<47:0> delPh<47:0>
D<7:0>
buf_udClk<31:0>
Buffer
Register
___
Memory
buf_RRC<19:0> RRC<19:0>
Bank
WR
Latches
buf_CTL<31:0> CTL<31:0>
___
buf_outRampIMult<15:0> outRampIMult<15:0>
RD
buf_outRampQMult<15:0> outRampQMult<15:0>
buf_outRampRate<7:0> outRampRate<7:0>
buf_QDAC<11:0> QDAC<11:0>
sysclk
updateRegs
IntUpdateActive
UPDATE_CLK
Update Clock Logic
sysclk
hold
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Tristate
AD9854 PRELIMINARY TECHNICAL DATA
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Parallel IO Operation
Parallel IO operation allows write access to each byte
With the SPSELECT pin tied high, the parallel IO
of any register in a single IO operation at 100Mhz.
mode is active. The IO port is compatible with industry
Read back capability for each register is included to
standard DSPs and micro-Controllers. Six address bits,
ease designing with the AD9854/52. Reads are not
8 bi-directional data bits and separate write/read
guaranteed at 100Mhz as they are intended for
control inputs make up the IO port pins (Figure
software debug only.
above).
Parallel IO operation timing diagrams and are shown in
the figures below.
AD9854/52 Parallel Port Write Timing Diagram
February 22, 1999
A<5:0> A1 A2 A3
D<7:0> D1 D2 D3
____
WR
TASU TDSU TAHD
TDHD
TWRHIGH TWRLOW
TWR
Specification Value Description
TASU ~3ns Address Setup Time To WR Singal Active
TDSU ~3ns Data Setup Time To WR Signal Inactive
TADH ~3ns Address Hold Time To WR Signal Inactive
TDHD ~3ns Data Hold Time To WR Signal Inactive
TWRLOW ~5ns WR Signal Minimum Low Time
TWRHIGH T + T WR Signal Minimum High Time
ASU AHD
TWR T + T WR Signal Minimum Period
WRLOW WRHIGH
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AD9854 PRELIMINARY TECHNICAL DATA
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AD9854/52 Parallel Port Read Timing Diagram
February 22, 1999
A<5:0> A1 A2 A3
D<7:0> D1 D2 D3
____
RD
TRDLOV
TRDHOZ
TAHD
TADV
Specification Value Description
TADV tbd Address To Data Valid Time (maximum)
TADH tbd Address Hold Time To RD Signal Inactive (minimum)
TRDLOV tbd RD Low to Output Valid (maximum)
TRDHOZ tbd RD High To Data Tristate (maximum)
Serial Port IO Operation
the AD9854/52 and can be configured as a single pin IO
(SDIO) or two unidirectional pins for in/out
With the SPSELECT pin tied low, the serial IO mode (SDIO/SDO). Data transfers are supported in most
is active. The AD9854/52 serial port is a flexible, significant bit (msb) first format or least significant bit
synchronous serial communications port allowing easy
(lsb) first format at up to 10Mhz.
interface to many industry standard microcontrollers and
microprocessors. The serial I/O is compatible with most
When configured for serial IO operation, most pins
synchronous transfer formats, including both the Motorola
from the AD9854/52 parallel port are inactive; some
6905/11 SPI and Intel 8051 SSR protocols. The interface
are used for the serial IO. Table x below describes pin
allows read/write access to all 12 registers that configure
requirements for serial IO.
Pin Number Pin Name Serial IO Description
1,2,3,4,5,6,7,8 D[7:0] The parallel data pins are not active, tie to VDD or GND
14,15,16 A[5:3] The parallel address pins A5, A4, A3 are not active, tie to VDD or GND
17 A2 IORESET
18 A1 SDO
19 A0 SDIO
20 I/O UD Update Clock. Same functionality for Serial Mode as Parallel Mode
21 WRB SCLK
22 RDB CSB  Chip Select
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AD9854 PRELIMINARY TECHNICAL DATA
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General Operation of the Serial Interface
The first eight SCLK rising edges of each communication
There are two phases to a communication cycle with the cycle are used to write the instruction byte into the
AD9854/52. Phase 1 is the instruction cycle, which is the AD9854/52. The remaining SCLK edges are for phase 2 of
writing of an instruction byte into the AD9854/52, the communication cycle. Phase 2 is the actual data
coincident with the first 8 SCLK rising edges. The transfer between the AD9854/52 and the system controller.
instruction byte provides the AD9854/52 serial port The number of data bytes transferred in Phase 2 of the
controller with information regarding the data transfer communication cycle is a function of the register address.
cycle, which is phase 2 of the communication cycle. The The AD9854/52 internal serial IO controller expects every
Phase 1 instruction byte defines whether the upcoming data byte of the register being accessed to be transferred. Table
transfer is read or write, and the register address in which below describes how many bytes must be transferred
to transfer data to/from.
Serial Register Number of Bytes
Address Register Name Transferred
0 Phase OffsetTuning Word Register#1 2 bytes
1 Phase OffsetTuning Word Register #2 2 bytes
2 Frequency Tuning Word #1 6 bytes
3 Frequency Tuning Word #2 6 bytes
4 Delta FrequencyRegister 6 bytes
5 Update Clock Rate Register 4 bytes
6 Ramp Rate Clock Register 3 bytes
7 Control Register 4 bytes
8 I Path Digital Multiplier Register 2 bytes
9 Q Path Digital Multiplier Register 2 bytes
A Shaped On-Off Keying Ramp Rate Register 2 bytes
B Q DAC Register 2 bytes
At the completion of any communication cycle, the
AD9854/52 serial port controller expects the next 8 rising All data input to the AD9854/52 is registered on the rising
SCLK edges to be the instruction byte of the next edge of SCLK. All data is driven out of the AD9854/52 on
communication cycle. In addition, an active high input on the falling edge of SCLK.
the IORESET pin immediately terminates the current
communication cycle. After IORESET returns low, the Figures 2 and 3 are useful in understanding the general
AD9854/52 serial port controller requires the next 8 rising operation of the AD9854/52 Serial Port.
SCLK edges to be the instruction byte of the next
communication cycle.
Figure 2. Using SDIO as a Read/Write Transfer
CS
INSTRUCTION
DATA BYTE 1 DATA BYTE 2 DATA BYTE 3
BYTE
SDIO
INSTRUCTION
DATA TRANSFER
CYCLE
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AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
Figure 3. Using SDIO as an Input, SDO as an Output
CS
INSTRUCTION
BYTE
SDIO
INSTRUCTION
CYCLE
DATA BYTE 1 DATA BYTE 2 DATA BYTE 3
SDO
DATA TRANSFER
Instruction Byte
The instruction byte contains the following information:
Instruction Byte Information
MSB D6 D5 D4 D3 D2 D1 LSB
__
R/W X X X A3 A2 A1 A0
__
R/W - Bit 7 of the instruction byte determines whether a SDIO - Serial Data I/O (Pin 19). Data is always written
read or write data transfer will occur after the instruction into the AD9854/52 on this pin. However, this pin can be
byte write. Logic high indicates read operation. Logic zero used as a bi-directional data line. The configuration of this
indicates a write operation. pin is controlled by bit 1 of register address 20h. The
default is logic zero, which configures the SDIO pin as bi-
Bits 6, 5 and 4 of the instruction byte are don t care. directional.
A3, A2, A1, A0  Bits 3, 2, 1, 0 of the instruction byte SDO - Serial Data Out (Pin 18). Data is read from this pin
determine which register is accessed during the data for protocols that use separate lines for transmitting and
transfer portion of the communications cycle. See Table 1 receiving data. In the case where the AD9854/52 operates
for register address details in a single bi-directional I/O mode, this pin does not output
data and is set to a high impedance state.
SYNC I/O  Synchronize IO Port (Pin 17). Synchronizes
Serial Interface Port Pin Description the I/O port state machines without affecting the
addressable registers contents. An active high input on
SCLK - Serial Clock (Pin21). The serial clock pin is used SYNC I/O pin causes the current communication cycle to
to synchronize data to and from the AD9854/52 and to run terminate. After SYNC I/O returns low (logic 0) another
the internal state machines. SCLK maximum frequency is communication cycle may begin, starting with the
10 MHz. instruction byte write.
CS - Chip Select (Pin 22). Active low input that allows
more than one device on the same serial communications
lines. The SDO and SDIO pins will go to a high
impedance state when this input is high. If driven high
during any communications cycle, that cycle is suspended
until CS is reactivated low. Chip Select can be tied low in
systems that maintain control of SCLK.
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AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
instruction cycle will properly write the first two data bytes
into the AD9854/52 but the next 8 rising SCLK edges are
interpreted as the next instruction byte, NOT the final byte
of the previous communication cycle.
Notes on Serial Port Operation
In the case where synchronization is lost between the
The AD9854/52 serial port configuration bits reside in bits system and the AD9854/52, the SYNC I/O pin provides a
1 and 0 of register address 7h. It is important to note that means to re-establish synchronization without re-
the configuration changes IMMEDIATELY upon writing initializing the entire chip. Asserting the SYNC I/O pin
this register. For multibyte transfers, writing this register (active high) resets the AD9854/52 serial port state
may occur during the middle of a communication cycle. machine, terminating the current IO operation and putting
Care must be taken compensate for this new configuration the device into a state in which the next 8 SCLK rising
for the remainder of the current communication cycle. edges are understood to be an instruction byte. The SYNC
IO pin must be de-asserted (low) before the next
The system must maintain synchronization with the instruction byte write can begin. Any information that had
AD9854/52 or the internal control logic will not be able to been written to the AD9854/52 registers during a valid
recognize further instructions. For example, if the system communication cycle prior to loss of synchronization will
sends the instruction to write a 2-byte register, then pulses remain intact.
the SCLK pin for a 3-byte register (24 additional SCLK
rising edges), communication synchronization is lost. In Timing Diagram for Data Write to AD9854/52
this case, the first 16 SCLK rising edges after the
tPRE
tSCLK
CS
tSCLKPWH tSCLKPWL
tDSU
SCLK
tDHLD
SDIO
1st Bit 2nd Bit
SYMBOL DEFINITION MIN
tPRE CS Set up Time 30 ns
tSCLK Period of Serial Data Clock 100 ns
tDSU Serial Data Set up Time 30 ns
tSCLKPWH Serial Data Clock Pulse Width High 40 ns
tSCLKPWL Serial Data Clock Pulse Width Low 40 ns
tDHLD Serial Data Hold Time 0 ns
7/16/99 REV.PRA
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AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
Timing Diagram for Read from AD9854/52
CS
SCLK
SDIO
1st Bit 2nd Bit
SDO
tDV
SYMBOL DEFINITION MAX
tDV Data Valid Time 30 ns
DATA WRITE CYCLE, SCLK IDLE HIGH
IR WRITE PHASE DATA TRANSFER - TWO BYTE WRITE
CS
SCLK
I0 I1 I2 I3 I4 I5 I6 I7 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15
SDIO
7/16/99 REV.PRA
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AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
Data read cycle, 3-wire configuration, SCLK IDLE Low
IR WRITE PHASE DATA TRANSFER - TWO BYTE READ
CS
SCLK
I0 I1 I2 I3 I4 I5 I6 I7
SDIO
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15
SDO
MSB/LSB Transfers This transfer of data can occur automatically, with
frequency of updates programmable by the user, or can
The AD9854/52 serial port can support both most occur completely under user control.
significant bit (MSB) first or least significant bit (LSB)
first data formats. This functionality is controlled by the Complete user control, referred to as external update mode,
REG0<6> bit. When REG0<6> is set active high, the allows the user to drive the UPDATE_CLK signal from
AD9854/52 serial port is in LSB first format. REG0<6> their ASIC or DSP. The AD9854/52 UPDATE_CLK pin
defaults low, to the MSB first format. The instruction byte is configured as an input in external update mode. A rising
must be written in the format indicated by REG0<6>. That edge on UPDATE_CLK indicates to the AD9854/52 that
is, if the AD9854/52 is in LSB first mode, the instruction the contents of the buffer memory is to be transferred to the
byte must be written from least significant bit to most register bank. The design uses an edge detector to signal
significant bit. the AD9854/52 to transfer data which allows a very small
minimum high pulse width requirement (two system clock
Multi-byte data transfers in MSB format can be completed periods). Its important to note that if the user keeps
by writing an instruction byte which includes the register UPDATE_CLK high, the AD9854/52 will NOT
address of the most significant byte. In MSB first mode, continuously update the register bank.
the serial port internal byte address generator decrements
for each byte required of the multi-byte communication Internal update mode, in which the AD9854/52 transfers
cycle. Multi-byte data transfers in LSB first format can be data from the buffer memory to the register bank
completed by writing an instruction byte which includes automatically, configures the AD9854/52 UPDATE_CLK
the register address of the least significant byte. In LSB pin as an output. The AD9854/52 generates a high pulse
first mode, the serial port internal byte address generator on UPDATE_CLK pin to signal the user that the buffer
increments for each byte required of the multi-byte memory has just been transferred to the register bank. The
communication cycle. minimum high pulse width is designed to be 8 system
clock cycles (min). The UPDATE_CLK signal can be used
Update Clock Operation as an interrupt within the system. Its important to note that
as an output UPDATE_CLK pin will not have anything
Programming the AD9854/52 is asynchronous to the approaching a 50/50 duty cycle for slower update rates.
system clock with all data being stored in a buffer memory
that does not immediately affect the part operation. The Programming the Update Clock register for values less
buffer memory is transferred to the register bank than 5 will cause the UPDATE_CLOCK pin to remain
synchronous to system clock. The register bank high. The update clock functionality still works, its just
information affects part operation. that the user cannot use the signal as an indication that
data is transferring. This is an affect of the minimum high
pulse time when UPDATE_CLK is an output.
7/16/99 REV.PRA
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AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
will be forced to DC, effectively powering down the digital
For internal update clock operation, the rate which the section. The REFCLK input will still be seen by the PLL
updates occur is programmed into the update clock and the PLL will continue to output the higher frequency.
register. The update clock register is 32 bits and the value
written into the register corresponds to HALF the number PLL functions:
of clock cycles between updates. That is, if a value of
00_00_00_0a (hex), is written into the update clock Seven Control register bits, located in the Control
register the rising edge of the UPDATE_CLOCK pin will Register[22:16] positions, relate to the PLL.
occur every 20 cycles (0a hex equals 10 decimal).
CR[23] is open
Control Register
CR[22] is the PLL range bit. The PLL range bit controls
the VCO gain. The power up state of the PLL range bit is
The Control Register is located in the shaded portion of the
logic 1, higher gain for high frequencies.
Register Layout table at address 1D through 20 hex. It is
composed of 32 bits. Bit 31 is located at the top left
CR[21] is the bypass PLL bit, active high. When active the
position and bit 0 is located in the lower right position of
PLL is powered down and the REFCLK input is used to
the shaded table portion. The register has been sub-
drive the system clock signal. The power up state of the
divided below to make it easier to locate the text associated
bypass PLL bit is logic 1, PLL bypassed.
with specific control categories.
CR[20:16] bits are the PLL multiplier factor. These bits are
Power down functions:
the REFCLK multiplication factor unless the bypass PLL
bit is set. The PLL multiplier valid range is from 4 to 20,
Four bits are available to power down the AD9854/52.
inclusive.
Each bit is active high, that is, they default low and a logic
1 causes the power down function to be working, The four
Other operational functions:
bits all reside in the same control byte such that one IO
write cycle can complete a full power down by writing all
CR[15] is the clear accumulator 1 bit. This bit has a one
four bits true simultaneously. The four bits are located in
shot type function. When written active, logic one, a clear
Control Register[28, 26:24] and are described below. The
accumulator 1 signal is sent to the DDS logic, resetting the
default state for these bits is logic zero, inactive.
accumulator value to zero. The bit is then automatically
reset but the buffer memory is not reset. This bit allows the
CR[31:29] are open
user to easily create a saw wave output with very little (or
no) user input required. This bit is intended for chirp mode
CR[28] is the comparator power down bit. When set (logic
only but there is no logic to suppress its functionality in
1), this signal indicates to the comparator that a power
other modes.
down mode is active. This bit is an output of the digital
section and is an input to the analog section.
CR[14] is the clear accumulators bit. This bit, active high,
holds both the accumulator 1 and accumulator 2 values at
CR[27] must always be written to logic zero. Writing this
zero for as long as the bit is active. This allows the DDS
bit to logic one causes the AD9854/52 to stop working
phase to be initialized via the IO port.
until a master reset is applied.
CR[13] is the triangle bit. When this bit is set the
CR[26] is the Q DAC power down bit. When set (logic 1),
AD9854/52 will automatically perform a continuous
this signal indicates to the Q DAC a power down mode is
frequency sweep from the mark to space frequencies and
active. This bit is an out of the digital section and is an
back. The effect is a triangular frequency sweep. When this
input to the analog section.
bit is set, the operating mode must be set to ramped fsk.
CR[25] is the full DAC power down bit. When set (logic
CR[12] is the source Q DAC bit on the AD9854 only.
1), this signal indicates to both the I and Q dacs as well as
When set, the Q path DAC accepts data from the QDAC
the reference that a power down mode is active. This bit is
Register. For the AD9852, this bit does not require a logic
an out of the digital section and is an input to the analog
one as the only data available to the Q path DAC is from
section.
the QDAC Register.
CR[24] is the digital power down bit. When set (logic 1),
this signal indicates to the digital section that a power
down mode is active. Within the digital section, the clocks
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AD9854 PRELIMINARY TECHNICAL DATA
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CR[5] is the output amplitude enable bit. When set the
output ramping function is enabled and is performed in
CR[11:9] are the three bits that describe the five operating accordance with the CR[4] bit requirements.
modes of the AD9854/52:
0h = single tone mode
1h = fsk mode CR[4] is the internal/external output ramp control bit.
2h = ramped fsk mode When set, logic 1, the output ramp factor will be internally
3h = chirp mode generated and applied to both the I and Q paths, When
4h = psk mode clear, the output ramping function is externally controlled
by the user and the ramp factor is the I and Q output ramp
CR[8] is the internal update active bit. When this bit is set factor register values. Defaults low external ramp factors
to logic 1, the UPDATE_CLOCK pin is an output and the used. The two registers that are the ramp factors also
AD9854/52 generates the UPDATE_CLK signal. When default low such that the output is off at power up and until
logic 0, external update_clock functionality is performed, the device is programmed by the user.
the UPDATE_CLK pin is configured as an input.
CR[3:2] are open.
CR[7] is open
CR[1] is the serial port msb/lsb first bit. Defaults low, msb
CR[6] is the bypass the inverse sinc filter bit. When set, first.
the data from the DDS block goes directly to the output
ramp logic and the clock to the inverse sinc filter is CR[0] is the serial port SDO active bit. Defaults low,
stopped. Default is clear, filter enabled. inactive.
7/16/99 REV.PRA
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