SiSoftware Sandra Q & A - Memory Detection








SiSoftware Sandra - The Diagnostic Tool, Q & A - Memory Detection

This document provides some frequently asked questions about Sandra. Please read the Help File as well!





Q: What does the PCx-xxx-xxx marking displayed by Sandra mean?
A: There are many conventions:


PC66/100 SDRAM Intel Specification - Version 1.0 to 1.2:

PCx-abc-defm (e.g. PC100-322-622R) where:
x - Speed rating (MHz). Memory bus speed should be equal/lower.
a - CAS latency (CL cycles). Lower the better (faster), but more expensive.
b - RAS to CAS delay (tRCD cycles). Lower the better.
c - Row precharge (tRP cycles). Lower the better.
d - Read data access time (tAC ns). Lower the better.
e - SPD chip revision. 2 corresponds to SPD 1.2.
f - Design revision. 2 corresponds to Rev 1.2.
m - R for registered DIMMS. 256MB and bigger modules need to be registered.



PC100/133+ SDRAM Extended Intel Specification - Version 1.2b+:

PCx-abc-ddeefm (e.g. PC100-322-54122R) where:
x - Speed rating (MHz). Memory bus speed should be equal/lower.
a - CAS latency (CL cycles). Lower the better (faster), but more expensive.
b - RAS to CAS delay (tRCD cycles). Lower the better.
c - Row precharge (tRP cycles). Lower the better.
dd - Read data access time (tAC ns). 54 corresponds to 5.4ns. Lower the better.
ee - SPD chip revision. 12 corresponds to SPD 1.2.
f - Design revision. The current is 2 corresponding to Rev 1.2.
m - R for registered DIMMS. 256MB and bigger modules need to be registered.



PC133+ H/E/VC/SDRAM IBM/VIA/Micron/NEC Specification - Version 2.0:

PCxm-abc-dde (e.g. PC133U-222-452, PC133R-333-542)
x - Speed rating (MHz). Memory bus speed should be equal/lower.
m - Module Type (R = Registered, U = Unbuffered).
a - CAS latency (CL cycles). Lower the better (faster), but more expensive.
b - RAS to CAS delay (tRCD cycles). Lower the better.
c - Row precharge (tRP cycles). Lower the better.
dd - Read data access time (tAC ns). 54 corresponds to 5.4ns. Lower the better.
e - SPD chip revision. 2 corresponds to SPD 2.0.



PC1600+ DDR SDRAM Micron/Samsung/Hyundai Specification - Version 1.0:

PCxm-aabc-dde (e.g. PC2100R-2533-750)
x - Memory bandwidth (MB/s). Memory bus speed should be 1/16 of this or lower.
m - Module Type (R = Registered, U = Unbuffered).
aa - CAS latency (CL cycles). Lower the better (faster), but more expensive.
b - RAS to CAS delay (tRCD cycles). Lower the better.
c - Row precharge (tRP cycles). Lower the better.
dd - Read data access time (tAC ns). 54 corresponds to 5.4ns. Lower the better.
e - SPD chip revision. 0 corresponds to SPD 1.0.



PC600+ RDRAM Rambus Specification - Version 1.0:

xMB/a b c PCd-e (e.g. 256MB/16 ECC PC800-45)
x - Module size in Mbytes on the module.
a - Number of RDRAM devices on the module.
b - Error correcting support (e.g. ECC)
c - Reserved.
d - Speed (Mega data transfers per second, Mt/s). Memory bus speed should be 1/2 of this or lower.
e - Response time (ns).




Q: What is this PCxxxx marking for DDR SDRAM?
A: The marking denotes the bandwidth of the memory in MB/s. The actual frequencies used are as follows:


PC1600 (DDR200) - 2x 100MHz
PC2100 (DDR266) - 2x 133MHz
PC2400 (DDR300) - 2x 150MHz (unofficial)
PC2700 (DDR333) - 2x 166MHz
PC3200 (DDR400) - 2x 200MHz



Q: What is this PCxxxx marking for RDRAM?
A: The marking denotes the transfer rate of the memory in Mt/s. The actual frequencies used are as follows:


PC600 - 2x 300MHz
PC700 - 2x 350MHz (stop-gap)
PC800 - 2x 400MHz
PC1066 - 2x 533MHz



Q: What does the a-b-b-bR c-d-d-dW e-f-gCL marking for SDRAM/DDR mean?
A: SDRAM/DDR specification:


a - read page hit clocks for first item
b - read page hit clocks for follow-up items
c - write page hit clocks for first item
d - write page hit clocks for follow-up items
e - CL (CAS latency)
f - SDRAM tRCD (RAS to CAS delay)
g - SDRAM tRP (RAS precharge)



Q: What does the a-b-b-bR c-d-d-dW e/fCL marking for RDRAM mean?
A: SDRAM/DDR specification:


a - read page hit clocks for first item
b - read page hit clocks for follow-up items
c - write page hit clocks for first item
d - write page hit clocks for follow-up items
e - RDRAM tRCD (Row to Column delay)
f - RDRAM tCAC (Channel to Channel delay)



Q: What does the Ax(BMxC) marking displayed by Sandra in addition to the above marking mean?
A: This marking on modules, e.g. 16x(8Mx8), and shows the device arrangement on the module, where:


A - number of chips on module
B - size of chip in Mbit
C - data width of chip in bits



Q: What are the typical ratings of a CL3 PC133 SDRAM unbuffered module?
A: A PC133 (3xx) unbuffered module may have the following CL settings:


CL1 - up to ~66MHz (most chipsets only support CL2 or higher)
CL2 - up to ~100MHz
CL3 - up to 133MHz



Q: What are the typical ratings of a CL3 PC100 SDRAM unbuffered module?
A: A PC100 (3xx) unbuffered module may have the following CL settings:


CL2 - up to ~66MHz
CL3 - up to 100MHz



Q: My PC133+ VC-SDRAM is detected as SDRAM!
Q: My PC16000+ DDR SDRAM is detected as PC133 SDRAM!
Q: My PC133+ H/ESDRAM is detected as SDRAM!
Q: My RDRAM is not detected!
A: Update to Sandra 6.53 or later.


Q: How is H/ESDRAM different from SDRAM?
A: In terms of latencies H/ESDRAM can run at CL2 (222) while SDRAM at CL3 (333) at higher speeds. However, SDRAM is catching up.


Q: How is DDR-SDRAM different from SDRAM?
A: DDR SDRAM is double pumped (similar to 2x AGP) and thus can transfer more data in the same time as SDRAM. It should, therefore, be quite a bit faster.


Q: Is VC-SDRAM different from SDRAM?
Q: Is RDRAM faster than H/E/VC/SDRAM?
A: This is beyond the scope of this document. Check reviews for benchmarks.


Q: My CL3 Registered SDRAM is detected as CL4! CL4 does not exist!
A: Registered SDRAM have a one clock CL penalty due to the on-board buffering, i.e. CL2 becomes CL3 and CL3 becomes CL4. In buffered-only mode this penalty does not apply.


Q: The response time for RDRAM (e.g. PC800-45) is totally wrong!
A: Remember this is the worst-case rating thus it may be higher than rated to make sure the memory works in all cases! Thus, a -40ns module may be rated as -45 just to be safe or for compatibility. Then again, the SPD information may be wrong - it happens!


Q: Sandra detects the wrong manufacturer name/serial number/version for my memory module!
Q: Sandra does not display a manufacturer name for my memory module!
Q: Sandra does not display a model name or serial number for my memory module!
A: First check with another SPD module detector, e.g. DIMM_ID or our own SPDINFO. It is very likely that you will get the same information. Unfortunately, some manufacturers do not set the SPD of the memory modules correctly so you will get incorrect information. There is nothing that can be done about this. Please buy from a reputable supplier/manufacturer in the future!


Q: The memory access speed (e.g. SDRAM 70ns) is totally wrong!
A: Make sure the system BIOS supports SMBIOS/DMI 2.2 or later. If not, SDRAM speeds are reported w.r.t. FPM/EDO speeds since earlier SMBIOS/DMI interfaces cannot represent SDRAM speeds. This way 80/70ns -> PC66, 60/50ns -> PC100. This is NOT a bug, the value is reported verbatim. However, we've deveoped a mapping for such BIOSes - please update to Sandra 5.00 or later.


Q: Sandra says my PC100 SDRAM is PC125! PC125 does not exist!
A: Update to Sandra 7.00 or later.


Q: I get SPD information only the 1st time I run the module, but not afterwards!
A: Right-click module Mainboard Information, choose Options and uncheck Include Programable Clock Generator Information. The PLL IC may be locking up when read or it may be write-only.


Q: My PC100 SDRAM definitely has SPD but Sandra does not display any information!
A: SPD information is displayed only on systems that contain a supported i2c or SMBus that is also supported by Sandra. Check the compatibility document for more information. Some mainboards/BIOS do not set/enable the i2c or SMBus correctly - you may need a BIOS upgrade to ensure correct operation. Update to the latest version of Sandra.


Q: Sandra does not detect ECC but my memory is ECC!
A: Check that ECC/parity is enabled in the BIOS. Update to Sandra 5.00 or later if you're using an earlier version.


Q: Sandra says my SPD has incorrect checksum. What does that mean?
A: It means that either the SMBus/i2c controller is faulty or the board has some incorrect settings. This sometimes happens with non-Intel controllers. Alternatively, the SPD on the memory module has been programmed incorrectly. This may affect the way the board configures itself based on the SPD.


Q: My SDRAM has SPD 1.0 or 1.1 rather than the latest 1.2. Is this a problem?
A: Not as far as Sandra is concerned. Older SPD versions are still supported. However, the actual timings identified by the BIOS may be different if the BIOS does not support older versions.




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