E365 Theory of Operation
Service Manual
Compal Communications, Inc.
Å‚% Baseband function Descriptions
1. Introduction
Baby Garnet use TI s chipset (Calypso c035 and IOTA) as base-band
solution. Calypso c035 is a GSM digital base-band logic included
microprocessor , DSP , and peripheral. IOTA is GSM analog/codec solution.
It contains the base-band codec, voice-band codec, several voltage
regulators and SIM level shifter etc. The baby garnet add some features such
as digital camera , photo sensor , TFT display , sixteen tone melody etc.
2. Base-band block
TFT
Color
Display RF- Base_Band Interface ( RIF )
(BBC, APC, AFC,ADAC)
32.768kHz
BACKUP
BATTERY
Tx & Rx I/Q
VBACKUP
TPU PARALLEL
32.768kHz
13MHz
13MHz
Miscellaneous
SIM
U1
Base band Interface
UART_IRDA
Regulator
UART_MODERN & Shifter
GSM/DCS Baseband and Vice A/D and
o
ARM SERIAL PORT
U15
D/A RF Interface Circuit With Power
KBR
Supply Management
Monitoring
KEYPAD
TPU SERIAL
Digital baseband processor
ADC
KBC
M
ATRIX
(MADC)
Power Management
JTAG(TAP)
PWL
KEYPAD
V
oice Band Interface
BACKLIGHT
VIBRATOR
I/O
SIM interface Interface
LCD BACKLIGHT
M
IC
VCC4
MAIN
BATTERY
Charging function
EARN
128M bits FLASH
U6
EARP
16M bits SRAN
U7
Melody
ADPA VCHG
TOR IN
PHONE
IC
DIGITAL CAMERA
(DC Power Input)
JACK
Mlody
e
Speaker
3. Theory
3.1 CALYPSO
Calypso is a chip implement the digital base-band processes of a GSM/GPRS
mobile phone. The chip combines a DSP sub-chip (LEAD2 CPU) with its
program and data memories, a micro-controller core with emulation
facilities(ARMTDMIE), internal 8Kb of boot ROM memory , 4M bit SRAM
memory , a clock squarer cell, several compiled single-port or 2 ports RAM and
CMOS gates.
Ncs2
NCS1
DAC
NCS0
NCS4
DATA BUS
ADDRESS
BUS
NCS3
uWIRE
SCS0
n
NCS1
AUXI
HSO
3.1.1 Real Time Clock (RTC)
3.1.2 Pulse Width Tones (PWT)
The PWT generates a modulated frequency signal for the external buzzer.
Frequency is programmable between 349Hz and 5276Hz with 12 half tone
frequencies per octave.
3.1.3 Pulse Width Light (PWL)
The PWL allows the control of the backlight of LCD and keypad by
employing a 4096bit random sequence. The block used a switchable clock of
32kHz .
3.1.4 Modem-Uart
3.1.5 I2c master serial interface (I2C)
3.1.6 General purposes I/O (GPIO)
Calypso provides 16 GPIOs in read or write mode by internal registers. In
Baby garnet we use 9 of them as follows.
GPIO PIN Used As.. Description
IO0 / TPU_WAIT IO0 DTR_MODEM Output ; RS232 DTR output signal
IO1 / TPU_IDLE IO1 disable
IO2 / IRQ4 IO2 LEDLCM_EN: LCM backlight=1 active
IO3 / SIM_RnW IO3 LCDA0 ; LCD Data or Command Control signal
IO4 / TSPDI IO4 nIRQ_melody:Melody IC interrupt, active=0
IO5 / SIM_PWCTRL SIM_PWCTRL For SIM Card Power Control
IO6 / BCLKX IO6 EAR_DETECT ; input
IO7 / NRESET_OUT nRESET_OUT ? LCD Peripherals reset
IO8 / MCUEN1 IO8 nIO_PWR_EN: Accessary power control : active=1
IO9 / MCSI_TXD MCSI_TXD DAI interface ,reserved; disable
IO10 / MCSI_RXD IO10 COMS_LDO_EN ; active=1
IO11 / MCSI_CLK IO11 COMS_ASK ; input
IO12/ MCSI_FSYNCH IO12 IO_PWR_EN: Accessary power control : active=1
IO13 / MCUEN2 IO13 LCD_ID; input
IO14 / nBHE nBHE nBHE
IO15 / nBLE nBLE nBLE
3.1.7 Serial Port Interface (SPI)
The SPI is a full-duplex serial port configurable from 1 to 32 bits and
provides 3 enable signals programmable either as positive or negative edge or
level sensitive. We use SPI to control the melody IC.
nSCS0 :Chip select 0
SDO: Data out.
SDI: Data in
SCLK: Serial clock
3.1.8 Memory interface and internal static RAM
A 4Mbit SRAM is embedded on the die and memory mapped on the
chip-select CS6 of the memory interface.
3.1.9 SIM interface
3.1.10 JTAG
3.1.11 Time Serial Port (TSP)
3.1.12 TSP Parallel interface (ACT)
Herculse Pin no Pin Name Used As.. Description/Net
M12 TSPACT0 TP5 X
M14 TSPACT1 TSPACT1 PAENA (Chip enable for
Power Amp IC)
L12 TSPACT2 TSPACT2 PDNB (RF IC power down
control)
L13 TSPACT3 TSPACT3 X
J10 TSPACT4 TSPACT4 X
K11 TSPACT5 TSPACT5 X
K13 TSPACT6/nCS6 TSPACT6 TRENA (T/R switch
enable)
K12 TSPACT7/CLKX_SPI NC X
K14 TSPACT8/Nmreq TSPACT8 GSM_TXEN (Used both
within the RF switch and
the Power Amp to select the
GSM Frequency Band)
J11 TSPACT9/MAS1 TSPACT9 X
J12 TSPACT10/nWAIT NC X
J13 TSPACT11/MCLK NC X
3.1.13 Radio Interface (RIF)
3.2 IOTA
IOTA is an analog base-band device which a digital base-band device is
part of a TI DSP solution intended for digital cellular telephone applications.
This includes the GSM 900, DCS 1800, PCS 1900 standards.
IOTA includes a complete set of base-band functions that perform the
interface and processing of the following voice signals, the base-band in
phase(I) and quadrature (Q) signals. Which support both the single-slot and
multislot modes. IOTA also includes associated auxiliary RF control features
supply voltage regulation, battery charging controls , and switch on/off
system analysis.
 IOTA interfaces with the CALYPSO through a digital base-band port and a
voicebad serial port. The signal ports communicate with a DSP core. A
microcontroller serial port communicates with the microcontoller core and a
time serial port communicates with the time processing unit for real-time
control.
3.2.1 Base-band Codec (BBC)
3.2.2 Automatic Frequency Control ( AFC)
3.2.3 Automatic Power Control ( APC)
3.2.4 Time serial port (TSP)
3.2.5 Voice band Codec (VBC)
3.2.6 SIM card shifters (SIMS)
3.2.7 Voltage Regulation (VREG)
Several low-dropout(LDO) linear voltage regulation supply power to
internal analog and digital circuits to the DBB processor and to external
memory
a. VRDBB is a programmable regulator that generates the supply
voltages( 1.8V , 1.5V , and 1.3V) for the core of the CALYPSO. In baby
garnet , it is programmed to 1.5V. During all modes, the main battery directly
supplies VRDBB.
b. VRIO is a programmable regulator that generates the supply voltages(2.8V)
for I/Os of the CALYPSO and IOTA. During all modes, the main battery
directly supplies VRIO.
c. VRMEM is a programmable regulator that generates the supply
voltages(2.8V and 1.8V) for external memories (typically flash memories)
and CALYPSO memory interface I/Os. In baby garnet , it is programmed to
2.8V. During all modes, the main battery directly supplies VRMEM.
d. VRRAM is a programmable regulator that generates the supply
voltages(2.8V and 1.8V) for external memories (typically SRAM memories)
and CALYPSO memory interface I/Os. In baby garnet , it is programmed to
2.8V. During all modes, the main battery directly supplies VRRAM.
e. VRABB is a programmable regulator that generates the supply voltages
(2.8V ) for the analog functions of the IOTA. During all modes, the main
battery directly supplies VRRAM.
f. VRSIM is a programmable regulator that generates the supply voltages
(2.9V and 1.8V )for SIM card and SIM card drivers. During all modes, the
main battery directly supplies VRRAM.
g. VRRTC is programmable regulator that generates the supply voltages
(1.3V, 1.5V ,and 1.8V) for CALYPSO s backup RTC. It is switched on the
main or backup battery, depending on the phone state.
3.2.8 Base-band Serial Port (BSP)
3.2.9 Battery charger interface (BCI)
3.2.10 Monitoring ADC (MADC)
3.2.11 Reference Voltage / Power on control (VRPC)
3.2.12 Internal bus and interrupt controller( IBIC)
3.3power supply circuit
IO TA VRSIM 1.8V/2.9V SIM card
GSM/DCS Baseband VRSAM 2.8V
and Voice A/D and VRMEM 2.8V
CALYPSO
D/A RF Interface VRDBB 1.5V
Digital
C ircuit With Pow er VRIO 2.8V
baseband
Supply Management VRABB 2.8V
processor
VRRTC 1.5V
External 1.8v Flash core 128MBit
150mA Flash I/O
External 2.8v
SRAM 16MBit
300mA
LCM
Light sensor
External 2.5v Backend core
150mA I/O
External 3.3v
Cmos sensor
150mA
The phone is mainly supplied from the main battery. The main battery supply
the two parts : RF block, base-band block.
The input power to IOTA is divided into 4 blocks.
VCRAM: to provide power for VRRAM
VCMEM: to provide power for VRMEM
VCIO1,VCIO2: to provide power for VRIO and VRSIM
VCABB: to provide power for VRABB
VCDBB: to provide power for VRDBB
The IOTA provides seven low drop-out voltage regulators.
VRRAM:2.8V@50mA, to supply SRAM
VRMEM:2.8V@60mA, to supply flash I/O and CALYPSO memory interface
I/Os.
VRDBB;1.5V@120mA. to supply the core of the CALYPSO
VRIO:2.8V@100mA, to supply I/Os of the CALYPSO and IOTA
VRABB;2.8V@50mA to supply the analog functions of the IOTA
VRRTC:1.5V@10uA, to supply the CALYPSO s backup RTC.
VRSIM:1.8V or 2.9V@10mA , to supply the SIM.
3.4 memory circuit
CALYPSO FLASH
Data bus
Address bus
NCS0
NCS3 /CE
NFOE /OE
FDP /RST
RNW /WE
NCS1
NBHE
SRAM
NBLE
/CE
/OE
/HB
/LB
/WE
Description
Flash is a 128Mbit device, supported by external LDO and VRMEM. The
access time of flash is 90ns. The total 128Mbit are divided into two sections:
112Mbit is used for software program code and 16Mbit is used for user s data.
SRAM is a 16Mbit device supported by VRRAM. The access time of flash is
70ns.
3.5 display circuit
VBAT VBAT
VDDS-MIF_2.8V VDDS-MIF_2.8V
C79 C80 C77
C78 C720 C76 C81
C82 C83 C74 C85
C722
100PF 0402
D[0..15]
Down
J5
30
LED_Cathode
Cathode
29
LED_Anode Anode
1 8 28
D13
2 7 R68 27
D14
3 6 200 0408 26
D15
4 5 25
nRESET /RESET
24
VDDS-MIF_2.8V VCC
23
VCC
1 8 22
D12
2 7 R69 21
D11
3 6 200 0408 20
D10
4 5 19
D9
1 8 18
D8
2 7 R70 17
D7
3 6 200 0408 16
D6
4 5 15
D5
1 8 14
D4
2 7 R71 13
D3
3 6 200 0408 12
D2
4 5 11
D1
10
D0
9
R75 200 0402
LCD_RD /RD
8
RNW /WR
R76 200 0402 7
LCDA0 RS
6
nCS2 /CS
5
R77 100 0402
GND
4
GND
3
LCD_ID LCD_ID
2
NC
1
NC
CON30 Up
C84 C87 C88 C721 C89 C90 C91 C92 C93 C94
DGND
DGND DGND DGND DGND DGND DGND
DGND DGND DGND DGND
Description
The display area is a 128*160 resolution LCD module. The power of LCDM
is supplied from external LDO (2.8V). It is controlled by CALYPSO via parallel
interface : data bus and chip select .The Ncs2 is low active to enable the LCDM
data bus. Resistance and capacitance is used for radiation suppression.
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
3.6vibrater circuit
VBAT
No. G3240010
F1
SGM20F1E104-2A 2012
4 3
G G
DGND DGND
BQ1
1 2 2
2SC5592 SC59
DAC
R42
R43
33 0402
10K 0402
0.95mm
M1
MOTOR 4.0*8.8-1.5V-KHN4NZ1D
DGND
D4
3930408801W
1SS400 SC79
DGND
DAC of the IOTA is used to control the vibrational level. D4 is used to
protection the vibrater. In the 3.8V, the DAC output voltage is 1.9V and drain
current is around 90mA .
3.7 speaker circuit
1
I/O2
I/O1
2
2
1
1
3
Description
The Melody IC MA2 works as follows.
First, the CPU (G2) fetch melody data from flash and fed them into MA2
by serial interface. After receiving these data, MA2 will start decode its content
and start its sequencer for processing. After completing this process, the MA2
will generate the tones we want according to the melody data. Then, these data
will run through MA2 s DAC, which inside it. Then, the converted signal is fed
into an equalizer, and then followed by an amplifier, which they are inside MA2.
Then this signal will be outputted from SPOUT1 and SPOUT2 to drive the
speaker.
Here, the R44 and R46 provide optimal gain control for MA2. To ensure
the speaker not to be overdrove.
3.8 DSC (Digital Still Camera) function block diagram and circuit
description
3.8.1 Function block diagram
CF
SCCB
Backend
Host LCM
(a) (d)
(W99688)
(Calypso 035) Toppoly
CMOS
SENSOR
(b) (c)
Memory
interface
SRAM
Interface
Data path
Control path
Fig. 1 Imbedded DSC block diagram
Imbedded DSC included two portions, one is front-end sensor module and
another is backend DSP chip. There are including two interfaces which are
SCCB (Serial Camera Control Bus) and CF (Compact Flash). The function
block diagram is shown in Fig.1. The SCCB is used in sensor to backend
interface, and the backend to host (G2) is used CF interface.
3.8.1. Sensor to Backend Interface
CMOS SENSOR
RESET
PWDN
SIO_C
SIO_D
Backend
XCLK
PCLK
(W99688)
VSYNC
HSYNC
DATA BUS
RESET: (default 0) chip reset with active high
PWDN: (default 0) power down mode selection
 0 normal mode,  1 power down mode
SIO_C: SCCB (Single Chip Camera Bridge) serial interface clock input
SIO_D: SCCB (Single Chip Camera Bridge) serial interface data input and
output
XCLK: Clock input
PCLK: Pixel clock output
VSYNC: Vertical sync output
HSYNC: Horizontal sync output
Data Bus: 8 bits
3.8.1.2 Backend to Sensor
Interface
A0..A3: Compact Flash: Address-0~3 for command
D15..D0: Data bus connect to Host
RD#: Read data or command
WR#: Write data or command
CS#: Chip select
3.8.2 Circuit description
3.8.2.1 Main circuit
ROW4
DGND
S22
COL4
DD[0..7]
CAMERA
CC8
TP
33nF 0402 D33V
TP27
C726
DGND
D25V
100nF 0402
FPC 0.5mm PITCH
CMOS SENSOR MODULE I/F C725
100nF 0402
OV7645FB/TASC
DGND
RR23
J6
DD3 G9 K1
0 0402 NM(Tasc)
SD5 VSSI-2
J11 L3
VDDI-3 GND-7
1 DD4 G11 L2
GND SD6 VD3-7
2 DD5 K4 L1
HREF SD7 GND-6
3 DD6 F9 J1
VSYNC SD8 VD3-6
RR22
4 DD7 F11 H1
PWDN PWDN SD9 GND-5
5 E11 G1
PCLK 0 0402 (OV) GND-10 VDDI-1
6 F10 H2
AVDD S25V SPCLK VSSI-1
7 RR24 J4 G2
DVDD DD25V 0 0402 NM(Tasc) SVS U12 VD3-5
8 K3 F1
SIO_D SDA SHS P31 PWDN
R79
9 E10 F2
688CBM3
XCLK SCLK P30 TP25
10 H4 E1
SIO_C SCK 47 0402 SCK SCK USBVDD
11 DD0 E9 E2 1
TP26
Y0 SDA SDA DM T
12 DD1 D9 E3
TP29
SDO
Y1 R81 SDO DP 1
13 DD2 R80
RR16 D11 D1
T
Y2 VD3-9 USBVSS 1 TP
14 DD3 4.7K 0402 4.7K 0402 10K J3 D2
T
Y3 FWAIT# GND-4
15 K2 C1
TP
GND FCD# VD3-4
16 DD4 D10 B1 TP
Y4 FRST FRST GPIO15
17 DD5 A1 B11 C2
Y5 FA0 GPIO14
18 DD6 A2 D8 B2
Y6 FA1 GPIO13
19 DD7 A3 A11 D3
Y7 DD25V FA2 GPIO12
20 F3 A1 C96
RESET GND-D GPIO11
A[1..3] G3 C3 1u 0603
VD3-D GPIO10
B5 B3
GND-F RESET
K6 A2
CMOS_CON DD[0..7] VD3-F GND-3
RR20
SDO RR4
100K 0402
0 0402 NM(Tasc)
RR5
C?
10K 0402(OV) RR25
47nF 0402(Tasc)]
4.7k 0402 NM(Tacs)
DGND
DGND
DD25V
R80:
CLOSED TO
688 ASAP
DGND
D[0..7]
TP28
TP
D33V: Power supply for I/O pads +3.3 V
DD25V: Power supply for CMOS sensor digital part +2.5 V
S25V: Power supply for CMOS sensor analog part +2.5 V
D25V: Internal core logic power supply. +2.5 V.
AVDPP: Power supply for PLL analog 2.5V
AVSSP: Ground for PLL analog
FSRT: Compact flash: RESET/RESET# signal (High enable 2.8V)
Vsync & HREF relation:
DGND
DGND
DD2
DD1
DD0
D0
D1
D2
D3
D4
D5
D6
D7
CLK13M_DSC
AVSSP
AVDDP
RNW
nCS4
nFOE
T
G10
H8
H10
H11
J5
H9
J10
L11
K11
K10
J9
L10
J6
J8
K9
K8
J7
K7
L8
K5
L9
L7
L6
L5
L4
1
SD4
SD3
SD2
SD1
SD0
DVS
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
MD1
DHS
VD3-8
GPIO3
VSSI-3
GND-9
GND-8
DFULL
VDDI-2
DOCLK
DVALID
DGND
DGND
VD3-1
FIRQ/FSRB#/FWP
FIORD#/FSRE#/XCMD
FIOWR#/FSWE#/FCMD
FCE2#/FSCLE/XCLK
FCE1#/FSALE
FREG#/FSWP#/FCLK
GND-1
FD0/FDAT0
FD1/FDAT1
FD2/FDAT2
FD3/FDAT3
FD4/XDAT0
FD5/XDAT1
FD6/XDAT2
FD7/XDAT3
GPIO0
VD3-2
XIN
XOUT
GND-2
GPIO1
AVSSP
AVDDP
VD3-3
J2
B9
A9
B8
A8
B7
B6
A7
A6
A5
A4
B4
A3
C8
C9
H3
C7
C6
D4
C4
C5
A10
B10
C10
C11
1
T
DGND
The backend power on reset is 100ms that generated by C96 (1uF) and RR4
(100k ohms). The backend clock CLK13M_DSC is 13MHz (Vp-p 3.0V), and
XCLK is 24MHz ( Vp-p 3.35V) that is generated from backend to sensor. Then
sensor will base on XCLK to generate PCLK for image data clock that is
12MHz (Vp-p 2.3V).
3.8.2.2 DSC DC power
D25V
L6
AVDDP
100nH 0402
RR26
1SS400 SC-79(W99685)
L8
2.5V FOR OV7645FB DD25V
S25V
100nH 0402
U13
1 10
VBAT Vin VOUT2.5
2 9
EN1 VOUT3.0 D33V
3 8
EN2 NC
COMS_EN
C97
4 7
2.2uF/6V
C99
BYP NC
L7
5 6
C98
NC GND
AVSSP
1uF/6V
100nH 0402
C700
MIC2211-2.5/3.3BML
10nF 0402 DGND
DGND
DGND
DGND
DGND
CMOS_EN is used to control DSC power enable. It is high active (2.8V). L6,
L7 and L8 are formed low pass filter with C97 in order to suppress low
frequency noise.
RR26
0 0603
RR9
100K 0402 nm
100nF 0402
3.8.2.3 DSC system clock
D33V
RR14
10
U18
1
NC
C723 5
VCC
C724
100pF
2
0402
CLK13M_OUT
IN
DGND
10%
4
50V
CLK13M_DSC 100pF
OUT
3
NPO
X7R
GND
0402
10%
KIC7S04FU
50V
DGND
SOT23-5
RR15
1M
Add buffer to avoid CLK13M_OUT over load causing system hang.
3.8.3 Function flow chart
3.8.3.1 Preview:
Video Preview Path
RGB Data
W99688 Host LCM
1 2
1.CDM40 (Set Single Capture Mode)
2.CDM41 (Set Preview Size 128x96)
3.CDM42 (Get Preview Data)
Preview Data Source
SRAM
Data Memory
3.8.3.2 Capture:
Capture Image Path
Jpeg Data
W99688 Host LCM
1
1.CDM40 (Set Single Capture Mode)
2.CDM41 (Set Image Format 640x480)
3.CDM43 (Snapshot)
2
4.CDM2 (Get Jpeg Bitstream)
Preview Data Source
Flash
SRAM
3.8.3.3 Playback:
Data Memory
Play Picture Path
Jpeg Data
W99688 Host LCM
2
4
1.CDM40 (Set Playback Mode) RGB Data
2.CDM48 (Set Decode Size 640x480)
3.CDM44 (Send Jpeg Bitstream)
4.CDM45 (Decode Jpeg Bitstream)
1
4.CDM47 (Get Decode Image Data)
Preview Data Source
3
Flash ROM
Preview Data
Put Image
SRAM
Transformation
Data Memory
3.9 led circuit
keypad backlight
R2 R3 R4 R5
RS2N39 0404 RS2N39 0404 RS2N39 0404 RS2N39 0404
VBAT
C7
NM 47nF 0402
DGND
VR1
14V 0402
D2 D3 D4 D5 D6 D7 D8 D9
LED LED LED LED LED LED
LED LED
R64 0 0402 NM
LEDB
R65 1.5K 0402
2 BQ3
KeyLed_En
2SC5585 EMT3
R66
4.7 0402
R67
C73
33nF 0402 1K 0402
DGND
LCD module backlight
LED_Anode
D6
FL1
22uH
3 2
VBAT
CC1 RB551V-30
U11
0.22uF 0603
1 5
SW BIAS
2
DGND
GND
3 4
FB EN LEDLCM_EN
R36 R40
MP1523
CC2
LED_Cathode
1uF 0603
0 0402 0 0402 NM
RR1
56 0402
DGND
DGND
VDDS-MIF_2.8V
description
The baby garnet employ three LEDs for LCD module backlight and six LEDs
for keypad backlight. The keypad backlight is controlled by PWL (Pulse with
light). The LCD module backlight is controlled by GPIO of the CALYPSO. The
CALYPSO is used to enable BQ3 and U11. The total current of LCD backlight
LED s and keypad backlight LED s is about 70mA during all LED work.
DGND
R2
R2
R1
R1
R2
R2
R1
R1
R2
R2
R1
R1
R2
R2
R1
R1
3
2
4
1
3
2
4
1
3
2
4
1
3
2
4
1
1
3
3.10 audio circuit
Uplink:
Downlink:
Description
The acoustic circuit can be divided into two parts, Uplink and Downlink
path.
For the Uplink path, the analog signal, or Voice, is fed into IOTA (MICIP
and MICIN) by the microphone s differential input. This signal is then sampled
and transmitted into G2 DSP via the VSP (Voice-Band Serial Port) interface.
After being modulated, the signal goes through the uplink I/Q path to the RF
transceiver and then being transmitted by the antenna.
The microphone is biased by the IOTA MICBIAS pin (2.5V). Where the
bias circuit R58, R59, R60, R61 provide optimal operation point for the
microphone.
For the Downlink path, the signal is received from antenna. Then it is
down-converted to I/Q signal and then send into G2 DSP. After being
demodulated, the signal is then transmitted into IOTA via VSP interface. After
re-construct this signal, this signal is then amplified and drove the receiver.
3.11 charging circuit
3.11.1Function Block
Battery pack
Detect current
Detect voltage
3.11.2 function description
When the charging device is plugged in, the charging scheme for the Li-ion
battery is constant current first (MAX current is 400mA) then followed by
constant voltage charging. When battery voltage has been detected full, the BCI
of IOTA will be turned off till a Low voltage threshold has been detected. At
charger plug OUT, the charger status bit CHG_STS is driven from  1 to  0
and an interrupt of the INT2 type is generated making the uC aware of the
charging device unplug. When over-discharging (battery voltage is less than
3.2V), the BCI of the IOTA will be the pre-charge state (charging current equal
to 30mA). Until battery voltage bigger than 3.2V, it returns to normal charge.
When ICHG bigger than 1 A, the OCP (over current protection) will be enabled.
When the battery voltage is higher then 4.35V, the OVP (over voltage protection)
will be enabled.
OCP
OVP(2)
Charging Control
AC/DC
Adapter
(IOTA)
Micro control
3.12 Earphone block diagram and circuit description
3.12.1 Function block diagram
Send-End
Protect
Audio Jack EMI circuit key
circuit
controller
Power manager
(IOTA)
Host
Fig. 1 Earphone block diagram
The earphone circuit included audio jack, protect circuit, EMI circuit and
Send-End key controller. The all design based on external earphone which
characteristic is shown below.
3.12.1.1 Outward appearance:
Send-End key
MIC AUXO GND
CONNECT TO CELLPHONE
3.12.1.2 Impedance:
The status of send-end Relaxed Pressed
key
1.7k©
MIC TO GND OPEN
35© 35©
AUXO TO GND
Audio signal
Use row0 to
detect
3.12.2 Circuit description
R72
varistor 5.5V 0402
VRIO_2.8V
EAR_BIAS
VR12
NM 100 0402
R49
220K 0402
R52
R51 varistor 5.5V 0402
HSMICBIAS
J4
VR6
100 0402
EAR_DETECT
Jack
2.2K 0402
C56
C730
BQ4
10uF 0805
33pF 0402
DGND
DGND
2
DGND
B
EF1
PDTA144EE SC-75
5 1
Auxi2 O1 I1
2
GND
R53
4 3
O2 I2
4.7K 0402 (HSMICBIAS)
EMIF01-10005W5 SOT323-5L 10k 0402 (EAR_BIAS)
DGND
L3
varistor 5.5V 0402
HSO
VR11
100nH 0402
C57
varistor 5.5V 0402
10uF 0805
C59
VR13
33pF 0402
DGND
DGND
DGND
ROW0
Vmicbias(2.5V)
2 BQ2
HSMICIP
C58
22K DTC124EE EMT3
R54
1uF / 0603 22K
39K 0402
Auxi2
DGND
BQ4: It is used to avoid error function on earphone plug in/out.
J4: Audio jack
EF1: Filter audio and circuit noise.
BQ2: Send-end key detected. When BQ2 turned on, the send-end function
work.
3.12.2.1. EMI Filter including ESD protection
EF1
5 1
O1 I1
2
GND
4 3
O2 I2
EMIF01-10005W5 SOT323-5L
Rd=Rd1=Rd2=100©
Rd1 is the dynamic impedance between I1 and O1.
Rd2 is the dynamic impedance between I2 and O2.
47K
DGND
5
1
DGND
1
Mic
Mic2
AUXO
ADCID
4
3
2
C
E
3
3
1
DGND
47K
0.7MM
3.12.2.2. Digital transistors (built-in resistors)
BQ4
2
B
PDTA144EE SC-75
Vi(off) input-off voltage Viÿ-ð1.2V, (VO=0V)
Vi(on) input-on voltage Viÿ-ð1.6V, (VCE = 300 mV)
-ð
R1 (input resistor) =47k0Resistor ratio=1
ð,ð
3.12.2.3 Digital transistors (built-in resistors)
2 BQ2
22K DTC124EE EMT3
22K
Vi (off) input-off voltageÿ0.9V, (VO=0V)
Vi (on) input-on voltageÿ1.1V, (0.1VÿVCEÿ0.3V)
R1 (input resistor) =22k0Resistor ratio=1
ð,ð
We could base on EAR_DETECT, HSMIBIAS and ROW0 to function.
EAR_DETECT used to detect  earphone plugging and it is high active.
HSMIBIAS is high active that is used to switch internal path or external
earphone path. Send-end function is based on ROW0 which is low active. The
three signals high/low level are shown to below.
EAR_DETECT HSMIBIAS ROW0
High level (V) 2.8 2.5 2.8
Low level (V) 0 0 0
The function status is following below:
3.12.2.4 Status1:
Insert the headset plug when the phone holds over idle mode without the
headset plug in the jack.
EAR_DETECT HSMIBIAS ROW0
Status L L H
47K
3
1
1
C
E
3
47K
0.7MM
3.12.2.5 Status2:
Receive an incoming call and the phone rings
EAR_DETECT HSMIBIAS ROW0
Status L H H
3.12.2.6 Status3:
Press the send-end key to answer the call.
EAR_DETECT HSMIBIAS ROW0
Status L H H to L (falling
edge)
3.13sim circuit
VRSIM VCC/VPP
CALYPSO IOTA SIM
SOCKET
SIM_IO SIO3 SIO5 I/O
SIM_CLK SCLK3 SCLK5 CLK
SIM_RST SRST3 SRST5 RST
GND
DGND
Description
The IOTA SIM interface is composed by a dedicated LDO and I/O level
shifters. It is able to support 3V and 1.8V SIM cards.
SIM_IO: DATA
SIM_RST :Reset signal
SIM_CLK: Clock
For that reason correct enabling sequence is the following :
a. Selection of the SIM voltage and enable of the SIM LDO
b. Wait for the SIM LDO output voltage set up.
c. Enable SIM level shifter when SIMRSU=1.
3.14keypad circuit
S1
PWON
Power / End
DGND
ROW4 ROW3 ROW2 ROW1 ROW0
S2 S3 S4 S5 S6
Soft-KeyL * 7 4 1
COL3
S7
S8 S9 S10 S11
8
Menu 0 5 2
COL2
S12 S13 S14 S15 S16
C9
47nF 0402
DGND
Soft-KeyR # 9 6 3
COL1
S17 S18 S19 S20 S21
RIGHT LEFT down UP SEND
COL0
C1 C2 C3 C4 C5 C8
33nF 0402 NM 33nF 0402 33nF 0402 47nF 0402 10nF 0402 47nF 0402
DGND DGND DGND DGND DGND DGND
DGND
Description
3.14.1 The keypad is made of a 5Column * 5 Row matrixes.
3.14.2 The keypad matrix is as follows:
Function key Col 0 Col 1 Col 2 Col 3 Row 0 Row1 Row 2 Row 3 Row 4
No/PW S1 0
R
MEDIR S2 0 0
* S3 0 0
7 S4 0 0
4 S5 0 0
1 S6 0 0
MENU S7 0 0
0 S8 0 0
8 S9 0 0
5 S10 0 0
2 S11 0 0
STYLE S12 0 0
# S13 0 0
9 S14 0 0
6 S15 0 0
DGND
3 S16 0 0
RIGHT S17 0 0
LEFT S18 0 0
DOWN S19 0 0
UP S20 0 0
SEND S21 0 0
3.15 photo sensor circuit
VDDS-MIF_2.8V
Q1
LIGHTSENSER_EN
Photo-Transistor
R1
C6
10k
?nF 0402 NM
DGND
DGND
Description
The phototransistor is used to switch the backlight of keypad according to the
R1 voltage level. This saves energy and add to stand by time .We use analog
digital converter (ADC) to detect the voltage variation in the R1. The Q1 is a
phototransistor. The light affect the current variation. The lightsenser_en is from
the IOTA S ADC. So we know the voltage variation, and control the backlight
of keypad. If the brightness is too strong, we will turn off the LED of keypad.
Å‚% Radio Frequency function Descriptions
Top Side
Bot
tom Side
Receiver Block Diagram
Transmitter Block Diagram
Frequency Synthesizer Block Diagram
1.T/R Switch:
U101 is a front-end switch device for GSM/DCS. The below table shows the
three operating mode.
Mode
VC1 (pin2) VC2 (pin11)
L H
GSM TX
DCS TX H L
GSM/DCS RX
L L
These four control signals are generated from U103, which controlled by T/R
Switch.
2.Power Amplifier:
PA (U401) is control by signal PAENA, BS, and APC. The power controlloop is
a voltage sensor.
3.Transceiver:
U201 is the transceiver.
A. Receiver Operation
Received signals from the antenna are passed to the T/R switch U101.This T/R
switch contains a diplexer which filters the signal to the required receiver path
(E-GSM900 or GSM1800).Pin diode switches within U101 route the signal path
from the transmitter or to the receiver as required. Output signals from U101 are
then applied via the SAW filter F101 or F102 to the balanced Low Noise
Amplifiers (LNA) onboard U201.Output from LNAs are applied to a pair of
Gilbert Cell mixers within U201.An image-reject mixer downconverts the RF
signal to a 100kHz intermediate frequency (IF) with the RFLO from the U301
frequency synthesizer. The RFLO frequency is between 1737.8 to 1089.9MHz,
and is divided by to in the Si4200 (U201) for GSM 850 and E-GSM 900 modes.
The mixer output is amplified with an analog programmable gain amplifier
(PGA), which is controlled with the internal register. The quadrature IF signal is
digitized with high resolution A/D converters. The signal is then down
converted by a demodulator to I and Q. The Si4201 (U203) downconverts the
ADC output to baseband with a digital 100kHz quadrature LO signal.
B. Transmitter Operation
The transmitter chain converts differential IQ baseband signals to a suitable
format for transmission by a power amplifier. A quadrature mixer upconverts
the differential in-phase (TXIP, TXIN) and quadrature (TXQP, TXQN) signals
with the IFLO to generate a SSB IF signal which is filtered and used as the
reference input to the OPLL. The Si4133 (U301) generates the IFLO & RFLO
frequency.
4.Synthesizer:
U301 is a dual frequency synthesizer that performs IF and RF synthesis. Two
complete PLLs are integrated including VCOs, varactors, loop filters, reference
and VCO dividers, and phase detectors. Differential outputs for the IF and RF
PLLs are provided for direct connection to the Si4200 (U201) transceiver. The
RF PLL uses two multiplexed VCOs. The RF1 VCO is used for receive mode,
and RF2 VCO is used for transmit mode. The IF PLL is used only during
transmit mode and uses a single VCO.