HEAD_INT
N3
C14, D4, E12, H4, J10, K6, N12 V2
KBR0, KBR1, KBR2 H2, H3, H1
( Keyboard )
V3
B5, B9, B10, G12, K14, L11, N8
KBC0, KBC1, KBC2, KBC3 K1, J4, J3, J2
( CE ) MQSPI_CS1
U700
L8
BKLT_EN K2
( SPI_CLK ) MOSPI_CLK1
WHITE_CAP
J700
KEYPAD SPI M8
DP_EN E10 ( MAGIC SPI )
( SPI_DATA ) DX1
L6
HS_INT INTERFACE
FLIP CON.
DISPLAY M7
D7 - D0
VIB_EN K4
INTERFACE 7, 9, 10, 11, 13,
LED_RED M3
DATA BUS
M
14, 15, 17
LED_GRN M2
E
A0
LS1_IN E8 M
SIM
D6 O
LS2_IN 19
ADDRESS BUS
INTER
R
LS3_TX E1
Y
FACE
LS3_RX E6
3, 4, 6, 12, 16
( Flip Con. ) R_W V2
A1
CLK_SELCT C3 V2
RESET 22
I
TX_EN D2
C1 D6, E1 V2
CPU
N
A4, A6, F6
CE2 18
R_W
DM_CS
F5
E2
T C9 B2
U702
CTM RESET DP_EN 21
CE3
TX_KEY E1 U701
E4
E
B4
E9 A1
SRAM
BKLT+
E2 MODULE 1
RX_EN E3 R
R_W
EPROM
D11 G6
RX_ACQ E3 F
E4 GND 2, 6 ,24, 26
EEPROM
A CE0
M4
RESET P2 27
D9 RTC_BATT
D7
C
( SDTX ) BDX CE1
C6
E
A9 F8
( TX_CLK ) BCLKX
A2
SERIAL
( SCLK_OUT ) BCLKR CTM
INTER ( WhiteCap ) HS_INT
F3
from / to MAGIC DSP
A3
-5V_EN
( SDFS ) BFSR FACE
LS_V1
N6
A / D KBR0, KBR1, KBR2
B4 STDBY DEEP SLEEP
( SDRX ) BDR
A4
( WhiteCap )
V1
C4
15 PIN EXT CONN. J 600 CIRCUIT
H5
2 LS_V1 KBC0, KBC1, KBC2,KBC3
KEYBOARD
1
DSC_EN J6 5
13 DSC
U901 -5V
( GCAP2 ) PWR_SW
BATT_PD
RS232_RX
7
( Q938 )
D6 UART BKLT+
SPI
TIMER
BATT_SER_DATA
INTERF.
RS232_TX 6 A6 INTERFACE
( GCAP2 ) V2
D7 K5 G14 GND
BATT CON. V2
CHRGC
1
3
BATT_FDBK 4
J604
4 2
( WhiteCap ) VIB_EN
ISENSE J810 J811
1
SW_RF
2 4
U801
5
B+
3 2 VIBRA CON.
BATT+
EXT_CHG_EN 8 EXT_B+
4 THERM 1
4
1, 2, 5, 6
R932 Q932 U950
( GCAP2 ) V2
EXT_B+ 14 EXT_B+
6-8
1, 2, 3
B+
Q942
4
3
CHRGC
VR830
CR940
5
GND 1 LED_RED Q805
6
( WhiteCap )
GND
F5 2 4
3 A7 B7 E8
LED_GRN Q805
ISENSE
GND
10
C7 D6 CHARGE
D9
1
SPI
GND
15 SELECT
REAL TIME
F10
INTERFACE
BATT+
CLOCK F7
SENSE
D10 EXT_B+
CLK
F6 6
J900
MAN_TEST_AD 5
A1 U900
PD
LEVEL SIM
J7
4
DSC_EN_AD B2
SENSE
Con.
SIM_I/O
SHIFT
DOWNLINL_AD A2 J8
5
1 2 VSIM1
G_CAP2
B3
BATT_THERM CNTL.
D9
ISENSE
K7 LS1_IN
G6 LS2_IN
K10 LS3_TX
H8 LS3_RX
ON / OFF 9 G5 C8 RX SIGNAL PATH
PWR_SW
C4 G4
STDBY
RESET Logic Control
TX SIGNAL PATH
VREF G9
VREF 2.775V,for GCAP
D2 REG.
UPLINK
11
MAIN VCO SIGNAL PATH
C3 V3 B5
V3 1,8V, for WhiteCap
DOWNLINK 12 REG.
J5
V2
V2 2.775V, for WhiteCap logic outputs, RAM, FLASH, EEPROM TUNING VOLTAGES
REG.
J2
A6
V1
MIC LS_V1 5.0V, for DSC Bus, Negative Voltage Regulator
REFERENCE CLOCK
REG.
VSIM C6
Interface
VSIM1 3.0 or 5.0V, for SIM Card Circuit
REG.
A10, C10 Orderable Part
Audio
2 1 H3
Codec
U980
VBOOST1
REG.
H9
H6 H7 K9 J9 K5 E10
Non - Orderable Part
J650 B10
EUROPE MIDDLE EAST & AFRICA 29.04.99
SPKR
V2
CUSTOMER SERVICES
HEADSET
CR901
CON.
Q938 L901 LEVEL 3 AL Block Diagram Rev. 1.5
V_BOOST1 Internal GCap use only (VSIM1, LS_V1)
ALRT
ALRT_VCC Dualband Kramer
HEAD_INT
B+
Q939
BKLT+ ( Flip Con. ) Ralf Lorenzen, Michael Hansen, Colin Jack, Ray Collins Page1
BATT_PD
13 MHz
MAGIC_13MHz
32.768 KHz
GCLK
GCAP SPI
RTC_BATT
Y900
GCAP_CLK
AUDIO SPI
BATT_THERM
PA_DRV
SPR+
SPR-
ALRTOUT
BKLT_EN
DUALBAND KRAMER
GSM_LNA275 RX
A1
LOCAL A9
OSCILLATOR
GSM LNA
Osc.
800MHz
E9
discrete
PLL
circuty
Q1255
C
U913
MIX_275
Q461
FL460 FL470
C8
B
MAGIC
CR259
V1
925-960MHz
925-960MHz
C
B ( SCLK_OUT ) BCLKR
Q1254
7 F7
4
B
C RX ( SDFS ) BFSR
A7 RXI
10 E
5 STEP to WhiteCap
G9
Q490
MIX_275 DEMODULATION
FL457
ATT.
SPI
RXQ ( SDRX ) BDR
6 C
C G8
400 MHz
EXT ANT
Q1254
B
U101 SW_VCC
C7
SW_RF
1805-1880MHz E
1805-1880MHz F2
2
9
B
C
B
G1
Q451
FL450 FL465
RF_V2 Q242 F1
VRef
C
E H9, J9
PHASE
H1
B+
U401
SWITCH DET
E
Divider
CONTROL
RF_V1 Q240
H2
200KHz
CR230
CIRCUIT C
B
J7
13MHz
DCS_LNA275
H7, C8; J1
B+
MAGIC_13MHz
J6
to WhiteCap
MUX G6
CLK_SELCT
1-3
4 DM_CS from WhiteCap
EGSM: 880-915Mhz
SF_OUT C1
Startup
U341
RVCO_250
DCS: 1710-1785MHz
EGSM: 1325-1360MHz Ref.
DCS_VCO
5 1 /2
A1
DCS: 1405-1480MHz
PA_B+
C1
PHASE Prog.
B1
Divider
REF. OSC.
DET
RX VCO
CR251
200KHz
A3 26 MHz
AFC
5
Divider 26MHz Y230
CR300 REF.
U300
FL300
CR250
2 C
B
C257
2 1
DCS Q300
PLL
Q253
3 4
1, 7 Q262
PA V1
Q255
C
B
J8
( CE ) MQSPI_CS1
Q455
G5
CR301 DCS_SEL C4 SPI
U400
( SPI_CLK ) MOSPI_CLK1
7 C
LOGIC
B
EGSM: 880-915Mhz F9
CR306,307 H4
GSM Q400
INTER
DCS: 1710-1785MHz
( SPI_DATA ) DX1
CONTROL
2, 8
PA
J3
FACE
-5V PAC_275
SHIFT LEVEL CIRCUIT
from WhiteCap
7
U340 PAC
2 U250 TX LOOP
6
FILTER
RF_IN
TX VCO ( SDTX ) BDX
4
DET
TXI TX J2
12 10 6
1, 3 NPA_MUTE
2
Q344 MODULATION
( TX_CLK ) BCLKX
SF_OUT
TXQ SPI
G7
PAC_275
TX_EN
SAT. TVCO_250 Q343
4, 14 PA_B+ ( GSM / DCS SELECT )
U341
10 12 8
11
RVCO_250
( RX VCO, GSM/DCS SELECT )
DETECT_SW
DET_SW A5
RX_ACQ
H8
AOC_DRIVE AOC_DRIVE
B6 DM_CS
LOGIC
J4 from WhiteCap
PA
TX_KEY
CONTROL
SAT_DETECT SAT_DETECT CONTROL H5
B4
TX_KEY_OUT TX_KEY_OUT C5
NPA_MUTE
TVCO_250
PAC_275
EUROPE MIDDLE EAST & AFRICA 29.04.99
REFERENCE CLOCK
RX SIGNAL PATH
DCS_VCO
MIX_275
CUSTOMER SERVICES Orderable Part
GSM_LNA275
TX SIGNAL PATH
GSM / DCS SELECT CIRCUIT
DCS_LNA275
LEVEL 3 RF Block Diagram Rev. 1.5
G_TX_VCO
MAIN VCO SIGNAL PATH Non - Orderable Part
D_TX_VCO
Dualband Kramer
GSM_PINDIODE
TUNING VOLTAGES
Ralf Lorenzen, Michael Hansen, Colin Jack, Ray Collins Page1
DCS_LNA275
GSM_LNA275
SWITCH
REG.
SWITCH
MIX_275
PAC_275
SUPER
FILTER
10
10-15
-15
GP04
GSM_PINDIODE
PAC_275
G_TX_VCO
D_TX_VCO
DUALBAND KRAMER