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-- Company:
-- Engineer:
--
-- Create Date: 10:22:17 12/07/2010
-- Design Name:
-- Module Name: mod16 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dioda is
Port ( CLK : in STD_LOGIC;
P1,P2 : in STD_LOGIC;
Q : inout STD_LOGIC:='1');
end dioda;

architecture Behavioral of dioda is
signal c,cs : integer range 0 to 14 := 0;
signal czas : integer range 1 to 4 := 1;
signal C1 : std_logic := '0';

begin


process(CLK)
begin
-- wybieranie czy 1s czy 3s za pomocą przycisku
if P1 = '1' then czas <= 1;
elsif P2 = '1' then czas <= 4; -- 4 chyba powinno być ze na 3 sec zgaśnie
else czas <= czas;
end if;

-- dzielnik częstotliwości CLK = 14HZ, C1 = 1HZ (zewrzeć dwa piny po prawo)
if rising_edge(CLK) then c <= c + 1;
if c = 2 then c <= 0; C1 <= not C1; end if;
--if c = 13 then c <= 0; C1 <= not C1; end if;
end if;
--- tu włączanie i wyłączanie diody
end process;

process(C1)
begin
if rising_edge(C1) then cs <= cs + 1;
if Q = '1' then -- gdy dioda nie pali sie
if cs >= 1 then cs <= 0; Q <= '0'; end if;
else -- czyli gdy Q ='0' tj dioda zapalona;
if cs >= czas then cs <= 0; Q <= '1'; end if;
end if;
end if;

end process;



end Behavioral;