24 lutego 2010 Wojciech Kucewicz 1
Design for
Design for
Design for
Design for
Design for
Design for
Design for
Design for
Manufacturability
Manufacturability
Manufacturability
Manufacturability
Manufacturability
Manufacturability
Manufacturability
Manufacturability
From presentation of prof.Wieław Kuz
micz on MIXDES 2003
24 lutego 2010 Wojciech Kucewicz 2
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability:
Design for Manufacturability:
what is it?
what is it?
24 lutego 2010 Wojciech Kucewicz 3
Typical analog IC design cycle
Typical analog IC design cycle
Typical analog IC design cycle
Typical analog IC design cycle
24 lutego 2010 Wojciech Kucewicz 4
Real circuits exhibit statistical spread of
Real circuits exhibit statistical spread of
Real circuits exhibit statistical spread of
Real circuits exhibit statistical spread of
parameters and characteristics
parameters and characteristics
parameters and characteristics
parameters and characteristics
Acceptance
Acceptance
Acceptance
Acceptance
region
region
This circuit is not manufacturable
This circuit is not manufacturable
This circuit is not manufacturable
This circuit is not manufacturable
24 lutego 2010 Wojciech Kucewicz 5
Real circuits exhibit statistical spread of
Real circuits exhibit statistical spread of
Real circuits exhibit statistical spread of
Real circuits exhibit statistical spread of
parameters and characteristics
parameters and characteristics
parameters and characteristics
parameters and characteristics
Acceptance
Acceptance
Acceptance
Acceptance
region
region
This circuit is manufacturable
This circuit is manufacturable
This circuit is manufacturable
This circuit is manufacturable
24 lutego 2010 Wojciech Kucewicz 6
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability
The question is:
The question is:
How to ensure that our design is not only
How to ensure that our design is not only
How to ensure that our design is not only
How to ensure that our design is not only
formally correct, but also manufacturable ?
formally correct, but also manufacturable ?
The answer is in
The answer is in
Design for Manufacturability
Design for Manufacturability
24 lutego 2010 Wojciech Kucewicz 7
Verification of manufacturability
Verification of manufacturability
Verification of manufacturability
Verification of manufacturability
Formal and functional verification: logic and/or electrical
Formal and functional verification: logic and/or electrical
Formal and functional verification: logic and/or electrical
Formal and functional verification: logic and/or electrical
simulations, DRC, LVS.
simulations, DRC, LVS.
Verification and optimization with respect of
Verification and optimization with respect of
Verification and optimization with respect of
Verification and optimization with respect of
secondary/parasitic effects: thermal effects, noise, RF
secondary/parasitic effects: thermal effects, noise, RF
stability, transmission effects in interconnections etc.
stability, transmission effects in interconnections etc.
y
y
Verification and minimization of sensitivity to
Verification and minimization of sensitivity to
manufacturing imperfections -> reduction of yield losses
manufacturing mp rf ct ons reduction of yield losses
manufactur ng mp rf ct ons r uct on of y oss s
manufactur ng imperfections -> r uct on of y oss s
due to catastrophic and parametric faults
due to catastrophic and parametric faults..
24 lutego 2010 Wojciech Kucewicz 8
SOI detektor
SOI detektor
SOI detektor
SOI detektor
SOI Detector 48x48 cells
SOI Detector 48x48 cells
- yields 20%
- yields 20%
SOI Detector 128x128 cells - yields 0%
SOI Detector 128x128 cells - yields 0%
24 lutego 2010 Wojciech Kucewicz 9
Terminology
Terminology
Terminology
Terminology
" Defect (defekt, usterka):
" Defect (defekt, usterka):
D f t (d f kt t k )
D f t (d f kt t k )
a significant difference between designed and actual IC
a significant difference between designed and actual IC
structure
structure
" Fault (wada):
" Fault (wada):
unacceptable IC performance
unacceptable IC performance
24 lutego 2010 Wojciech Kucewicz 10
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability
Defects:
Defects:
Structural defects: breaks, shorts, pinholes etc.
Structural defects: breaks, shorts, pinholes etc.
Statistical variations of device structure: doping profiles, layer
Statistical variations of device structure: doping profiles, layer
thicknesses etc
thicknesses etc
thicknesses etc.
thicknesses etc.
Faults:
Faults:
Catastrophic (hard) faults: IC does not work (does not perform its
Catastrophic (hard) faults: IC does not work (does not perform its
function)
function)
Parametric (soft) faults: IC does work but its performance is
Parametric (soft) faults: IC does work but its performance is
unacceptable
unacceptable
unacceptable
unacceptable
24 lutego 2010 Wojciech Kucewicz 11
Structural defects
Structural defects
Structural defects
Structural defects
VDD
VDD
VDD
VDD
Missing poly
Missing poly
Missing poly
Missing poly
Out
Out
In
In
A break
A break
An oxide pinhole
An oxide pinhole
(missing
(missing
(missing
(missing
contact)
contact)
A break
A break
( lit
( lit
(open, split
(open, split
node)
node)
A short (bridge)
A short (bridge)
VSS
VSS
VSS
VSS
St t l d f t ft lt in catastrophic faults but l
St t l d f t ft lt in t t hi f lt b t may also
Structural defects often result i t t hi faults but l
Structural defects often result i catastrophic f lt b t may also
affect performance
affect performance
24 lutego 2010 Wojciech Kucewicz 12
Structural defects
Structural defects
Structural defects
Structural defects
A spot of missing metal between
A spot of missing metal between
two contacts results in a break
two contacts results in a break
two contacts results in a break...
two contacts results in a break...
similar shape of the active
similar shape of the active
... but not always !
... but not always !
area mask with a similar
area mask with a similar
redundant routing
redundant routing
defect does result in a break !
defect does result in a break !
Structural defects not always result in faults
Structural defects not always result in faults
24 lutego 2010 Wojciech Kucewicz 13
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability
In a CMOS circuit voltage on a disconnected
In a CMOS circuit voltage on a disconnected
g
g
transistor gate is unpredictable
transistor gate is unpredictable
(a) Low voltage (~0) :
(a) Low voltage (~0) :
PMOS transistor conducting logic function not
PMOS transistor conducting logic function not
PMOS transistor conducting, logic function not
PMOS transistor conducting, logic function not
affected, but: - increased "0" level and static DC
affected, but: - increased "0" level and static DC
current when A = "0", B ="1 - speed may be
current when A = "0", B ="1 - speed may be
reduced
reduced
(b) High voltage (~VDD) : PMOS transistor cut
(b) High voltage (~VDD) : PMOS transistor cut
off, logic output incorrect when B = "0".
off, logic output incorrect when B = "0".
Consequences of structural defects may be unpredictable Structural
Consequences of structural defects may be unpredictable Structural
qy p
qy p
defects may result in parametric faults Faults are not always easily
defects may result in parametric faults Faults are not always easily
observable
observable
24 lutego 2010 Wojciech Kucewicz 14
Process and layout variations
Process and layout variations
Process and layout variations
Process and layout variations
" Unavoidable disturbances in
" Unavoidable disturbances in
Unavoidable disturbances in
Unavoidable disturbances in
process parameters (temperatures,
process parameters (temperatures,
times, doses etc.)
times, doses etc.)
" Unavoidable disturbances in
" Unavoidable disturbances in
Unavoidable disturbances in
Unavoidable disturbances in
litography (under/overetching, mask
litography (under/overetching, mask
misalignment, shape distortion etc.)
misalignment, shape distortion etc.)
" Result: statistical spread of device
" Result: statistical spread of device
parameters
parameters
parameters
parameters
Th i ti l d t t i f lt b t t t hi
Th i ti l d t t i f lt b t t t hi
These variations may lead to parametric faults but catastrophic
These variations may lead to parametric faults but catastrophic
faults (non-functional circuits) are also possible
faults (non-functional circuits) are also possible
24 lutego 2010 Wojciech Kucewicz 15
Process variations: classification
Process variations: classification
Process variations: classification
Process variations: classification
Global variations: affect all structures in a wafer in the same way,
Global variations: affect all structures in a wafer in the same way,
do not introduce mismatch (example: variation of temperature along
do not introduce mismatch (example: variation of temperature along
do not introduce mismatch (example: variation of temperature along
do not introduce mismatch (example: variation of temperature along
a furnace during thermal processes).
a furnace during thermal processes).
Global process variations may result in large variations of device
Global process variations may result in large variations of device
Global process variations may result in large variations of device
Global process variations may result in large variations of device
parameters
parameters
24 lutego 2010 Wojciech Kucewicz 16
Process variations: classification
Process variations: classification
Process variations: classification
Process variations: classification
Local deterministic variations are
Local deterministic variations are
Local deterministic variations are
Local deterministic variations are
deterministic (often, but not always, radial)
deterministic (often, but not always, radial)
functions of position on wafer (example:
functions of position on wafer (example:
radial variation of temperature during
radial variation of temperature during
th l ss s)
th l ss s)
thermal processes).
thermal processes).
Local deterministic variations introduce mismatch (difference in
Local deterministic variations introduce mismatch (difference in
parameters of identical devices) which increases with distance
parameters of identical devices) which increases with distance
b t t h d i f d i
b t t h d i f d i
between matched pair of devices
between matched pair of devices
24 lutego 2010 Wojciech Kucewicz 17
Process variations: classification
Process variations: classification
Process variations: classification
Process variations: classification
Local random variations: "random noise" in
Local random variations: "random noise" in
mm
mm
some process parameters or material
some process parameters or material
properties. Example: random variations in
properties. Example: random variations in
substrate doping concentration; another
substrate doping concentration; another
example: random variations in carrier
example: random variations in carrier
example: random variations in carrier
example: random variations in carrier
lifetime.
lifetime.
Local random variations introduce mismatch which may or may not
Local random variations introduce mismatch which may or may not
Local random variations introduce mismatch which may or may not
Local random variations introduce mismatch which may or may not
depend on distance.
depend on distance.
24 lutego 2010 Wojciech Kucewicz 18
Process variations: classification
Process variations: classification
Process variations: classification
Process variations: classification
Let's assume radial dependence of VT:
Let's assume radial dependence of VT:
No VT mismatch for this pair of devices
No VT mismatch for this pair of devices
Moderate VT mismatch for this pair of devices
Moderate VT mismatch for this pair of devices
Large VT mismatch for this pair of devices
Large V mismatch for this pair of devices
Large V mismatch for this pair of devices
Large VT mismatch for this pair of devices
For a randomly selected sample of devices coming from various
For a randomly selected sample of devices coming from various
unknown locations on the wafer deterministic variations seem to be
unknown locations on the wafer deterministic variations seem to be
random ! - that s why all local variations are often considered
random ! - that s why all local variations are often considered
random.
random.
24 lutego 2010 Wojciech Kucewicz 19
Process variations: classification
Process variations: classification
Process variations: classification
Process variations: classification
Parameter value
Parameter value
actual value = nominal value
actual value = nominal value
+ global variation "g
+ global variation "g
l b l i i
l b l i i
+ local deterministic variation "d
+ local deterministic variation "d
+ local random variation "r
+ local random variation "r
local random variation "r
local random variation "r
"g
"g
Nominal value
Nominal value
A t l l f t i i l ff t d b
A t l l f t i i l ff t d b
Actual value of a process parameter is, in general case, affected by
Actual value of a process parameter is, in general case, affected by
all three kinds of variations
all three kinds of variations
24 lutego 2010 Wojciech Kucewicz 20
Layout disturbances
Layout disturbances
Layout disturbances
Layout disturbances
Green: desired shape (as designed) Red: actual shape
Green: desired shape (as designed) Red: actual shape
Green: desired shape (as designed) Red: actual shape
Green: desired shape (as designed) Red: actual shape
misalignment: over/underetching: shape distortion:
misalignment: over/underetching: shape distortion:
global disturbance global disturbance local disturbance
global disturbance global disturbance local disturbance
L t di t b l h l b l and l l t S
L t di t b l h l b l d l l t Some
Layout disturbances also have global d local components. Some
Layout disturbances also have global and local components. S
disturbances affect device performance, other don t
disturbances affect device performance, other don t
24 lutego 2010 Wojciech Kucewicz 21
Layout disturbances
Layout disturbances
Layout disturbances
Layout disturbances
Under/over etching: Shape distortion:
Under/over etching: Shape distortion:
Misalignment:
Misalignment:
change of W/L in a single individual W/L change in
change of W/L in a single individual W/L change in
W/L not affected
W/L not affected
device, but W/L(n) /W/L(p) in every device
device, but W/L(n) /W/L(p) in every device
a CMOS gate not affected
a CMOS gate not affected
CMOS t t ff t d
CMOS t t ff t d
S di t b ff t d i d i it f
S disturbances affect device and circuit performance,
Some disturbances affect device and circuit performance,
Some di t b ff t d i d i it f
other don t
other don t
24 lutego 2010 Wojciech Kucewicz 22
Deep submicron CMOS: new
Deep submicron CMOS: new
Deep submicron CMOS: new
Deep submicron CMOS: new
phenomena (examples)
phenomena (examples)
phenomena (examples)
phenomena (examples)
M l l l i i f d i
M l l l i i f d i
Molecular scale variations of doping
Molecular scale variations of doping
Lithography: proximity effects
Lithography: proximity effects
and corrections, phase shifting
and corrections, phase shifting
masks
masks
It is expected that very deep submicron CMOS circuits will
It is expected that very deep submicron CMOS circuits will
It is expected that very deep submicron CMOS circuits will
It is expected that very deep submicron CMOS circuits will
exhibit much higher sensitivity to process and layout disturbances.
exhibit much higher sensitivity to process and layout disturbances.
24 lutego 2010 Wojciech Kucewicz 23
Manufacturing imperfections vs.
Manufacturing imperfections vs.
Manufacturing imperfections vs.
Manufacturing imperfections vs.
faults: CMOS digital gates
faults: CMOS digital gates
faults: CMOS digital gates
faults: CMOS digital gates
Structural defects:
Structural defects:
" usually result in catastrophic faults
" usually result in catastrophic faults
usually result in catastrophic faults
usually result in catastrophic faults
" may affect performance
" may affect performance
Variations of device parameters:
Variations of device parameters:
" affect performance
" affect performance
" do not affect function
" do not affect function
Physical design:
Physical design:
Physical design:
Physical design:
" large number of small devices
" large number of small devices
" dense layout, dense wiring, large area
" dense layout, dense wiring, large area
yg g
yg g
-> sensitivity to structural defects
-> sensitivity to structural defects
Structural defects are the most important source of faults in digital
Structural defects are the most important source of faults in digital
Structural defects are the most important source of faults in digital
Structural defects are the most important source of faults in digital
CMOS circuits
CMOS circuits
24 lutego 2010 Wojciech Kucewicz 24
Manufacturing imperfections vs.
Manufacturing imperfections vs.
Manufacturing imperfections vs.
Manufacturing imperfections vs.
faults: CMOS analog circuits
faults: CMOS analog circuits
faults: CMOS analog circuits
faults: CMOS analog circuits
Structural defects:
Structural defects:
" usually result in catastrophic faults
" usually result in catastrophic faults
" often affect performance
" often affect performance
f ff f
f ff f
Variations of device parameters:
Variations of device parameters:
" strongly affect performance
" strongly affect performance
strongly affect performance
strongly affect performance
" often affect function, resulting in
" often affect function, resulting in
catastrophic faults
catastrophic faults
Ph si l d si :
Ph si l d si :
Physical design:
Physical design:
" small number of relatively large devices
" small number of relatively large devices
" low layout and wiring density, moderate
" low layout and wiring density, moderate
yg y,
yg y,
area
area
-> low sensitivity to structural defects
-> low sensitivity to structural defects
In analogue circuits variations of device parameters are usually more
In analogue circuits variations of device parameters are usually more
important source of failures than structural defects
important source of failures than structural defects
24 lutego 2010 Wojciech Kucewicz 25
Fundamental model of a good IC design:
Fundamental model of a good IC design:
Fundamental model of a good IC design:
Fundamental model of a good IC design:
" Global i ti f d i t l
" Gl b l variations of device parameters are large
Global i ti f d i t l
Gl b l variations of device parameters are large
" Local variations of device parameters are small
" Local variations of device parameters are small
(1) Circuits are manufacturable if their performance is insensitive to
(1) Circuits are manufacturable if their performance is insensitive to
absolute values of device parameters
absolute values of device parameters
(2) This is achieved if circuit performance depends on ratios of
(2) This is achieved if circuit performance depends on ratios of
(2) This is achieved if circuit performance depends on ratios of
(2) This is achieved if circuit performance depends on ratios of
device parameters ( device matching principle)
device parameters ( device matching principle)
(3) Circuits based on device matching principle are manufacturable if
(3) Circuits based on device matching principle are manufacturable if
(3) Circuits based on device matching principle are manufacturable if
(3) Circuits based on device matching principle are manufacturable if
device mismatch is not too big.
device mismatch is not too big.
24 lutego 2010 Wojciech Kucewicz 26
MOS transistor matching
MOS transistor matching
MOS transistor matching
MOS transistor matching
A
adunek
A
adunek
Kontaktowa Potencjał A
adunek Koncentracja
Kontaktowa Potencjał A
adunek Koncentracja
domieszek
domieszek
domieszek
domieszek
różnica Fermiego równoważny domieszki w
różnica Fermiego równoważny domieszki w
ó i F i ó d i ki
ó i F i ó d i ki
zjonizowanych w
zjonizowanych w
potencjałów stanów zaimplantowanym
potencjałów stanów zaimplantowanym
półprzewodniku
półprzewodniku
me-pp powierzchniowych kanale
me-pp powierzchniowych kanale
24 lutego 2010 Wojciech Kucewicz 27
MOS transistor matching
MOS transistor matching
MOS transistor matching
MOS transistor matching
A good measure of matching: input offset voltage of a differential pair
A good measure of matching: input offset voltage of a differential pair
"V = VGS1 - VGS2
"V = VGS1 - VGS2
- a difference in gate voltages necessary to obtain equal drain currents (assuming
- a difference in gate voltages necessary to obtain equal drain currents (assuming
identical drain-source voltages VDS)
identical drain-source voltages VDS)
24 lutego 2010 Wojciech Kucewicz 28
MOS transistor matching
MOS transistor matching
MOS transistor matching
MOS transistor matching
Variations affecting the drain current:
Variations affecting the drain current:
" Carrier mobility ź
" Carrier mobility ź
Carrier mobility ź
Carrier mobility ź
" Oxide capacitance Cox
" Oxide capacitance Cox
" Channel dimensions W, L
" Channel dimensions W, L
" Threshold voltage Vth
" Threshold voltage Vth
Variations affecting the threshold voltage:
Variations affecting the threshold voltage:
" Śms, Śf - negligible effect (log functions of doping)
" Śms, Śf - negligible effect (log functions of doping)
" Interface charge Qss
" Interface charge Q
" Interface charge Q
" Interface charge Qss
" Substrate doping NA
" Substrate doping NA
" Channel implant dose DI
" Channel implant dose DI
p
p
I
I
" Oxide capacitance Cox
" Oxide capacitance Cox
24 lutego 2010 Wojciech Kucewicz 29
MOS transistor matching
MOS transistor matching
MOS transistor matching
MOS transistor matching
24 lutego 2010 Wojciech Kucewicz 30
MOS transistor matching
MOS transistor matching
MOS transistor matching
MOS transistor matching
VTh mismatch as a function of device channel size
VTh mismatch as a function of device channel size
24 lutego 2010 Wojciech Kucewicz 31
MOS transistor matching
MOS transistor matching
MOS transistor matching
MOS transistor matching
24 lutego 2010 Wojciech Kucewicz 32
MOS transistor matching
MOS transistor matching
MOS transistor matching
MOS transistor matching
F d t hi i i dimensions cannot be used!
F d t hi i i dimensions cannot be used!
For good matching minimum di si s t b s d!
For good matching minimum di si s t b s d!
As a result, there is a trade off between good matching and:
As a result, there is a trade off between good matching and:
" high frequency performance,
" high frequency performance,
hi h f f
hi h f f
" chip area.
" chip area.
24 lutego 2010 Wojciech Kucewicz 33
MOS transistor matching
MOS transistor matching
MOS transistor matching
MOS transistor matching
24 lutego 2010 Wojciech Kucewicz 34
MOS transistor matching
MOS transistor matching
MOS transistor matching
MOS transistor matching
Averaging of variations of VTh
Averaging of variations of VTh
24 lutego 2010 Wojciech Kucewicz 35
MOS transistor matching
MOS transistor matching
MOS transistor matching
MOS transistor matching
Averaging of variations of VTh
Averaging of variations of VTh
C t id l tff ti l di t h lti
C t id l tff ti l di t h lti
Common centroid layout very effectively reduces mismatch resulting
Common centroid layout very effectively reduces mismatch resulting
from local deterministic variations
from local deterministic variations
24 lutego 2010 Wojciech Kucewicz 36
MOS transistor matching
MOS transistor matching
MOS transistor matching
MOS transistor matching
For purely random variations of
For purely random variations of
V the probability density
V the probability density
VTh the probability density
VTh the probability density
functions of all four "VTh are the
functions of all four "VTh are the
same. Therefore, it doesn't
same. Therefore, it doesn't
matter whether transistors are
matter whether transistors are
matter whether transistors are
matter whether transistors are
cross-connected or not.
cross-connected or not.
Averaging of variations of VTh
Averaging of variations of VTh
C t id layout does NOT reduce mismatch resulting from
C t id layout does NOT reduce mismatch resulting f
Common centroid l t d NOT d i t h lti f
Common centroid l t d NOT d i t h lti from
local random variations
local random variations
24 lutego 2010 Wojciech Kucewicz 37
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability:
Design for Manufacturability:
" requires good understanding of the sources of disturbances,
" requires good understanding of the sources of disturbances,
" involves various design trade-offs,
" involves various design trade-offs,
" is still considered  more art than Science
" is still considered  more art than Science
24 lutego 2010 Wojciech Kucewicz 38
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability - phase 1
Design for Manufacturability - phase 1
" Selection and design of a circuit which is inherently insensitive
" Selection and design of a circuit which is inherently insensitive
g y
g y
to global variations of device parameters.
to global variations of device parameters.
" Design of a layout which does not violate design rules and (if
" Design of a layout which does not violate design rules and (if
necessary) uses simple i t iti rules to obtain good d i
necessary) uses simple i t iti rules to obtain good d i
) i l intuitive l t bt i d device
) i l intuitive l t bt i d device
matching.
matching.
" Verification of formal and functional correctness of the design
" Verification of formal and functional correctness of the design
Verification of formal and functional correctness of the design
Verification of formal and functional correctness of the design
(DRC, circuit extraction, LVS and post-layout circuit simulation
(DRC, circuit extraction, LVS and post-layout circuit simulation
with nominal values of device parameters).
with nominal values of device parameters).
24 lutego 2010 Wojciech Kucewicz 39
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability - phase 2:
Design for Manufacturability - phase 2:
V ifi ti d ti i ti f the design ith t t
V ifi ti d ti i ti f th d i ith t t
Verification and optimization of the design with respect to
Verification and optimization of th d i with respect to
secondary parasitic effects such as:
secondary parasitic effects such as:
" Thermal effects
" Thermal effects
Thermal effects
Thermal effects
" Parasitic coupling, switching noise
" Parasitic coupling, switching noise
" RF stability
" RF stability
" RF stability
" RF stability
" Signal propagation effects in long interconnects
" Signal propagation effects in long interconnects
24 lutego 2010 Wojciech Kucewicz 40
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability
Design for Manufacturability - phase 3:
Design for Manufacturability - phase 3:
V ifi ti d i i i ti f iti it to f t i
V ifi ti d i i i ti f iti it to f t i
Verification and minimization of sensitivity t manufacturing
Verification and minimization of sensitivity t manufacturing
imperfections:
imperfections:
" Worst case analysis (simulations for  process
" Worst case analysis (simulations for  process
Worst case analysis (simulations for process
Worst case analysis (simulations for process
Corners )
Corners )
" Simple statistical Monte Carlo analysis
" Simple statistical Monte Carlo analysis
" Simple statistical Monte Carlo analysis
" Simple statistical Monte Carlo analysis
" Mismatch oriented statistical Monte Carlo analysis
" Mismatch oriented statistical Monte Carlo analysis
" Netlist driven statistical process device circuit Monte Carlo
" Netlist driven statistical process-device-circuit Monte Carlo
Netlist driven statistical process-device-circuit Monte Carlo
Netlist driven statistical process device circuit Monte Carlo
simulation
simulation
24 lutego 2010 Wojciech Kucewicz 41
Conclusions
Conclusions
Conclusions
Conclusions
Methods of design for manufacturability are still not part of the
Methods of design for manufacturability are still not part of the
standard engineering practices, in most cases only simplest of them
standard engineering practices, in most cases only simplest of them
are used
are used
d
d
Understanding of the sources of variations and mismatch and their
Understanding of the sources of variations and mismatch and their
effects on circuit performance are necessary blind use of
effects on circuit performance are necessary blind use of
effects on circuit performance are necessary,  blind use of
effects on circuit performance are necessary,  blind use of
methods and tools does not guarantee good results
methods and tools does not guarantee good results
Special tools exist but are not always mature and are seldom
Special tools exist but are not always mature and are seldom
py
py
available in standard commercial CAD toolsets
available in standard commercial CAD toolsets
24 lutego 2010 Wojciech Kucewicz 42