ARM assembly language reference card MOVcdS reg, arg copy argument (S= set flags) Bcd imm12 branch to imm12 words away MVNcdS reg, arg copy bitwise NOT of argumentBLcd imm12 copy PC to LR, then branch ANDcdS reg, reg, arg bitwise AND BXcd reg copy reg to PC ORRcdS reg, reg, arg bitwise OR SWIcd imm24 software interrupt EORcdS reg, reg, arg bitwise exclusive-OR LDRcdB reg, mem loads word/byte from memory BICcdS reg, rega, argb bitwise rega AND (NOT argb) STRcdB reg, mem stores word/byte to memory ADDcdS reg, reg, arg add LDMcdum reg!, mreg loads into multiple registers SUBcdS reg, reg, arg subtract STMcdum reg!, mreg stores multiple registers RSBcdS reg, reg, arg subtract reversed arguments SWPcdB regd, regm,[regn] copies regm to memory at regn, ADCcdS reg, reg, arg add with carry flag old value at address regn to regd SBCcdS reg, reg, arg subtract with carry flag RSCcdS reg, reg, arg reverse subtract with carry flag CMPcd reg, arg update flags based on subtraction CMNcd reg, arg update flags based on addition TSTcd reg, arg update flags based on bitwise AND TEQcd reg, arg update flags based on bitwise exclusive-OR MULcdS regd, rega, regb multiply rega and regb, places lower 32 bits into regd MLAcdS regd, rega, regb, regc places lower 32 bits of rega · regb + regc into regd UMULLcdS reg , regu, rega, regb multiply rega and regb, place 64-bit unsigned result into {regu, reg } UMLALcdS reg , regu, rega, regb place unsigned rega · regb + {regu, reg } into {regu, reg } SMULLcdS reg , regu, rega, regb multiply rega and regb, place 64-bit signed result into {regu, reg } SMLALcdS reg , regu, rega, regb place signed rega · regb + {regu, reg } into {regu, reg } reg: register arg: right-hand argument " R0toR15 register according to number #imm8 immediate (rotated into 8 bits) SP register 13 reg register LR register 14 reg, shift register shifted by distance PC register 15 mem: memory address um: update mode [reg,#Ä…imm12] reg offset by constant IA increment, starting from reg [reg, Ä…reg] reg offset by variable bytes IB increment, starting from reg + 4 [rega, Ä…regb, shift] rega offset by shifted variable regb DA decrement, starting from reg [reg,#Ä…imm12]! update reg by constant, then access memory DB decrement, starting from reg - 4 [reg, Ä…reg]! update reg by variable bytes, access memory [reg, Ä…reg, shift]! update reg by shifted variable , access memory cd: condition code [reg],#Ä…imm12 access address reg, then update reg by offset ALor omitted always [reg], Ä…reg access address reg, then update reg by variable EQ equal (zero) [reg], Ä…reg, shift access address reg, update reg by shifted variable NE nonequal (nonzero)
shift distance must be by constant CS carry set (same asHS) CC carry clear (same asLO) shift: shift register value MI minus LSL#imm5 shift left 0 to 31 PL positive or zero LSR#imm5 logical shift right 1 to 32 VS overflow set ASR#imm5 arithmetic shift right 1 to 32 VC overflow clear ROR#imm5 rotate right 1 to 31 HS unsigned higher or same RRX rotate carry bit into top bit LO unsigned lower LSLreg shift left by register HI unsigned higher LSRreg logical shift right by register LS unsigned lower or same ASRreg arithmetic shift right by register GE signed greater than or equal RORreg rotate right by register LT signed less than GT signed greater than LE signed less than or equal