/
CM-H777RC H888RC
AMPS
CM-H777RC/H888RC
SECTION 5
DIAGRAMS
5-1. FRAME SCHEMATIC DIAGRAM
FRONT ASSY I/F
MIC201
MICROPHONE
>1 MIC
>2 GND
MIC201
ANTENNA
J201
J2
J3
RECEIVER
>1 EP (+)
>2 EP ( )
ANTENNA
LOGIC
MATCHING
NETWORK
BATTERY
J1
<1 +B 1> +B
>20
<2 TEMP DET CHG-C
>22
RADIO
<3 GND 2> GND
>19
EXT +B
>5
VBC
>1
EXT +B
>3
VPP
>4
RX DATA
>2
EXT PS SW
>6
EXT A. M
>7
TX DATA
>8
ID
>9
VDD
>10
GND
>11
RECEIVE AUDIO
>12
GND
>13
TRANSMIT AUDIO
>14
MAIN
 18 
+B
1>
>1
+B
+B
2>
>2
+B
+B
3>
>3
+B
MIC
16>
>16
MIC
VDD
26>
>26
VDD
GND
4>
>4
GND
GND
15>
>15
GND
GND
27>
>27
GND
BL-C
19>
>19
BL-C
RIN5
9>
>9
RIN5
RIN4
10>
>10
RIN4
RIN3
11>
>11
RIN3
RIN2
12>
>12
RIN2
RIN1
13>
>13
RIN1
RIN0
14>
>14
RIN0
VDDB
21>
>21
VDDB
R-LED
18>
>18
R-LED
RESET
22>
>22
RESET
PS SW
23>
>23
PS SW
SCAN3
5>
>5
SCAN3
SCAN2
6>
>6
SCAN2
SCAN1
7>
>7
SCAN1
SCAN0
8>
>8
SCAN0
LCD-CE
20>
>20
LCD-CE
LCD-SID
25>
>25
LCD-SID
LCD-CLK
24>
>24
LCD-CLK
CHARGE-IN
28>
>28
CHARGE-IN
CHARGE-IN
29>
>29
CHARGE-IN
CHARGE-IN
30>
>30
CHARGE-IN
CHARGE-DET
17>
>17
CHARGE-DET
" IC Block Diagrams  RAGIC Board 
U2 AT29LV010A-15TC1
OE, CE & WE
LOGIC
DATA BUS
A11 OE
1 32
A9 2 31 A10
A8 3 DATA LATCH 30 CE
A13 4 29 I/O7
A14 5 28 I/O6
INPUT/OUTPUT
NC 6 BUFFERS 27 I/O5
WE 7 26 I/O4
VCC 8 25 I/O3
Y
Y-GATING
DECODER
NC 9 24 GND
A16 10 23 I/O2
OPTIONAL BOOT
A15 11 22 I/O1
X
BLOCK
DECODER
A12 12 21 I/O0
(8K BYTES)
A7 13 20 A0
MAIN MEMORY
A6 14 19 A1
(112K BYTES)
A5 15 18 A2
OPTIONAL BOOT
A4 16 17 A3
BLOCK
(8K BYTES)
U3 MB3805APFV-G-BND
36 35 34 33 32 31 30 29 28 27 26 25
FB 37 24 VO2
SPEAKER
BP 38 23 VO3
SOUNDER
AMP
BLOCK
IN 39 22 VO0
BLOCK
SB 40 21 VCC5
20 NC
DETECTOR 19 VCC3
&
CT4 41 18 TOUT
POWER ON
REVERSION
RESET 17 CT3
BLOCK OF
BLOCK
POR OUT 42 16 CT2
POWER
15 CLR
SUPPLY
CT1 43
ON1 44
ON/OFF
REFERENCE
ON2 45 SWITCH
VOLTAGE
BLOCK
OFF 46
CIRCUIT
VCC2 47 14 GND2
13 GND1
POWER
REG 1 REG 4 REG 2 REG 3
SUPPLY
SWITCH
NC 48
1 2 3 4 5 6 7 8 9 10 11 12
 19 
ADDRESS BUS
GND4
GND3
OUTB
OUTA
VCC4
CLK
IN1
IN2
IN3
GND6
GND5
VO1
NC
NC
NC
CTL2
CTL3
VREF
VCC1
OUT3
OUT1
OUT2
OUT4
OUT5
U5 AK2334
80 1 2 71 70 69 72 17 44 43 15 16 14 13 4 3 5 74 73
ALCVDD 41
AMP2
VR8 DTMF GEN
+
ALCVSS 47
77 REC1
S7

RPLVSS 30 VREF/BIAS
REGISTER
AGND
RPLVDD 25 S5
S1
S19
VR1
TPLVSS 32 AMP3
+
 COS+RDATA
S20 78 EXTOUT
TPLVDD 38
MSELI AAF1 VR7 RX BPF D/E ADD

+ LPF
EXPAND
RAVSS 79
AMP1
S6
S17
RAVDD 75
S15
VR2
AMP4
TAVSS 61 +
S9 76 REC2
TAVDD 65 
DVSS 23
RSW
S18
DVDD 24 SMF1
CMP1 19 RDATA
ULALM 33
RXPDP 29
6 RDCAP
RXPDN 28
SAT
SAT SAT
SMF2 CMP2 20 SATOUT
RXSYNTH
RXCLK 27
BFP2
BFP1 NPATH
9 CKSEL
RXMC 26
11 OSCOUT
S14
OSC
NC 31 12 OSCIN
S2
21 CPUCK
TXPDN 36
SATDATA
TSATLPF VR6
SATNPATH CLK
TXCLK 35 REMAKE
TXSYNTH
22 MCLK
CLKDIV DIVIDE
S3
TXPDP 37
DATA
VR5 42 TDATA
TXMC 34
REMAKE
VR10 64 TONEIN
S9
TDATA S4
TEST1
MODOUT 55 SMF3 VR3 SUM
66 MIC2
LPF S6
SPLAT S13
LIMITER
67 MIC3
P/E VR4
AMP5
S16 VR9
68 MIC1
S11
COS+ S13
COMPRES AAF2 MUX
TXBPF
LODAC DTX ALC
TSS ALCDAC
63 EXTIN
S10
S12
STIN 39 62 MEMIN
NC 10 7 NC
40 8 18 58 53 52 51 50 49 54 45 46 48 56 57 59 60
U8A AT24C32N-10SI-2.7 U302 TA31181FN
8 VCC
START/ WP
7
STOP 24 23 22 21 20 19 18 17 16 15 14 13
6 SCL
LOGIC
H.V.
EN
SERIAL
PUMP/
CONTROL
LOAD DETECTOR
DEVICE CONTROL
TIMING
COMP
ADDRESS LOGIC
COMPARATOR
MIXER
IF AMP
A0 1
DATA
RSSI AMP
A1 2
RECOVERY
+
A2 3
DATA WORD X
R/W
LOCAL BAND-PASS
EEPROM

ADDRESS/ DECODER RSSI
OSCILLATOR FILTER
COUNTER
SERIAL
MUX
Y
1 2 3 4 5 6 7 8 9 10 11 12
DECODER
D OUT/
ACK
LOGIC
D IN
VSS 4
D OUT
5 SDA
 20 
DEM3
DEM1
DEM2
RAGND
AGNDIN
TAGND
BIAS
SPCNT
CRON
TXE
SDATA
SCLK
STROBE
RSTB
EXP1
EXP2
RTONE
DTMFOUT
EXP3
TSSI
ALCI
TSSO
ALCIO
DTXIN
TXBPF
LOREF
PVREF
VREFO
NVREF
STOUT
COMP2
COMP1
ALCREF
ALCOUT
COMPIN
DTXOUT
CLK
CLK SEL
LPF
VCC2
GND
MIX SEL
IF OUT
MIX IN
AF OUT
BS
DET IN
MONI
INC
LOAD
NF
REF
DEC
RSSI
VCC1
BPF IN
OSC IN
MIX OUT
OSC OUT
R-DET IN+
R-DET IN
R-DET OUT

+
U306 MB15U10PFV-G-BND
20 19 18 17 16 15 14 13 12 11
I SET
SHIFT
CHARGE
REGISTER
CR2
PUMP
(21 BIT)
SELECT
OLA, B
CIRCUIT
PHASE
COMPARATOR LATCH
No.2 SELECT
P0
MAIN COUNTER 17 BIT LATCH
No.2 COMPARSION
(BINARY 17BIT) DIVIDER No.2
MAIN COUNTER 17 BIT LATCH
No.1 COMPARSION
(BINARY 17BIT) DIVIDER No.1
CR1, 2
REFERENCE 14 BIT LATCH
10 BIT OLA, B
÷1/÷2
COUNTER REFERENCE
LATCH
P0
(BINARY 12BIT) DIVIDER
P1, 2, 3
PHASE
COMPARATOR
No.1
SELECT
P1, 2, 3
CIRCUIT
POWER SAVE
No.1
CHARGE
CR1
PUMP
POWER SAVE
No.2
1 2 3 4 5 6 7 8 9 10
U405 TK11240BMCL
V IN GND V OUT
6 5 4
THERMAL
PROTECTION
BANDGAP
REFERENCE

+
1 2 3
C GND N.BYPASS
 21 
LE
DATA
CLOCK
ISET
PO/LD
AGND
fin 2
VDD2
Vr
DO2
PS
DO1
fin 1
VDD1
P3/fr2
DGND
P2/fp2
P1/fp1
OSCIN
OSCOUT
+

CM-H777RC/H888RC
5-2. PRINTED WIRING BOARD  RF/LOGIC Section 
" Semiconductor Location
Ref. No. Location Ref. No. Location Ref. No. Location
CR2 I-7 Q7 G-7 U1A H-6
CR3 C-14 Q8 G-6 U2 I-3
CR4 G-3 Q301 I-13 U3 D-4
CR5 G-4 Q303 I-10 U5 D-6
CR401 G-13 Q304 H-9 U8A E-5
CR402 E-11 Q401 G-13 U301 I-11
Note:
CR403 E-11 Q402 F-12 U302 I-8
" This board is four-layer printed board.
Q403 G-11 U306 H-11
However, the patterns of layers 2 and 3 have not been
Q405 G-12 U405 G-11
included in the diagram.
 23   24 
CM-H777RC/H888RC
5-3. SCHEMATIC DIAGRAM  RAGIC Board (1/2) (RF Section) 
" See page 22 for Waveforms. " See page 20 and 21 for IC Block Diagrams.
(Page 28)
(Page 27)
 25   26 
CM-H777RC/H888RC
5-4. SCHEMATIC DIAGRAM  RAGIC Board (2/2) (LOGIC Section) 
" See page 22 for Waveforms. " See page 19 and 20 for IC Block Diagrams.
(Page 31)
(Page
26)
(Page 25)
 27   28 
CM-H777RC/H888RC
5-6. SCHEMATIC DIAGRAM  I/F Section 
(Page 28)
 31   32