procedurę conv_to_BCD ( signal ten : in std_logic_vector (9 downto 0); signal bcd : out std_logic_vector (3 downto 0)) is begin case ten is when "0000000010" => bcd <= "0001" when “0000000100” => bcd <= "0010" when "0000001000" => bcd <= "0011" when "0000010000" => bcd <= "0100" when "0000100000" => bcd <= "0101" when "0001000000" => bcd <= "0110" when "0010000000" => bcd <= "0111" when "0100000000" => bcd <= "1000" when "1000000000" => bcd <= "1001" when others => bcd <= "0000"; end case; end conv_to_BCD; Jednobitowy komparator opisuje się dwuargumentową funkcją XNOR: entity kompl is port(p,q : in std_logic; y : out std_logic); end kompl; architecture al of kompl is begin y <= p xnor q;
end al; KONWERTER KODU BIN/BCD library ieee; use ieee.std_logic_1164.all; entity binl ia port( bin: in std_logic_vector(4 downto 0); digl: out std_logic__vector (3 downto 0); dig2: out std_logic_vector(l downto 0)); end binl; use ieee.numeric_std.all; architecture behavioral of binl is begin process(bin) variable bin_var: unsigned(4 downto 0); begin bin_var := unsigned(bin); if bin_var < 10 then dig2 <= "00"; elsif bin_var < 20 then bin_var := bin_var - 10; dig2 <= "01"; elsif bin_var < 30 then bin_var := bin_var - 20; dig2 <= "10"; else bin_var := bin_var - 30; dig2 <= "11" ; end i f; digl <= std__logic_vector (bin_var (3 downto 0)); end process; end; licznik modulo 10 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity CNT is port( UP,DOWN,C,R: in std_logic; Q: inout std_logic_vector(3 downto 0) BORROW,CARRY: OUt Std_logic ); end; architecture beh of CNT is signal F: std_logic_vector(l downto 0); begin F<=UP&DOWN; process(C,R) variable Q_int: unsigned(3 downto 0); begin if R='l' then Q_int:="0000"; elsif rising_edge(C) then case F is when "10" => if Q_int<"1001" then Q_int:=Q_int+l; else Q_int:="0000"; end if; when "01" => if Q_int>"0000" then Q_int:=Q_int-l; else Q_int:="1001"; end if; when others => Q_int:=Q_int; end case; end if; Q<=std_logic_vector(Q_int); end process; CARRY<='1' when (Q="1001" and F="10") else 'O'; BORROW<='1' when (Q="0000" and F="01") else 'O'; end: MODULO 256 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity MOD256 is port( C,EN,R: in std_logic; Q: out std_logic_vector(7 downto 0) end; architecture beh of MOD256 is signal x: std_logic_vector(l downto 0); begin process(C,R) variable Q_int: unsigned(7 downto O); begin if R='l' then Q_int:=(others=>'O'); elsif rising_edge(C) then x<=x(0)&EN; -- synchronizator if x(l)='!' then Q_int:=Q_int+l; end i f; end if; Q<=std_logic_vector(Q_int); end process; end;
|
library IEEE; uae lEEE.std_logic_1164.all; entity JEDEN is port( C,EN,R: in std_logic; Q: inout std_logic_vector(7 downto 0) ); end; architecture beh of JEDEN is signal x: std_logic_vector(l downto O); begin process(C,R) begin if R='l' then Q< = "00000001" ; elsif rising_edge(C) then x<=x(0)&EN; -- synchronizator if x(l)='l' then Q<=Q(6 downto 0)&Q(7); -- przesuw end if; end if; end process; end; SYNCHRONIZATOR library ieee; use ieee.std_logic_1164.all; entity synch is port(ASYNC, C : in std_logic; SYNC : out std_logic); end synch; architecture shift_reg of synch is -- signal pomocniczy tq signal tq : std_logic_vector(l downto 0) begin process (C) begin if rising_edge (C) then tq <= ASYNC & tq(l); end if; end process; SYNC <= tq(0); end shift_reg;
LICZNIK REWERSYJNY 8 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cntnbrev is generic (N: positive := 8); -- deklaracja N = 8 bit port(C, R, ENCNT, DIR : in std_logic; Q : out std_logic_vector(N-l downto O)); end cntnbrev; architecture cnt_rev of cntnbrev is signal cnt: std_logic_vector(N-l downto 0); begin process (C, R, DIR) begin if R = 'O' then -- zerowanie asynchroniczne cnt <= (others => ' O ' ) ; elsif rising_edge(C) then if ENCNT = 'l' then -- zezwolenie na liczenie case DIR is -- granice liczenia ustala parametr N = 8 -- operacja cnt - l jest wykonywana -- w kodzie U2 when 'l1 => cnt <= cnt + 1; when 'O' => cnt <= cnt - 1; when others => null; end case; end if; --ENCNT = 'O1 'pamiętanie poprzed. stanu end if; end process; Q <= cnt; end cnt_rev; DETEKTOR library IEEE; use IEEE.std_logic_1164.all; entity detlOlO is port (x,reset: in std_logic; clk: in std_logic; y: out std_logic); end detlOlO; architecture detlOlOarch of detlOlO is type stan is (sO, sl, s2, s3, s4); signal s : stan; begin stany: process (clk, x, reset) begin if reset='l' then s<=sO; elsif rising_edge(clk) then case s is when s O = > if x='O' then s<=sO; else s<=sl; end i f; when sl=> if x='l' then s<=sl; else s<=s2; end if; when s2=> if x='l' then s<=s3; else s<=sO; end if; when s 3 = > if x='O' then s<=s4; else s<=sl; end i f; when s 4 = > if x='l' then s<=sl; else s<=sO; end if; end case; end i f; end process; wyjścia : process (s) begin case s is when sO=> y<='O'; when sl=> y<='O'; when s2=> y<='O'; when s3=> y<='O'; when s 4 = > y< ='l' ; end case; end process; end detlOlOarch;
|