^T i (ć) > Vr-fh
cljbtyunosci' fotJodu-y^ ?Ł ^s± \ a/e /)/je2 cg ty -łtn cg&s mus) £>yc
Tl
Vr* - £ Vos = O
■ Vj4 -
$11,Hm ~ CU
Tupe
TP
\
T.-H *l ^ & V /
?
eomckid / '70'2c,
460 Chaptor 8: Synchronous nMOS Logic
B
C
Logic diagram (a)
G = ł'r 9 Ez
4r-o
♦i
nMOS Circuit implementation (b)
FIGURĘ 8.17 Clocked AOI and combinational logie gatc arrangement.