EUWiP / MECHATRONIKA
Figurę 46. Guard Ring Layout and Connections to Reduce PC Board Leakage Currents
Figurę 47. Top View of AD8572 SOIC Layout with Guard Rings
CTeadENT
COPPER
TRACĘ
IF TA111*2, THEN Vts1 + VSC1 ¥ VTS2 + VSC2
Av=1 + (Rf'Ri)
NOTĘ: Rs SHOULD BE PLACED IN CLOSE PROXIMITY AND ALIGNMENT TO R, TO BALANCE SEEBECK VOLTAGES
Figurę 48. Mismatch in Seebeck Voltages Causes a Thermoelectric Voltage Error
Figurę 49. Using Dummy Components to Cancel Thermoelectric Voltage Errors
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