♦ DMA contro 11 er
— Four fully progranimable cliaiinels: two support external reąuests ancl external a ckn owi e d ge s
— Dual-address and single-addresstransfer supportwitli 8-? 16-, and 32-bitdata capability
— Source/destination address pointers tliat ean increment or reniain constant
— 24-bit transfer counter per cliannel
— Operand packing and unpaeking supported
—Auto-a li gnme nt transfer s suppoi*tedfor efficient błock movement
— Bursting and cycle steal support
— Two-bus-clock internal a ccess
—Automatic DMA transfers from 011-cliip UARTs using internal interrupts ♦ DRAM controller
— Synchronous DRAM (SDRAM), extended-data-out (EDO) DRAM, and fast page modę suppoii:
— Up to 512: Mbytes of DRAM
— Progranimable timer provides CAS-before-RAS refreslifor asynclironous DRAMs
— Suppoii: for two separate memoryblocks