TABLE 8 - FREOUENCY COMPARlSON MODĘ
Modę |
Bit 3 |
Bit 4 |
Control Reg. Bit 5 |
Counter Initialization |
Counter Enable Flip-Flop Set ICE) |
Counter Enable Flip-Flop Reset łCEł |
Interrupt Flag Set (I) |
Freguency |
1 |
0 |
0 |
G* *|« iCt+TOI+R |
G l |
W + R +1 |
G1 Bofore TO |
Corrpanson |
1 |
0 |
1 |
Gl.T+R |
Gł • |
W+R + l |
TO Befcre Gi |
Pulse Width |
1 |
1 |
0 |
"5*1 • 1 + R |
G1 W*R*I |
W + R + l+G |
Gt Before TO |
Companson |
1 |
1 |
1 |
G1 • + R |
G • • W • R • 1 |
W + R 1 + G |
TO Before (Tf |
Gł = Negaiive trarsnion o‘ Gate mpu:
W =Write Timer Latches Command. _
R =Timer Reset (CR‘iO = I or £xi9rna! RESET = 01 N = 16-Bit Number in Counter Latch TO = Counter Time Out (Ali Zerc Condition)
I = Interrypt for a given timer.
'Ali time intervals shown above assume tbe Gate (G) and Clock iC) signals are sycnhronized to the system doi (Eł with the speofied setup and hołd time requ>rements