♦Harvard arcliitecture memorv system witli i6-Kb\1e
♦ % «
iiistrnctioii caclie and 8-Kbvte data caclie ♦Two, 2-Kbyte oii-cliip SRAMs
♦Integer/iractional multiply-accumulate flVLVC) unit ♦Divide unit
♦System debug interface
•DRAM controller for synclironous and asvnclironous DRAM •Four-cliannel DMAl controller ♦Two general-purpose tiiners
♦Two UARTs, one tliat supports synclironous operationsfeC™ interface
♦Parallel I/O interface
♦System integration module (SEYI)