38236 PLD26

VECTOR COUNT := [ QD QC QB QA ] TRACE_ON ENA CLK QD QC QB QA SETF ENA CLK PRLDF QA QB /QC /QD

FOR X : = 0 BEGIN	TO 5	DO
CLOCKF END SETF /ENA	CLK
FOR X := 0 BEGIN	TO 3	DO
CLOCKF END SETF ENA	CLK
FOR X := 0 BEGIN	TO 9	DO
CLOCKF END TRACĘ OFF	CLK
FOR X := 0 BEGIN	TO 4	DO
CLOCKF END	CLK

INTEL Logic Optimizing Compiler Utilization Report'*    LICZNIK4.rpt

***** Design implemented successfully ; SCEMAT WEJSC I WYJSC UKŁADU NA PODSTAWIE OPISU

WARNING 4203-FIT: Non-Zero preload used for this PLD!

The 85C220 PLD registers power-up to ’0’, and preload must match this.

Incorrect registers: QA, QB

Yectors in the JEDEC file are truncated from the PRLDF statement.

85C220

CLK -	1	20	- Vcc
ENA -	2	1 9	- Gnd
Gnd -	3	18	- Gnd
Gnd -	4	1 7	- Gnd
Gnd ■ -	5	1 6	- Gnd
Gnd -	6	1 5	- QA
Gnd -	7	1 4	- QB
Gnd -	8	1 3	- QC
Gnd -	9	1 2	- QD
GND -	1 0	1 1	- Gnd

Gnd = unused input or 1/0 pin. N.C. = unconnected pins

CMOS Device:    ground unused inputs and I/Os

RESERVED = Leave pins unconnected on board.