Lock bits
BLB1 Model
|Mode1 3 |BLB0Model ^ No lock Boot Loader section
Fuse bits
W SPI Enable W WDTON
r~ BOOTRST V Reset Disable
r EESAVE
| Int RCosc, Frequency 1 MHz ▼
| Startup: 64ms + 6 CK ▼
| No BOD function ▼ | Boot błock 1024 Words ▼
Read
Write
Chip E rasę
Device signature |
1E 94 03 | |
T arget board |
AVR ISP | |
T arget SW rev. |
3.8 | |
Calibration byte |
0xD0 |
Close |