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��CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A EZ-USB� FX2LP"! USB Microcontroller High-Speed USB Peripheral Controller EZ-USB FX2LP"! USB Microcontroller High Speed USB Peripheral Controller Features �% USB 2.0 USB IF high speed certified (TID # 40460272) �% 3.3 V operation with 5 V tolerant inputs �% Single chip integrated USB 2.0 transceiver, smart SIE, and �% Vectored USB interrupts and GPIF/FIFO interrupts enhanced 8051 microprocessor �% Separate data buffers for the setup and data portions of a �% Fit, form, and function compatible with the FX2 CONTROL transfer P' Pin compatible �% Integrated I2C controller, runs at 100 or 400 kHz P' Object code compatible �% Four integrated FIFOs P' Functionally compatible (FX2LP is a superset) P' Integrated glue logic and FIFOs lower system cost �% Ultra low power: ICC No more than 85 mA in any mode P' Automatic conversion to and from 16-bit buses P' Ideal for bus and battery powered applications P' Master or slave operation �% Software: 8051 code runs from: P' Uses external clock or asynchronous strobes P' Internal RAM, which is downloaded through USB P' Easy interface to ASIC and DSP ICs P' Internal RAM, which is loaded from EEPROM �% Available in commercial and industrial temperature grade P' External memory device (128 pin package) (all packages except VFBGA) �% 16 KB of on-chip code/data RAM Features (CY7C68013A/14A only) �% Four programmable BULK, INTERRUPT, and �% CY7C68014A: Ideal for Battery Powered Applications ISOCHRONOUS endpoints P' Suspend current: 100 m�A (typ) P' Buffering options: Double, triple, and quad �% CY7C68013A: Ideal for Non Battery Powered Applications �% Additional programmable (BULK/INTERRUPT) 64-byte P' Suspend current: 300 m�A (typ) endpoint �% Available in Five Pb-free Packages with Up to 40 GPIOs �% 8-bit or 16-bit external data interface P' 128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs), 56-pin �% Smart media standard ECC generation QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin VFBGA (24 GPIOs) �% GPIF (general programmable interface) P' Enables direct connection to most parallel interfaces Features (CY7C68015A/16A only) P' Programmable waveform descriptors and configuration �% CY7C68016A: Ideal for Battery Powered Applications registers to define waveforms P' Suspend current: 100 m�A (typ) P' Supports multiple ready (RDY) inputs and Control (CTL) outputs �% CY7C68015A: Ideal for Non Battery Powered Applications �% Integrated, industry standard enhanced 8051 P' Suspend current: 300 m�A (typ) P' 48 MHz, 24 MHz, or 12 MHz CPU operation �% Available in Pb-free 56-pin QFN Package (26 GPIOs) P' Four clocks per instruction cycle �% Two more GPIOs than CY7C68013A/14A enabling additional P' Two USARTs features in same footprint P' Three counter/timers P' Expanded interrupt system P' Two data pointers Cypress Semiconductor Corporation " 198 Champion Court " San Jose, CA 95134-1709 " 408-943-2600 Document #: 38-08032 Rev. *V Revised February 7, 2012 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Logic Block Diagram High performance micro 24 MHz using standard tools Ext. XTAL with lower-power options FX2LP /0.5 I2C 8051 Core x20 Master VCC /1.0 12/24/48 MHz, PLL /2.0 four clocks/cycle Abundant I/O Additional I/Os (24) 1.5k including two USARTs connected for full speed General ADDR (9) programmable I/F D+ to ASIC/DSP or bus GPIF USB standards such as CY 16 KB RDY (6) 2.0 CTL (6) ATAPI, EPP, etc. D Smart RAM ECC XCVR USB Integrated 1.1/2.0 full speed and Engine Up to 96 MBytes/s high speed 4 kB 8/16 burst rate XCVR FIFO Enhanced USB core Soft Configuration FIFO and endpoint memory Simplifies 8051 code Easy firmware changes (master or slave operation) Cypress s EZ-USB� FX2LP�� (CY7C68013A/14A) is a low than USB 2.0 SIE or external transceiver implementations. With power version of the EZ-USB FX2�� (CY7C68013), which is a EZ-USB FX2LP, the Cypress Smart SIE handles most of the highly integrated, low power USB 2.0 microcontroller. By USB 1.1 and 2.0 protocol in hardware, freeing the embedded integrating the USB 2.0 transceiver, serial interface engine (SIE), microcontroller for application specific functions and decreasing enhanced 8051 microcontroller, and a programmable peripheral development time to ensure USB compatibility. interface in a single chip, The General Programmable Interface (GPIF) and Master/Slave Cypress has created a cost effective solution that provides Endpoint FIFO (8-bit or 16-bit data bus) provides an easy and superior time-to-market advantages with low power to enable glueless interface to popular interfaces such as ATA, UTOPIA, bus powered applications. EPP, PCMCIA, and most DSP/processors. The ingenious architecture of FX2LP results in data transfer The FX2LP draws less current than the FX2 (CY7C68013), has rates of over 53 Mbytes per second, the maximum allowable double the on-chip code/data RAM, and is fit, form and function USB 2.0 bandwidth, while still using a low cost 8051 compatible with the 56, 100, and 128 pin FX2. microcontroller in a package as small as a 56 VFBGA (5 mm x 5 Five packages are defined for the family: 56 VFBGA, 56 SSOP, mm). Because it incorporates the USB 2.0 transceiver, the 56 QFN, 100 TQFP, and 128 TQFP. FX2LP is more economical, providing a smaller footprint solution Document #: 38-08032 Rev. *V Page 2 of 66 Data (8) Address (16) Address (16) / Data Bus (8) CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Contents Applications ...................................................................... 4 Data Memory Read ................................................... 40 Functional Overview ........................................................ 4 Data Memory Write ................................................... 41 USB Signaling Speed .................................................. 4 PORTC Strobe Feature Timings ............................... 42 8051 Microprocessor ................................................... 4 GPIF Synchronous Signals ....................................... 43 I2C Bus ........................................................................ 4 Slave FIFO Synchronous Read ................................. 44 Buses .......................................................................... 4 Slave FIFO Asynchronous Read ............................... 45 USB Boot Methods ...................................................... 5 Slave FIFO Synchronous Write ................................. 46 ReNumeration ............................................................. 5 Slave FIFO Asynchronous Write ............................... 47 Bus-Powered Applications .......................................... 5 Slave FIFO Synchronous Packet End Strobe ........... 47 Interrupt System .......................................................... 5 Slave FIFO Asynchronous Packet End Strobe ......... 48 Reset and Wakeup ...................................................... 7 Slave FIFO Output Enable ........................................ 49 Program/Data RAM ..................................................... 8 Slave FIFO Address to Flags/Data ............................ 49 Register Addresses ................................................... 10 Slave FIFO Synchronous Address ............................ 49 Endpoint RAM ........................................................... 11 Slave FIFO Asynchronous Address .......................... 50 External FIFO Interface ............................................. 12 Sequence Diagram .................................................... 50 GPIF .......................................................................... 13 Ordering Information ...................................................... 55 ECC Generation[7] ................................................................... 13 Ordering Code Definitions ......................................... 55 USB Uploads and Downloads ................................... 13 Package Diagrams .......................................................... 56 Autopointer Access ................................................... 13 PCB Layout Recommendations .................................... 61 I2C Controller ............................................................. 14 Quad Flat Package No Leads (QFN) Package Compatible with Previous Generation EZ-USB FX2 . 14 Design Notes ................................................................... 62 CY7C68013A/14A and CY7C68015A/16A Differences 14 Acronyms ........................................................................ 63 Pin Assignments ............................................................ 15 Document Conventions ................................................. 63 CY7C68013A/15A Pin Descriptions .......................... 22 Units of Measure ....................................................... 63 Register Summary .......................................................... 30 Document History Page ................................................. 64 Absolute Maximum Ratings .......................................... 37 Sales, Solutions, and Legal Information ...................... 66 Operating Conditions ..................................................... 37 Worldwide Sales and Design Support ....................... 66 Thermal Characteristics ................................................. 37 Products .................................................................... 66 DC Characteristics ......................................................... 38 PSoC Solutions ......................................................... 66 USB Transceiver .......................................................38 AC Electrical Characteristics ........................................ 39 USB Transceiver .......................................................39 Program Memory Read ............................................. 39 Document #: 38-08032 Rev. *V Page 3 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 1. Applications Figure 2-1. Crystal Configuration �% Portable video recorder 24 MHz C1 C2 �% MPEG/TV conversion 12 pf 12 pf �% DSL modems �% ATA interface 20 � PLL �% Memory card readers �% Legacy conversion devices 12 pF capacitor values assumes a trace capacitance �% Cameras of 3 pF per side on a four-layer FR4 PCA �% Scanners The CLKOUT pin, which can be three-stated and inverted using �% Wireless LAN internal control bits, outputs the 50% duty cycle 8051 clock, at the selected 8051 clock frequency: 48 MHz, 24 MHz, or 12 MHz. �% MP3 players 2.2.2 USARTs �% Networking The Reference Designs section of the Cypress web site FX2LP contains two standard 8051 USARTs, addressed through Special Function Register (SFR) bits. The USART interface pins provides additional tools for typical USB 2.0 applications. Each reference design comes complete with firmware source and are available on separate I/O pins, and are not multiplexed with object code, schematics, and documentation. Visit port pins. www.cypress.com for more information. UART0 and UART1 can operate using an internal clock at 230 KBaud with no more than 1% baud rate error. 230 KBaud 2. Functional Overview operation is achieved by an internally derived clock source that generates overflow pulses at the appropriate time. The internal 2.1 USB Signaling Speed clock adjusts for the 8051 clock rate (48 MHz, 24 MHz, and 12 MHz) such that it always presents the correct frequency for FX2LP operates at two of the three rates defined in the USB Specification Revision 2.0, dated April 27, 2000: 230 KBaud operation.[1] �% Full speed, with a signaling bit rate of 12 Mbps 2.2.3 Special Function Registers Certain 8051 SFR addresses are populated to provide fast �% High speed, with a signaling bit rate of 480 Mbps access to critical FX2LP functions. These SFR additions are FX2LP does not support the low speed signaling mode of shown in Table 1 on page 5. Bold type indicates non standard, 1.5 Mbps. enhanced 8051 registers. The two SFR rows that end with 0 and 8 contain bit addressable registers. The four I/O ports A to 2.2 8051 Microprocessor D use the SFR addresses used in the standard 8051 for ports 0 The 8051 microprocessor embedded in the FX2LP family has to 3, which are not implemented in FX2LP. Because of the faster 256 bytes of register RAM, an expanded interrupt system, three and more efficient SFR addressing, the FX2LP I/O ports are not timer/counters, and two USARTs. addressable in external RAM space (using the MOVX instruction). 2.2.1 8051 Clock Frequency 2.3 I2C Bus FX2LP has an on-chip oscillator circuit that uses an external 24 MHz (�100 ppm) crystal with the following characteristics: FX2LP supports the I2C bus as a master only at 100/400 KHz. SCL and SDA pins have open-drain outputs and hysteresis �% Parallel resonant inputs. These signals must be pulled up to 3.3V, even if no I2C �% Fundamental mode device is connected. �% 500 m�W drive level 2.4 Buses �% 12 pF (5% tolerance) load capacitors All packages, 8-bit or 16-bit FIFO bidirectional data bus, multiplexed on I/O ports B and D. 128-pin package: adds 16-bit An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz, output-only 8051 address bus, 8-bit bidirectional data bus. as required by the transceiver/PHY and internal counters divide it down for use as the 8051 clock. The default 8051 clock frequency is 12 MHz. The clock frequency of the 8051 can be changed by the 8051 through the CPUCS register, dynamically. Note 1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a 1 for UART0, UART1, or both respectively. Document #: 38-08032 Rev. *V Page 4 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 1. Special Function Registers x 8x 9x Ax Bx Cx Dx Ex Fx 0 IOA IOB IOC IOD SCON1 PSW ACC B 1SP EXIF INT2CLR IOE SBUF1 2DPL0 MPAGE INT4CLR OEA 3 DPH0 OEB 4 DPL1 OEC 5 DPH1 OED 6 DPS OEE 7 PCON 8 TCON SCON0 IE IP T2CON EICON EIE EIP 9 TMOD SBUF0 ATL0 AUTOPTRH1 EP2468STAT EP01STAT RCAP2L BTL1 AUTOPTRL1 EP24FIFOFLGS GPIFTRIG RCAP2H CTH0reserved EP68FIFOFLGS TL2 DTH1 AUTOPTRH2 GPIFSGLDATH TH2 E CKCON AUTOPTRL2 GPIFSGLDATLX F reserved AUTOPTRSET-UP GPIFSGLDATLNOX Two control bits in the USBCS (USB Control and Status) register, 2.5 USB Boot Methods control the ReNumeration process: DISCON and RENUM. To During the power up sequence, internal logic checks the I2C port simulate a USB disconnect, the firmware sets DISCON to 1. To for the connection of an EEPROM whose first byte is either 0xC0 reconnect, the firmware clears DISCON to 0. or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM Before reconnecting, the firmware sets or clears the RENUM bit in place of the internally stored values (0xC0), or it boot-loads the to indicate whether the firmware or the Default USB Device EEPROM contents into internal RAM (0xC2). If no EEPROM is handles device requests over endpoint zero: if RENUM = 0, the detected, FX2LP enumerates using internally stored descriptors. Default USB Device handles device requests; if RENUM = 1, the The default ID values for FX2LP are VID/PID/DID (0x04B4, firmware services the requests. 0x8613, 0xAxxx where xxx = Chip revision).[2] Table 2. Default ID Values for FX2LP 2.7 Bus-Powered Applications Default VID/PID/DID The FX2LP fully supports bus powered designs by enumerating with less than 100 mA as required by the USB 2.0 specification. Vendor ID 0x04B4 Cypress Semiconductor Product ID 0x8613 EZ-USB FX2LP 2.8 Interrupt System Device release 0xAnnn Depends on chip revision (nnn = chip revision where first 2.8.1 INT2 Interrupt Request and Enable Registers silicon = 001) FX2LP implements an autovector feature for INT2 and INT4. There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF) vectors. See EZ-USB Technical Reference Manual (TRM) for 2.6 ReNumeration more details. Because the FX2LP s configuration is soft, one chip can take on the identities of multiple distinct USB devices. 2.8.2 USB Interrupt Autovectors When first plugged into USB, the FX2LP enumerates The main USB interrupt is shared by 27 interrupt sources. To automatically and downloads firmware and USB descriptor save the code and processing time that is required to identify the tables over the USB cable. Next, the FX2LP enumerates again, individual USB interrupt source, the FX2LP provides a second this time as a device defined by the downloaded information. level of interrupt vectoring, called Autovectoring. When a USB This patented two step process called ReNumeration�� happens interrupt is asserted, the FX2LP pushes the program counter to instantly when the device is plugged in, without a hint that the its stack, and then jumps to the address 0x0043 where it expects initial download step has occurred. to find a jump instruction to the USB Interrupt service routine. Note 2. The I2C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly. Document #: 38-08032 Rev. *V Page 5 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A The FX2LP jump instruction is encoded as follows: Table 3. INT2 USB Interrupts USB INTERRUPT TABLE FOR INT2 Priority INT2VEC Value Source Notes 1 00 SUDAV Setup data available 2 04 SOF Start of frame (or microframe) 3 08 SUTOK Setup token received 4 0C SUSPEND USB suspend request 5 10 USB RESET Bus reset 6 14 HISPEED Entered high speed operation 7 18 EP0ACK FX2LP ACK d the CONTROL Handshake 8 1C reserved 9 20 EP0-IN EP0-IN ready to be loaded with data 10 24 EP0-OUT EP0-OUT has USB data 11 28 EP1-IN EP1-IN ready to be loaded with data 12 2C EP1-OUT EP1-OUT has USB data 13 30 EP2 IN: buffer available. OUT: buffer has data 14 34 EP4 IN: buffer available. OUT: buffer has data 15 38 EP6 IN: buffer available. OUT: buffer has data 16 3C EP8 IN: buffer available. OUT: buffer has data 17 40 IBN IN-Bulk-NAK (any IN endpoint) 18 44 reserved 19 48 EP0PING EP0 OUT was pinged and it NAK d 20 4C EP1PING EP1 OUT was pinged and it NAK d 21 50 EP2PING EP2 OUT was pinged and it NAK d 22 54 EP4PING EP4 OUT was pinged and it NAK d 23 58 EP6PING EP6 OUT was pinged and it NAK d 24 5C EP8PING EP8 OUT was pinged and it NAK d 25 60 ERRLIMIT Bus errors exceeded the programmed limit 26 64 27 68 Reserved 28 6C Reserved 29 70 EP2ISOERR ISO EP2 OUT PID sequence error 30 74 EP4ISOERR ISO EP4 OUT PID sequence error 31 78 EP6ISOERR ISO EP6 OUT PID sequence error 32 7C EP8ISOERR ISO EP8 OUT PID sequence error If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP substitutes its INT2VEC byte. Therefore, if the high byte ( page ) of a jump table address is preloaded at the location 0x0044, the automatically inserted INT2VEC byte at 0x0045 directs the jump to the correct address out of the 27 addresses within the page. 2.8.3 FIFO/GPIF Interrupt (INT4) Just as the USB Interrupt is shared among 27 individual USB interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, similar to the USB Interrupt, can employ autovectoring. Table 4 on page 7 shows the priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources. Document #: 38-08032 Rev. *V Page 6 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 4. Individual FIFO/GPIF Interrupt Sources Priority INT4VEC Value Source Notes 1 80 EP2PF Endpoint 2 programmable flag 2 84 EP4PF Endpoint 4 programmable flag 3 88 EP6PF Endpoint 6 programmable flag 4 8C EP8PF Endpoint 8 programmable flag 5 90 EP2EF Endpoint 2 empty flag 6 94 EP4EF Endpoint 4 empty flag 7 98 EP6EF Endpoint 6 empty flag 8 9C EP8EF Endpoint 8 empty flag 9 A0 EP2FF Endpoint 2 full flag 10 A4 EP4FF Endpoint 4 full flag 11 A8 EP6FF Endpoint 6 full flag 12 AC EP8FF Endpoint 8 full flag 13 B0 GPIFDONE GPIF operation complete 14 B4 GPIFWF GPIF waveform If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP 5 ms after VCC reaches 3.0V. If the crystal input pin is driven by register), the FX 2LP substitutes its INT4VEC byte. Therefore, if a clock signal the internal PLL stabilizes in 200 m�s after VCC has the high byte ( page ) of a jump-table address is preloaded at reached 3.0V.[3] location 0x0054, the automatically inserted INT4VEC byte at Figure 2-2 on page 8 shows a power on reset condition and a 0x0055 directs the jump to the correct address out of the 14 reset applied during operation. A power on reset is defined as addresses within the page. When the ISR occurs, the FX2LP the time reset that is asserted while power is being applied to the pushes the program counter to its stack then jumps to address circuit. A powered reset is when the FX2LP powered on and 0x0053, where it expects to find a jump instruction to the ISR operating and the RESET# pin is asserted. Interrupt service routine. Cypress provides an application note which describes and recommends power on reset implementation. For more 2.9 Reset and Wakeup information about reset implementation for the FX2 family of 2.9.1 Reset Pin products visit http://www.cypress.com. The input pin, RESET#, resets the FX2LP when asserted. This pin has hysteresis and is active LOW. When a crystal is used with the CY7C680xxA the reset period must enable stabilization of the crystal and the PLL. This reset period must be approximately Note 3. If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200 m�s. Document #: 38-08032 Rev. *V Page 7 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 2-2. Reset Timing Plots RESET# RESET# VIL VIL 3.3V 3.3V 3.0V VCC VCC 0V 0V TRESET TRESET Power on Reset Powered Reset Table 2-1. Reset Timing Values 2.10 Program/Data RAM Condition TRESET 2.10.1 Size Power on reset with crystal 5 ms The FX2LP has 16 KBytes of internal program/data RAM, where PSEN#/RD# signals are internally ORed to enable the 8051 to Power on reset with external 200 m�s + Clock stability time access it as both program and data memory. No USB control clock registers appear in this space. Powered Reset 200 m�s Two memory maps are shown in the following diagrams: Figure 2-3 on page 9 shows the Internal Code Memory, EA = 0 2.9.2 Wakeup Pins Figure 2-4 on page 10 shows the External Code Memory, EA = 1. The 8051 puts itself and the rest of the chip into a power down mode by setting PCON.0 = 1. This stops the oscillator and PLL. 2.10.2 Internal Code Memory, EA = 0 When WAKEUP is asserted by external logic the oscillator This mode implements the internal 16 KByte block of RAM restarts after the PLL stabilizes, and the 8051 receives a wakeup (starting at 0) as combined code and data memory. When interrupt. This applies whether or not FX2LP is connected to the external RAM or ROM is added, the external read and write USB. strobes are suppressed for memory spaces that exist inside the The FX2LP exits the power down (USB suspend) state using one chip. This enables the user to connect a 64 KByte memory of the following methods: without requiring address decodes to keep clear of internal memory spaces. �% USB bus activity (if D+/D lines are left floating, noise on these lines may indicate activity to the FX2LP and initiate a wakeup) Only the internal 16 KBytes and scratch pad 0.5 KBytes RAM spaces have the following access: �% External logic asserts the WAKEUP pin �% USB download �% External logic asserts the PA3/WU2 pin �% USB upload The second wakeup pin, WU2, can also be configured as a general purpose I/O pin. This enables a simple external R-C �% Setup data pointer network to be used as a periodic wakeup source. WAKEUP is by default active LOW. �% I2C interface boot load. 2.10.3 External Code Memory, EA = 1 The bottom 16 KBytes of program memory is external and therefore the bottom 16 KBytes of internal RAM is accessible only as a data memory. Document #: 38-08032 Rev. *V Page 8 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 2-3. Internal Code Memory, EA = 0 Inside FX2LP Outside FX2LP FFFF 7.5 KBytes (OK to populate USB regs and 4K FIFO buffers data memory here RD#/WR# (RD#,WR#) strobes are not E200 E1FF active) 0.5 KBytes RAM Data (RD#,WR#)* E000 48 KBytes External 40 KBytes Code External Memory Data (PSEN#) Memory (RD#,WR#) 3FFF (Ok to populate (OK to populate data memory program 16 KBytes RAM here RD#/WR# memory here Code and Data strobes are not PSEN# strobe (PSEN#,RD#,WR#)* active) is not active) 0000 Data Code *SUDPTR, USB upload/download, I2C interface boot access Document #: 38-08032 Rev. *V Page 9 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 2-4. External Code Memory, EA = 1 Inside FX2LP Outside FX2LP FFFF 7.5 KBytes (OK to populate USB regs and data memory 4K FIFO buffers here RD#/WR# (RD#,WR#) strobes are not E200 active) E1FF 0.5 KBytes RAM Data (RD#,WR#)* E000 40 KBytes External 64 KBytes Data External Memory Code (RD#,WR#) Memory (PSEN#) 3FFF (Ok to populate 16 KBytes data memory RAM here RD#/WR# Data strobes are not (RD#,WR#)* active) 0000 Data Code *SUDPTR, USB upload/download, I2C interface boot access 2.11 Register Addresses FFFF 4 KBytes EP2-EP8 buffers (8 x 512) F000 EFFF 2 KBytes RESERVED E800 E7FF 64 Bytes EP1IN E7C0 E7BF 64 Bytes EP1OUT E780 E77F 64 Bytes EP0 IN/OUT E740 E73F 64 Bytes RESERVED E700 E6FF 8051 Addressable Registers (512) E500 E4FF Reserved (128) E480 E47F 128 bytes GPIF Waveforms E400 E3FF Reserved (512) E200 E1FF 512 bytes 8051 xdata RAM E000 Document #: 38-08032 Rev. *V Page 10 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 2.12.3 Setup Data Buffer 2.12 Endpoint RAM A separate 8 byte buffer at 0xE6B8-0xE6BF holds the setup data 2.12.1 Size from a CONTROL transfer. �% 3 � 64 bytes (Endpoints 0 and 1) 2.12.4 Endpoint Configurations (High Speed Mode) �% 8 � 512 bytes (Endpoints 2, 4, 6, 8) Endpoints 0 and 1 are the same for every configuration. Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can be either 2.12.2 Organization BULK or INTERRUPT. �% EP0 The endpoint buffers can be configured in any 1 of the 12 configurations shown in the vertical columns. When operating in �% Bidirectional endpoint zero, 64 byte buffer the full speed BULK mode only the first 64 bytes of each buffer �% EP1IN, EP1OUT are used. For example, in high speed, the max packet size is 512 bytes but in full speed it is 64 bytes. Even though a buffer is �% 64 byte buffers, bulk or interrupt configured to a 512 byte buffer, in full speed only the first 64 bytes �% EP2, 4, 6, 8 are used. The unused endpoint buffer space is not available for other operations. An example endpoint configuration is the �% Eight 512 byte buffers, bulk, interrupt, or isochronous. EP4 and EP2 1024 double buffered; EP6 512 quad buffered (column 8). EP8 can be double buffered; EP2 and 6 can be either double, triple, or quad buffered. For high speed endpoint configuration options, see Figure 2-5. Figure 2-5. Endpoint Configuration 64 64 64 64 EP0 IN&OUT 64 64 64 64 64 64 64 64 64 64 64 64 EP1 IN 64 64 64 64 64 64 64 64 64 64 64 64 EP1 OUT 64 64 64 64 64 64 64 64 EP2 EP2 EP2 EP2 EP2 EP2 EP2 EP2 EP2 EP2 EP2 EP2 512 512 512 512 512 512 512 1024 1024 1024 1024 512 512 512 512 512 512 512 1024 512 EP4 EP4 EP4 512 512 512 512 512 512 EP6 1024 1024 1024 1024 1024 512 512 512 512 512 512 512 EP6 EP6 EP6 EP6 EP6 EP6 EP6 EP6 EP6 512 1024 512 512 1024 1024 512 512 512 512 512 1024 1024 1024 512 512 512 512 512 512 EP8 EP8 EP8 EP8 EP8 512 512 1024 512 512 512 512 512 512 1024 1024 1024 512 512 512 512 512 512 512 512 9 10 11 12 4 5 8 1 2 3 6 7 Document #: 38-08032 Rev. *V Page 11 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 2.12.5 Default Full Speed Alternate Settings Table 5. Default Full Speed Alternate Settings[4, 5] Alternate Setting 0 1 2 3 ep0 64 64 64 64 ep1out 0 64 bulk 64 int 64 int ep1in 0 64 bulk 64 int 64 int ep2 0 64 bulk out (2�) 64 int out (2�) 64 iso out (2�) ep4 0 64 bulk out (2�) 64 bulk out (2�) 64 bulk out (2�) ep6 0 64 bulk in (2�) 64 int in (2�) 64 iso in (2�) ep8 0 64 bulk in (2�) 64 bulk in (2�) 64 bulk in (2�) 2.12.6 Default High Speed Alternate Settings Table 6. Default High Speed Alternate Settings[4, 5] Alternate Setting 0 1 2 3 ep0 64 64 64 64 ep1out 0 512 bulk[6] 64 int 64 int ep1in 0 512 bulk[6] 64 int 64 int ep2 0 512 bulk out (2�) 512 int out (2�) 512 iso out (2�) ep4 0 512 bulk out (2�) 512 bulk out (2�) 512 bulk out (2�) ep6 0 512 bulk in (2�) 512 int in (2�) 512 iso in (2�) ep8 0 512 bulk in (2�) 512 bulk in (2�) 512 bulk in (2�) domain. The blocks can be configured as single, double, triple, 2.13 External FIFO Interface or quad buffered as previously shown. 2.13.1 Architecture The I/O control unit implements either an internal master (M for The FX2LP slave FIFO architecture has eight 512 byte blocks in master) or external master (S for Slave) interface. the endpoint RAM that directly serve as FIFO memories and are In Master (M) mode, the GPIF internally controls FIFOADR[1..0] controlled by FIFO control signals (such as IFCLK, SLCS#, to select a FIFO. The RDY pins (two in the 56-pin package, six SLRD, SLWR, SLOE, PKTEND, and flags). in the 100-pin and 128-pin packages) can be used as flag inputs In operation, some of the eight RAM blocks fill or empty from the from an external FIFO or other logic if desired. The GPIF can be SIE, while the others are connected to the I/O transfer logic. The run from either an internally derived clock or externally supplied transfer logic takes two forms, the GPIF for internally generated clock (IFCLK), at a rate that transfers data up to 96 Megabytes/s control signals and the slave FIFO interface for externally (48 MHz IFCLK with 16-bit interface). controlled transfers. In Slave (S) mode, the FX2LP accepts either an internally derived clock or externally supplied clock (IFCLK, max frequency 2.13.2 Master/Slave Control Signals 48 MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals The FX2LP endpoint FIFOS are implemented as eight physically from external logic. When using an external IFCLK, the external distinct 256x16 RAM blocks. The 8051/SIE can switch any of the clock must be present before switching to the external clock with RAM blocks between two domains, the USB (SIE) domain and the IFCLKSRC bit. Each endpoint can individually be selected the 8051-I/O Unit domain. This switching is done virtually for byte or word operation by an internal configuration bit and a instantaneously, giving essentially zero transfer time between Slave FIFO Output Enable signal SLOE enables data of the USB FIFOS and Slave FIFOS. Because they are physically selected width. External logic must ensure that the output enable the same memory no bytes are actually transferred between signal is inactive when writing data to a slave FIFO. The slave buffers. interface can also operate asynchronously, where the SLRD and SLWR signals act directly as strobes, rather than a clock qualifier At any time, some RAM blocks are filling/emptying with USB data as in synchronous mode. The signals SLRD, SLWR, SLOE and under SIE control, while other RAM blocks are available to the PKTEND are gated by the signal SLCS#. 8051, the I/O control unit or both. The RAM blocks operate as single port in the USB domain, and dual port in the 8051-I/O Notes 4. 0 means not implemented. 5. 2� means double buffered. 6. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1. Document #: 38-08032 Rev. *V Page 12 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 2.13.3 GPIF and FIFO Clock Rates 2.15 ECC Generation[7] An 8051 register bit selects one of two frequencies for the The EZ-USB can calculate ECCs (Error Correcting Codes) on internally supplied interface clock: 30 MHz and 48 MHz. data that passes across its GPIF or Slave FIFO interfaces. There Alternatively, an externally supplied clock of 5 MHz 48 MHz are two ECC configurations: Two ECCs, each calculated over feeding the IFCLK pin can be used as the interface clock. IFCLK 256 bytes (SmartMedia Standard); and one ECC calculated over can be configured to function as an output clock when the GPIF 512 bytes. and FIFOs are internally clocked. An output enable bit in the The ECC can correct any one-bit error or detect any two-bit error. IFCONFIG register turns this clock output off, if desired. Another bit within the IFCONFIG register inverts the IFCLK signal 2.15.1 ECC Implementation whether internally or externally sourced. The two ECC configurations are selected by the ECCM bit: 2.14 GPIF ECCM = 0 The GPIF is a flexible 8-bit or 16-bit parallel interface driven by Two 3 byte ECCs, each calculated over a 256 byte block of data. a user programmable finite state machine. It enables the This configuration conforms to the SmartMedia Standard. CY7C68013A/15A to perform local bus mastering and can Write any value to ECCRESET, then pass data across the GPIF implement a wide variety of protocols such as ATA interface, or Slave FIFO interface. The ECC for the first 256 bytes of data printer parallel port, and Utopia. is calculated and stored in ECC1. The ECC for the next 256 bytes The GPIF has six programmable control outputs (CTL), nine is stored in ECC2. After the second ECC is calculated, the values address outputs (GPIFADRx), and six general-purpose ready in the ECCx registers do not change until ECCRESET is written inputs (RDY). The data bus width can be 8 or 16 bits. Each GPIF again, even if more data is subsequently passed across the vector defines the state of the control outputs, and determines interface. what state a ready input (or multiple inputs) must be before ECCM = 1 proceeding. The GPIF vector can be programmed to advance a FIFO to the next data value, advance an address, etc. A One 3 byte ECC calculated over a 512 byte block of data. sequence of the GPIF vectors make up a single waveform that Write any value to ECCRESET then pass data across the GPIF is executed to perform the desired data move between the or Slave FIFO interface. The ECC for the first 512 bytes of data FX2LP and the external device. is calculated and stored in ECC1; ECC2 is unused. After the ECC is calculated, the values in ECC1 do not change even if 2.14.1 Six Control OUT Signals more data is subsequently passed across the interface, till The 100-pin and 128-pin packages bring out all six Control ECCRESET is written again. Output pins (CTL0-CTL5). The 8051 programs the GPIF unit to define the CTL waveforms. The 56-pin package brings out three 2.16 USB Uploads and Downloads of these signals, CTL0 CTL2. CTLx waveform edges can be The core has the ability to directly edit the data contents of the programmed to make transitions as fast as once per clock (20.8 internal 16 KByte RAM and of the internal 512 byte scratch pad ns using a 48 MHz clock). RAM via a vendor specific command. This capability is normally used when soft downloading user code and is available only to 2.14.2 Six Ready IN Signals and from internal RAM, only when the 8051 is held in reset. The The 100-pin and 128-pin packages bring out all six Ready inputs available RAM spaces are 16 KBytes from 0x0000 0x3FFF (RDY0 RDY5). The 8051 programs the GPIF unit to test the (code/data) and 512 bytes from 0xE000 0xE1FF (scratch pad RDY pins for GPIF branching. The 56-pin package brings out two data RAM).[8] of these signals, RDY0 1. 2.17 Autopointer Access 2.14.3 Nine GPIF Address OUT Signals FX2LP provides two identical autopointers. They are similar to Nine GPIF address lines are available in the 100-pin and 128-pin the internal 8051 data pointers but with an additional feature: packages, GPIFADR[8..0]. The GPIF address lines enable they can optionally increment after every memory access. This indexing through up to a 512 byte block of RAM. If more address capability is available to and from both internal and external lines are needed I/O port pins are used. RAM. The autopointers are available in external FX2LP registers under control of a mode bit (AUTOPTRSET-UP.0). Using the 2.14.4 Long Transfer Mode external FX2LP autopointer access (at 0xE67B 0xE67C) In the master mode, the 8051 appropriately sets GPIF enables the autopointer to access all internal and external RAM transaction count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, to the part. or GPIFTCB0) for unattended transfers of up to 232 transactions. Also, the autopointers can point to any FX2LP register or The GPIF automatically throttles data flow to prevent under or endpoint buffer space. When autopointer access to external overflow until the full number of requested transactions memory is enabled, location 0xE67B and 0xE67C in XDATA and complete. The GPIF decrements the value in these registers to code space cannot be used. represent the current status of the transaction. Notes 7. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation. 8. After the data is downloaded from the host, a loader can execute from internal RAM to transfer downloaded data to external memory. Document #: 38-08032 Rev. *V Page 13 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A For designers migrating from the FX2 to the FX2LP a change in 2.18 I2C Controller the bill of material and review of the memory allocation (due to FX2LP has one I2C port that is driven by two internal controllers, increased internal memory) is required. For more information one that automatically operates at boot time to load VID/PID/DID about migrating from EZ-USB FX2 to EZ-USB FX2LP, see the and configuration information, and another that the 8051 uses application note titled Migrating from EZ-USB FX2 to EZ-USB when running to control external I2C devices. The I2C port FX2LP available in the Cypress web site. operates in master mode only. Table 8. Part Number Conversion Table 2.18.1 I2C Port Pins EZ-USB FX2 EZ-USB FX2LP Package The I2C pins SCL and SDA must have external 2.2 kW� pull up Part Number Part Number Description resistors even if no EEPROM is connected to the FX2LP. CY7C68013-56PVC CY7C68013A-56PVXC or 56-pin External EEPROM device address pins must be configured CY7C68014A-56PVXC SSOP properly. See Table 7 for configuring the device address pins. CY7C68013-56PVCT CY7C68013A-56PVXCT or 56-pin Table 7. Strap Boot EEPROM Address Lines to These Values CY7C68014A-56PVXCT SSOP Bytes Example EEPROM A2 A1 A0 Tape and Reel 16 24LC00[9] N/A N/A N/A CY7C68013-56LFC CY7C68013A-56LFXC or 56-pin QFN 128 24LC01 0 0 0 CY7C68014A-56LFXC 256 24LC02 0 0 0 CY7C68013-100AC CY7C68013A-100AXC or 100-pin 4K 24LC32 0 0 1 CY7C68014A-100AXC TQFP 8K 24LC64 0 0 1 CY7C68013-128AC CY7C68013A-128AXC or 128-pin CY7C68014A-128AXC TQFP 16K 24LC128 0 0 1 2.18.2 I2C Interface Boot Load Access 2.20 CY7C68013A/14A and CY7C68015A/16A At power on reset the I2C interface boot loader loads the Differences VID/PID/DID configuration bytes and up to 16 KBytes of CY7C68013A is identical to CY7C68014A in form, fit, and program/data. The available RAM spaces are 16 KBytes from functionality. CY7C68015A is identical to CY7C68016A in form, 0x0000 0x3FFF and 512 bytes from 0xE000 0xE1FF. The 8051 fit, and functionality. CY7C68014A and CY7C68016A have a is in reset. I2C interface boot loads only occur after power on lower suspend current than CY7C68013A and CY7C68015A reset. respectively and are ideal for power sensitive battery applications. 2.18.3 I2C Interface General-Purpose Access CY7C68015A and CY7C68016A are available in 56-pin QFN The 8051 can control peripherals connected to the I2C bus using package only. Two additional GPIO signals are available on the the I2CTL and I2DAT registers. FX2LP provides I2C master CY7C68015A and CY7C68016A to provide more flexibility when control only, it is never an I2C slave. neither IFCLK or CLKOUT are needed in the 56-pin package. 2.19 Compatible with Previous Generation USB developers wanting to convert their FX2 56-pin application EZ-USB FX2 to a bus-powered system directly benefit from these additional signals. The two GPIOs give developers the signals they need The EZ-USB FX2LP is form, fit and with minor exceptions for the power control circuitry of their bus-powered application functionally compatible with its predecessor, the EZ-USB FX2. without pushing them to a high pincount version of FX2LP. This makes for an easy transition for designers wanting to upgrade their systems from the FX2 to the FX2LP. The pinout The CY7C68015A is only available in the 56-pin QFN package and package selection are identical and a vast majority of Table 9. CY7C68013A/14A and CY7C68015A/16A firmware previously developed for the FX2 functions in the Pin Differences FX2LP. CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A IFCLK PE0 CLKOUT PE1 Note 9. This EEPROM does not have address pins. Document #: 38-08032 Rev. *V Page 14 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 3. Pin Assignments Figure 3-1 on page 16 identifies all signals for the five package The 128-pin package adds the 8051 address and data buses types. The following pages illustrate the individual pin diagrams, plus control signals. Note that two of the required signals, RD# plus a combination diagram showing which of the full set of and WR#, are present in the 100-pin version. signals are available in the 128-pin, 100-pin, and 56-pin In the 100-pin and 128-pin versions, an 8051 control bit can be packages. set to pulse the RD# and WR# pins when the 8051 reads The signals on the left edge of the 56-pin package in Figure 3-1 from/writes to PORTC. This feature is enabled by setting on page 16 are common to all versions in the FX2LP family with PORTCSTB bit in CPUCS register. the noted differences between the CY7C68013A/14A and the Section 9.5 displays the timing diagram of the read and write CY7C68015A/16A. strobing function on accessing PORTC. Three modes are available in all package versions: Port, GPIF master, and Slave FIFO. These modes define the signals on the right edge of the diagram. The 8051 selects the interface mode using the IFCONFIG[1:0] register bits. Port mode is the power on default configuration. The 100-pin package adds functionality to the 56-pin package by adding these pins: �% PORTC or alternate GPIFADR[7:0] address signals �% PORTE or alternate GPIFADR[8] address signal and seven additional 8051 signals �% Three GPIF Control signals �% Four GPIF Ready signals �% Nine 8051 signals (two USARTs, three timer inputs, INT4,and INT5#) �% BKPT, RD#, WR#. Document #: 38-08032 Rev. *V Page 15 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 3-1. Signal Port GPIF Master Slave FIFO PD7 FD[15] FD[15] PD6 FD[14] FD[14] PD5 FD[13] FD[13] PD4 FD[12] FD[12] PD3 FD[11] FD[11] PD2 FD[10] FD[10] PD1 FD[9] FD[9] PD0 FD[8] FD[8] PB7 FD[7] FD[7] PB6 FD[6] FD[6] PB5 FD[5] FD[5] XTALIN PB4 FD[4] FD[4] XTALOUT PB3 FD[3] FD[3] RESET# PB2 FD[2] FD[2] WAKEUP# PB1 FD[1] FD[1] PB0 FD[0] FD[0] SCL 56 SDA RDY0 SLRD RDY1 SLWR **PE0 replaces IFCLK & PE1 replaces CLKOUT CTL0 FLAGA on CY7C68015A/16A CTL1 FLAGB CTL2 FLAGC **PE0 **PE1 INT0#/PA0 INT0#/PA0 INT0#/ PA0 INT1#/PA1 INT1#/PA1 INT1#/ PA1 IFCLK PA2 PA2 SLOE CLKOUT WU2/PA3 WU2/PA3 WU2/PA3 DPLUS PA4 PA4 FIFOADR0 DMINUS PA5 PA5 FIFOADR1 PA6 PA6 PKTEND PA7 PA7 PA7/FLAGD/SLCS# CTL3 CTL4 CTL5 RDY2 RDY3 RDY4 100 RDY5 BKPT PORTC7/GPIFADR7 PORTC6/GPIFADR6 PORTC5/GPIFADR5 PORTC4/GPIFADR4 RxD0 PORTC3/GPIFADR3 TxD0 PORTC2/GPIFADR2 RxD1 PORTC1/GPIFADR1 TxD1 PORTC0/GPIFADR0 INT4 INT5# PE7/GPIFADR8 T2 PE6/T2EX T1 PE5/INT6 T0 PE4/RxD1OUT PE3/RxD0OUT PE2/T2OUT RD# PE1/T1OUT PE0/T0OUT WR# D7 CS# D6 OE# D5 PSEN# D4 D3 A15 D2 A14 D1 A13 D0 A12 A11 A10 A9 128 A8 A7 A6 A5 A4 EA A3 A2 A1 A0 Document #: 38-08032 Rev. *V Page 16 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 3-2. CY7C68013A/CY7C68014A 128-Pin TQFP Pin Assignment 1 102 CLKOUT PD0/FD8 2 101 VCC *WAKEUP 3 100 GND VCC 4 99 RDY0/*SLRD RESET# 5 98 RDY1/*SLWR CTL5 6 97 RDY2 A3 7 96 RDY3 A2 8 95 RDY4 A1 9 94 RDY5 A0 10 93 AVCC GND 11 92 XTALOUT PA7/*FLAGD/SLCS# 12 91 XTALIN PA6/*PKTEND 13 90 AGND PA5/FIFOADR1 14 89 NC PA4/FIFOADR0 15 88 NC D7 16 87 NC D6 17 86 AVCC D5 18 85 DPLUS CY7C68013A/CY7C68014A PA3/*WU2 19 84 DMINUS 128-pin TQFP PA2/*SLOE 20 83 AGND PA1/INT1# 21 82 A11 PA0/INT0# 22 81 A12 VCC 23 80 A13 GND 24 79 A14 PC7/GPIFADR7 25 78 A15 PC6/GPIFADR6 26 77 VCC PC5/GPIFADR5 27 76 GND PC4/GPIFADR4 28 75 INT4 PC3/GPIFADR3 29 74 T0 PC2/GPIFADR2 30 73 T1 PC1/GPIFADR1 31 72 T2 PC0/GPIFADR0 32 71 *IFCLK CTL2/*FLAGC 33 70 RESERVED CTL1/*FLAGB 34 69 BKPT CTL0/*FLAGA 35 68 EA VCC 36 67 SCL CTL4 37 66 SDA CTL3 38 65 OE# GND * denotes programmable polarity Document #: 38-08032 Rev. *V Page 17 of 66 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 PE6/T2EX 113 PE5/INT6 112 PE4/RXD1OUT 111 PE3/RXD0OUT 110 PE2/T2OUT 109 PE1/T1OUT 108 PE0/T0OUT 107 VCC 106 INT5# 105 PD3/FD11 104 PD2/FD10 103 A10 A9 A8 GND PD7/FD15 PD6/FD14 PD5/FD13 PD4/FD12 A7 A6 A5 A4 GND PE7/GPIFADR8 PD1/FD9 PB0/FD0 44 PB1/FD1 45 PB2/FD2 46 PB3/FD3 47 PB4/FD4 PB5/FD5 PB6/FD6 PB7/FD7 PSEN# RXD0 RXD1 TXD0 50 TXD1 WR# 41 GND 49 GND VCC 43 VCC 48 VCC RD# 40 CS# 42 D0 D1 D2 D3 D4 39 51 52 53 54 55 56 57 58 59 60 61 62 63 64 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 3-3. CY7C68013A/CY7C68014A 100-Pin TQFP Pin Assignment 1 VCC PD0/FD8 80 2 GND *WAKEUP 79 3 RDY0/*SLRD VCC 78 4 RDY1/*SLWR RESET# 77 5 RDY2 CTL5 76 6 RDY3 GND 75 7 RDY4 PA7/*FLAGD/SLCS# 74 8 RDY5 PA6/*PKTEND 73 9 AVCC PA5/FIFOADR1 72 10 XTALOUT PA4/FIFOADR0 71 11 XTALIN PA3/*WU2 70 12 AGND PA2/*SLOE 69 13 NC PA1/INT1# 68 14 NC PA0/INT0# 67 15 CY7C68013A/CY7C68014A NC VCC 66 16 100-pin TQFP 65 AVCC GND 17 DPLUS PC7/GPIFADR7 64 18 DMINUS PC6/GPIFADR6 63 19 AGND PC5/GPIFADR5 62 20 VCC PC4/GPIFADR4 61 21 GND PC3/GPIFADR3 60 22 INT4 PC2/GPIFADR2 59 23 T0 PC1/GPIFADR1 58 24 T1 PC0/GPIFADR0 57 25 T2 CTL2/*FLAGC 56 26 *IFCLK CTL1/*FLAGB 55 27 RESERVED CTL0/*FLAGA 54 28 BKPT VCC 53 29 SCL CTL4 52 30 SDA CTL3 51 * denotes programmable polarity Document #: 38-08032 Rev. *V Page 18 of 66 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CLKOUT GND PD7/FD15 PD6/FD14 PD5/FD13 PD4/FD12 GND PE7/GPIFADR8 PE6/T2EX PE5/INT6 PE4/RXD1OUT PE3/RXD0OUT PE2/T2OUT PE1/T1OUT PE0/T0OUT VCC INT5# PD3/FD11 PD2/FD10 PD1/FD9 PB0/FD0 34 PB1/FD1 35 PB2/FD2 36 PB3/FD3 37 PB4/FD4 PB5/FD5 PB6/FD6 PB7/FD7 RXD0 41 RXD1 43 TXD0 40 TXD1 42 WR# GND 39 GND GND VCC VCC 38 VCC RD# 31 32 33 44 45 46 47 48 49 50 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 3-4. CY7C68013A/CY7C68014A 56-Pin SSOP Pin Assignment CY7C68013A/CY7C68014A 56-pin SSOP 1 56 PD5/FD13 PD4/FD12 2 55 PD6/FD14 PD3/FD11 3 54 PD7/FD15 PD2/FD10 4 53 GND PD1/FD9 5 52 CLKOUT PD0/FD8 6 51 VCC *WAKEUP 7 50 GND VCC 8 49 RDY0/*SLRD RESET# 9 48 RDY1/*SLWR GND 10 47 AVCC PA7/*FLAGD/SLCS# 11 46 XTALOUT PA6/PKTEND 12 45 XTALIN PA5/FIFOADR1 13 44 AGND PA4/FIFOADR0 14 43 AVCC PA3/*WU2 15 42 DPLUS PA2/*SLOE 16 41 DMINUS PA1/INT1# 17 40 AGND PA0/INT0# 18 39 VCC VCC 19 38 GND CTL2/*FLAGC 20 37 *IFCLK CTL1/*FLAGB 21 36 RESERVED CTL0/*FLAGA 22 35 SCL GND 23 34 SDA VCC 24 33 VCC GND 25 32 PB0/FD0 PB7/FD7 26 31 PB1/FD1 PB6/FD6 27 30 PB2/FD2 PB5/FD5 28 29 PB3/FD3 PB4/FD4 * denotes programmable polarity Document #: 38-08032 Rev. *V Page 19 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 3-5. CY7C68013A/14A/15A/16A 56-Pin QFN Pin Assignment RESET# RDY0/*SLRD 1 42 GND RDY1/*SLWR 2 41 PA7/*FLAGD/SLCS# AVCC 3 40 PA6/*PKTEND XTALOUT 4 39 CY7C68013A/CY7C68014A PA5/FIFOADR1 XTALIN 5 38 & PA4/FIFOADR0 AGND 6 37 CY7C68015A/CY7C68016A PA3/*WU2 AVCC 7 36 PA2/*SLOE DPLUS 8 56-pin QFN 35 PA1/INT1# DMINUS 9 34 PA0/INT0# AGND 10 33 VCC VCC 11 32 CTL2/*FLAGC GND 12 31 CTL1/*FLAGB *IFCLK/**PE0 13 30 14 29 CTL0/*FLAGA RESERVED * denotes programmable polarity ** denotes CY7C68015A/CY7C68016A pinout Document #: 38-08032 Rev. *V Page 20 of 66 CLKOUT/**PE1 *WAKEUP PD7/FD15 PD6/FD14 PD5/FD13 PD4/FD12 PD3/FD11 PD2/FD10 PD1/FD9 PD0/FD8 GND 56 GND VCC VCC 55 54 53 52 51 50 49 48 47 46 45 44 43 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SCL SDA VCC PB0/FD0 PB1/FD1 PB2/FD2 PB3/FD3 PB4/FD4 PB5/FD5 PB6/FD6 PB7/FD7 GND VCC GND CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 3-6. CY7C68013A 56-pin VFBGA Pin Assignment Top View 1 2 3 4 5 6 7 8 1A 2A 3A 4A 5A 6A 7A 8A A 1B 2B 3B 4B 5B 6B 7B 8B B 1C 2C 3C 4C 5C 6C 7C 8C C 1D 2D 7D 8D D 1E 2E 7E 8E E 1F 2F 3F 4F 5F 6F 7F 8F F 1G 2G 3G 4G 5G 6G 7G 8G G 1H 2H 3H 4H 5H 6H 7H 8H H Document #: 38-08032 Rev. *V Page 21 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 3.1 CY7C68013A/15A Pin Descriptions The FX2LP pin descriptions follow.[10] Table 10. FX2LP Pin Descriptions 128 100 56 56 56 Name Type Default Description TQFP TQFP SSOP QFN VFBGA 10 9 10 3 2D AVCC Power N/A Analog VCC. Connect this pin to 3.3V power source. This signal provides power to the analog section of the chip. 17 16 14 7 1D AVCC Power N/A Analog VCC. Connect this pin to 3.3V power source. This signal provides power to the analog section of the chip. 13 12 13 6 2F AGND Ground N/A Analog Ground. Connect to ground with as short a path as possible. 20 19 17 10 1F AGND Ground N/A Analog Ground. Connect to ground with as short a path as possible. 19 18 16 9 1E DMINUS I/O/Z Z USB D Signal. Connect to the USB D signal. 18 17 15 8 2E DPLUS I/O/Z Z USB D+ Signal. Connect to the USB D+ signal. 94 A0 Output L 8051 Address Bus. This bus is driven at all times. When the 8051 is addressing internal RAM it reflects 95 A1 Output L the internal address. 96 A2 Output L 97 A3 Output L 117 A4 Output L 118 A5 Output L 119 A6 Output L 120 A7 Output L 126 A8 Output L 127 A9 Output L 128 A10 Output L 21 A11 Output L 22 A12 Output L 23 A13 Output L 24 A14 Output L 25 A15 Output L 59 D0 I/O/Z Z 8051 Data Bus. This bidirectional bus is high impedance when inactive, input for bus reads, and 60 D1 I/O/Z Z output for bus writes. The data bus is used for external 61 D2 I/O/Z Z 8051 program and data memory. The data bus is active only for external bus accesses, and is driven LOW in 62 D3 I/O/Z Z suspend. 63 D4 I/O/Z Z 86 D5 I/O/Z Z 87 D6 I/O/Z Z 88 D7 I/O/Z Z 39 PSEN# Output H Program Store Enable. This active-LOW signal indicates an 8051 code fetch from external memory. It is active for program memory fetches from 0x4000 0xFFFF when the EA pin is LOW, or from 0x0000 0xFFFF when the EA pin is HIGH. Note 10. Unused inputs must not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power up and in standby. Note also that no pins should be driven while the device is powered down. Document #: 38-08032 Rev. *V Page 22 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions (continued) 128 100 56 56 56 Name Type Default Description TQFP TQFP SSOP QFN VFBGA 34 28 BKPT Output L Breakpoint. This pin goes active (HIGH) when the 8051 address bus matches the BPADDRH/L registers and breakpoints are enabled in the BREAKPT register (BPEN = 1). If the BPPULSE bit in the BREAKPT register is HIGH, this signal pulses HIGH for eight 12-/24-/48 MHz clocks. If the BPPULSE bit is LOW, the signal remains HIGH until the 8051 clears the BREAK bit (by writing 1 to it) in the BREAKPT register. 99 77 49 42 8B RESET# Input N/A Active LOW Reset. Resets the entire chip. See section 2.9 Reset and Wakeup on page 7 for more details. 35 EA Input N/A External Access. This pin determines where the 8051 fetches code between addresses 0x0000 and 0x3FFF. If EA = 0 the 8051 fetches this code from its internal RAM. IF EA = 1 the 8051 fetches this code from external memory. 12 11 12 5 1C XTALIN Input N/A Crystal Input. Connect this signal to a 24 MHz parallel-resonant, fundamental mode crystal and load capacitor to GND. It is also correct to drive XTALIN with an external 24-MHz square wave derived from another clock source. When driving from an external source, the driving signal should be a 3.3V square wave. 11 10 11 4 2C XTALOUT Output N/A Crystal Output. Connect this signal to a 24 MHz parallel-resonant, fundamental mode crystal and load capacitor to GND. If an external clock is used to drive XTALIN, leave this pin open. 1 100 5 54 2B CLKOUT on O/Z 12 MHz CLKOUT: 12-, 24- or 48 MHz clock, phase locked to the CY7C68013A 24 MHz input clock. The 8051 defaults to 12 MHz and operation. The 8051 may three-state this output by CY7C68014A setting CPUCS.1 = 1. ------------------ ----------- ---------- ------------------------------------------------------------------------ PE1 on I/O/Z I PE1 is a bidirectional I/O port pin. CY7C68015A and CY7C68016A Port A 82 67 40 33 8G PA0 or I/O/Z I Multiplexed pin whose function is selected by INT0# (PA0) PORTACFG.0 PA0 is a bidirectional I/O port pin. INT0# is the active-LOW 8051 INT0 interrupt input signal, which is either edge triggered (IT0 = 1) or level triggered (IT0 = 0). 83 68 41 34 6G PA1 or I/O/Z I Multiplexed pin whose function is selected by: INT1# (PA1) PORTACFG.1 PA1 is a bidirectional I/O port pin. INT1# is the active-LOW 8051 INT1 interrupt input signal, which is either edge triggered (IT1 = 1) or level triggered (IT1 = 0). 84 69 42 35 8F PA2 or I/O/Z I Multiplexed pin whose function is selected by two bits: SLOE or (PA2) IFCONFIG[1:0]. PA2 is a bidirectional I/O port pin. SLOE is an input-only output enable with program- mable polarity (FIFOPINPOLAR.4) for the slave FIFOs connected to FD[7..0] or FD[15..0]. Document #: 38-08032 Rev. *V Page 23 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions (continued) 128 100 56 56 56 Name Type Default Description TQFP TQFP SSOP QFN VFBGA 85 70 43 36 7F PA3 or I/O/Z I Multiplexed pin whose function is selected by: WU2 (PA3) WAKEUP.7 and OEA.3 PA3 is a bidirectional I/O port pin. WU2 is an alternate source for USB Wakeup, enabled by WU2EN bit (WAKEUP.1) and polarity set by WU2POL (WAKEUP.4). If the 8051 is in suspend and WU2EN = 1, a transition on this pin starts up the oscil- lator and interrupts the 8051 to enable it to exit the suspend mode. Asserting this pin inhibits the chip from suspending, if WU2EN = 1. 89 71 44 37 6F PA4 or I/O/Z I Multiplexed pin whose function is selected by: FIFOADR0 (PA4) IFCONFIG[1..0]. PA4 is a bidirectional I/O port pin. FIFOADR0 is an input-only address select for the slave FIFOs connected to FD[7..0] or FD[15..0]. 90 72 45 38 8C PA5 or I/O/Z I Multiplexed pin whose function is selected by: FIFOADR1 (PA5) IFCONFIG[1..0]. PA5 is a bidirectional I/O port pin. FIFOADR1 is an input-only address select for the slave FIFOs connected to FD[7..0] or FD[15..0]. 91 73 46 39 7C PA6 or I/O/Z I Multiplexed pin whose function is selected by the PKTEND (PA6) IFCONFIG[1:0] bits. PA6 is a bidirectional I/O port pin. PKTEND is an input used to commit the FIFO packet data to the endpoint and whose polarity is program- mable via FIFOPINPOLAR.5. 92 74 47 40 6C PA7 or I/O/Z I Multiplexed pin whose function is selected by the FLAGD or (PA7) IFCONFIG[1:0] and PORTACFG.7 bits. SLCS# PA7 is a bidirectional I/O port pin. FLAGD is a programmable slave-FIFO output status flag signal. SLCS# gates all other slave FIFO enable/strobes Port B 44 34 25 18 3H PB0 or I/O/Z I Multiplexed pin whose function is selected by the FD[0] (PB0) following bits: IFCONFIG[1..0]. PB0 is a bidirectional I/O port pin. FD[0] is the bidirectional FIFO/GPIF data bus. 45 35 26 19 4F PB1 or I/O/Z I Multiplexed pin whose function is selected by the FD[1] (PB1) following bits: IFCONFIG[1..0]. PB1 is a bidirectional I/O port pin. FD[1] is the bidirectional FIFO/GPIF data bus. 46 36 27 20 4H PB2 or I/O/Z I Multiplexed pin whose function is selected by the FD[2] (PB2) following bits: IFCONFIG[1..0]. PB2 is a bidirectional I/O port pin. FD[2] is the bidirectional FIFO/GPIF data bus. 47 37 28 21 4G PB3 or I/O/Z I Multiplexed pin whose function is selected by the FD[3] (PB3) following bits: IFCONFIG[1..0]. PB3 is a bidirectional I/O port pin. FD[3] is the bidirectional FIFO/GPIF data bus. 54 44 29 22 5H PB4 or I/O/Z I Multiplexed pin whose function is selected by the FD[4] (PB4) following bits: IFCONFIG[1..0]. PB4 is a bidirectional I/O port pin. FD[4] is the bidirectional FIFO/GPIF data bus. Document #: 38-08032 Rev. *V Page 24 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions (continued) 128 100 56 56 56 Name Type Default Description TQFP TQFP SSOP QFN VFBGA 55 45 30 23 5G PB5 or I/O/Z I Multiplexed pin whose function is selected by the FD[5] (PB5) following bits: IFCONFIG[1..0]. PB5 is a bidirectional I/O port pin. FD[5] is the bidirectional FIFO/GPIF data bus. 56 46 31 24 5F PB6 or I/O/Z I Multiplexed pin whose function is selected by the FD[6] (PB6) following bits: IFCONFIG[1..0]. PB6 is a bidirectional I/O port pin. FD[6] is the bidirectional FIFO/GPIF data bus. 57 47 32 25 6H PB7 or I/O/Z I Multiplexed pin whose function is selected by the FD[7] (PB7) following bits: IFCONFIG[1..0]. PB7 is a bidirectional I/O port pin. FD[7] is the bidirectional FIFO/GPIF data bus. PORT C 72 57 PC0 or I/O/Z I Multiplexed pin whose function is selected by GPIFADR0 (PC0) PORTCCFG.0 PC0 is a bidirectional I/O port pin. GPIFADR0 is a GPIF address output pin. 73 58 PC1 or I/O/Z I Multiplexed pin whose function is selected by GPIFADR1 (PC1) PORTCCFG.1 PC1 is a bidirectional I/O port pin. GPIFADR1 is a GPIF address output pin. 74 59 PC2 or I/O/Z I Multiplexed pin whose function is selected by GPIFADR2 (PC2) PORTCCFG.2 PC2 is a bidirectional I/O port pin. GPIFADR2 is a GPIF address output pin. 75 60 PC3 or I/O/Z I Multiplexed pin whose function is selected by GPIFADR3 (PC3) PORTCCFG.3 PC3 is a bidirectional I/O port pin. GPIFADR3 is a GPIF address output pin. 76 61 PC4 or I/O/Z I Multiplexed pin whose function is selected by GPIFADR4 (PC4) PORTCCFG.4 PC4 is a bidirectional I/O port pin. GPIFADR4 is a GPIF address output pin. 77 62 PC5 or I/O/Z I Multiplexed pin whose function is selected by GPIFADR5 (PC5) PORTCCFG.5 PC5 is a bidirectional I/O port pin. GPIFADR5 is a GPIF address output pin. 78 63 PC6 or I/O/Z I Multiplexed pin whose function is selected by GPIFADR6 (PC6) PORTCCFG.6 PC6 is a bidirectional I/O port pin. GPIFADR6 is a GPIF address output pin. 79 64 PC7 or I/O/Z I Multiplexed pin whose function is selected by GPIFADR7 (PC7) PORTCCFG.7 PC7 is a bidirectional I/O port pin. GPIFADR7 is a GPIF address output pin. PORT D 102 80 52 45 8A PD0 or I/O/Z I Multiplexed pin whose function is selected by the FD[8] (PD0) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[8] is the bidirectional FIFO/GPIF data bus. 103 81 53 46 7A PD1 or I/O/Z I Multiplexed pin whose function is selected by the FD[9] (PD1) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[9] is the bidirectional FIFO/GPIF data bus. Document #: 38-08032 Rev. *V Page 25 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions (continued) 128 100 56 56 56 Name Type Default Description TQFP TQFP SSOP QFN VFBGA 104 82 54 47 6B PD2 or I/O/Z I Multiplexed pin whose function is selected by the FD[10] (PD2) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[10] is the bidirectional FIFO/GPIF data bus. 105 83 55 48 6A PD3 or I/O/Z I Multiplexed pin whose function is selected by the FD[11] (PD3) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[11] is the bidirectional FIFO/GPIF data bus. 121 95 56 49 3B PD4 or I/O/Z I Multiplexed pin whose function is selected by the FD[12] (PD4) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[12] is the bidirectional FIFO/GPIF data bus. 122 96 1 50 3A PD5 or I/O/Z I Multiplexed pin whose function is selected by the FD[13] (PD5) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[13] is the bidirectional FIFO/GPIF data bus. 123 97 2 51 3C PD6 or I/O/Z I Multiplexed pin whose function is selected by the FD[14] (PD6) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[14] is the bidirectional FIFO/GPIF data bus. 124 98 3 52 2A PD7 or I/O/Z I Multiplexed pin whose function is selected by the FD[15] (PD7) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[15] is the bidirectional FIFO/GPIF data bus. Port E 108 86 PE0 or I/O/Z I Multiplexed pin whose function is selected by the T0OUT (PE0) PORTECFG.0 bit. PE0 is a bidirectional I/O port pin. T0OUT is an active-HIGH signal from 8051 Timer-counter0. T0OUT outputs a high level for one CLKOUT clock cycle when Timer0 overflows. If Timer0 is operated in Mode 3 (two separate timer/counters), T0OUT is active when the low byte timer/counter overflows. 109 87 PE1 or I/O/Z I Multiplexed pin whose function is selected by the T1OUT (PE1) PORTECFG.1 bit. PE1 is a bidirectional I/O port pin. T1OUT is an active-HIGH signal from 8051 Timer-counter1. T1OUT outputs a high level for one CLKOUT clock cycle when Timer1 overflows. If Timer1 is operated in Mode 3 (two separate timer/counters), T1OUT is active when the low byte timer/counter overflows. 110 88 PE2 or I/O/Z I Multiplexed pin whose function is selected by the T2OUT (PE2) PORTECFG.2 bit. PE2 is a bidirectional I/O port pin. T2OUT is the active-HIGH output signal from 8051 Timer2. T2OUT is active (HIGH) for one clock cycle when Timer/Counter 2 overflows. 111 89 PE3 or I/O/Z I Multiplexed pin whose function is selected by the RXD0OUT (PE3) PORTECFG.3 bit. PE3 is a bidirectional I/O port pin. RXD0OUT is an active-HIGH signal from 8051 UART0. If RXD0OUT is selected and UART0 is in Mode 0, this pin provides the output data for UART0 only when it is in sync mode. Otherwise it is a 1. Document #: 38-08032 Rev. *V Page 26 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions (continued) 128 100 56 56 56 Name Type Default Description TQFP TQFP SSOP QFN VFBGA 112 90 PE4 or I/O/Z I Multiplexed pin whose function is selected by the RXD1OUT (PE4) PORTECFG.4 bit. PE4 is a bidirectional I/O port pin. RXD1OUT is an active-HIGH output from 8051 UART1. When RXD1OUT is selected and UART1 is in Mode 0, this pin provides the output data for UART1 only when it is in sync mode. In Modes 1, 2, and 3, this pin is HIGH. 113 91 PE5 or I/O/Z I Multiplexed pin whose function is selected by the INT6 (PE5) PORTECFG.5 bit. PE5 is a bidirectional I/O port pin. INT6 is the 8051 INT6 interrupt request input signal. The INT6 pin is edge-sensitive, active HIGH. 114 92 PE6 or I/O/Z I Multiplexed pin whose function is selected by the T2EX (PE6) PORTECFG.6 bit. PE6 is a bidirectional I/O port pin. T2EX is an active-HIGH input signal to the 8051 Timer2. T2EX reloads timer 2 on its falling edge. T2EX is active only if the EXEN2 bit is set in T2CON. 115 93 PE7 or I/O/Z I Multiplexed pin whose function is selected by the GPIFADR8 (PE7) PORTECFG.7 bit. PE7 is a bidirectional I/O port pin. GPIFADR8 is a GPIF address output pin. 4 3 8 1 1A RDY0 or Input N/A Multiplexed pin whose function is selected by the SLRD following bits: IFCONFIG[1..0]. RDY0 is a GPIF input signal. SLRD is the input-only read strobe with programmable polarity (FIFOPINPOLAR.3) for the slave FIFOs connected to FD[7..0] or FD[15..0]. 5 4 9 2 1B RDY1 or Input N/A Multiplexed pin whose function is selected by the SLWR following bits: IFCONFIG[1..0]. RDY1 is a GPIF input signal. SLWR is the input-only write strobe with programmable polarity (FIFOPINPOLAR.2) for the slave FIFOs connected to FD[7..0] or FD[15..0]. 6 5 RDY2 Input N/A RDY2 is a GPIF input signal. 7 6 RDY3 Input N/A RDY3 is a GPIF input signal. 8 7 RDY4 Input N/A RDY4 is a GPIF input signal. 9 8 RDY5 Input N/A RDY5 is a GPIF input signal. 69 54 36 29 7H CTL0 or O/Z H Multiplexed pin whose function is selected by the FLAGA following bits: IFCONFIG[1..0]. CTL0 is a GPIF control output. FLAGA is a programmable slave-FIFO output status flag signal. Defaults to programmable for the FIFO selected by the FIFOADR[1:0] pins. Document #: 38-08032 Rev. *V Page 27 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions (continued) 128 100 56 56 56 Name Type Default Description TQFP TQFP SSOP QFN VFBGA 70 55 37 30 7G CTL1 or O/Z H Multiplexed pin whose function is selected by the FLAGB following bits: IFCONFIG[1..0]. CTL1 is a GPIF control output. FLAGB is a programmable slave-FIFO output status flag signal. Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins. 71 56 38 31 8H CTL2 or O/Z H Multiplexed pin whose function is selected by the FLAGC following bits: IFCONFIG[1..0]. CTL2 is a GPIF control output. FLAGC is a programmable slave-FIFO output status flag signal. Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins. 66 51 CTL3 O/Z H CTL3 is a GPIF control output. 67 52 CTL4 Output H CTL4 is a GPIF control output. 98 76 CTL5 Output H CTL5 is a GPIF control output. 32 26 20 13 2G IFCLK on I/O/Z Z Interface Clock, used for synchronously clocking data CY7C68013A into or out of the slave FIFOs. IFCLK also serves as a and timing reference for all slave FIFO control signals and CY7C68014A GPIF. When internal clocking is used (IFCONFIG.7 = 1) the IFCLK pin can be configured to output 30/48 MHz by bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be inverted, whether internally or externally sourced, by setting the bit IFCONFIG.4 =1. ------------------ ----------- ---------- ----------------------------------------------------------------------- PE0 on I/O/Z I PE0 is a bidirectional I/O port pin. CY7C68015A and CY7C68016A 28 22 INT4 Input N/A INT4 is the 8051 INT4 interrupt request input signal. The INT4 pin is edge-sensitive, active HIGH. 106 84 INT5# Input N/A INT5# is the 8051 INT5 interrupt request input signal. The INT5 pin is edge-sensitive, active LOW. 31 25 T2 Input N/A T2 is the active-HIGH T2 input signal to 8051 Timer2, which provides the input to Timer2 when C/T2 = 1. When C/T2 = 0, Timer2 does not use this pin. 30 24 T1 Input N/A T1 is the active-HIGH T1 signal for 8051 Timer1, which provides the input to Timer1 when C/T1 is 1. When C/T1 is 0, Timer1 does not use this bit. 29 23 T0 Input N/A T0 is the active-HIGH T0 signal for 8051 Timer0, which provides the input to Timer0 when C/T0 is 1. When C/T0 is 0, Timer0 does not use this bit. 53 43 RXD1 Input N/A RXD1is an active-HIGH input signal for 8051 UART1, which provides data to the UART in all modes. 52 42 TXD1 Output H TXD1is an active-HIGH output pin from 8051 UART1, which provides the output clock in sync mode, and the output data in async mode. 51 41 RXD0 Input N/A RXD0 is the active-HIGH RXD0 input to 8051 UART0, which provides data to the UART in all modes. Document #: 38-08032 Rev. *V Page 28 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 10. FX2LP Pin Descriptions (continued) 128 100 56 56 56 Name Type Default Description TQFP TQFP SSOP QFN VFBGA 50 40 TXD0 Output H TXD0 is the active-HIGH TXD0 output from 8051 UART0, which provides the output clock in sync mode, and the output data in async mode. 42 CS# Output H CS# is the active-LOW chip select for external memory. 41 32 WR# Output H WR# is the active-LOW write strobe output for external memory. 40 31 RD# Output H RD# is the active-LOW read strobe output for external memory. 38 OE# Output H OE# is the active-LOW output enable for external memory. 33 27 21 14 2H Reserved Input N/A Reserved. Connect to ground. 101 79 51 44 7B WAKEUP Input N/A USB Wakeup. If the 8051 is in suspend, asserting this pin starts up the oscillator and interrupts the 8051 to enable it to exit the suspend mode. Holding WAKEUP asserted inhibits the EZ-USB�� chip from suspending. This pin has programmable polarity (WAKEUP.4). 36 29 22 15 3F SCL OD Z Clock for the I2C interface. Connect to VCC with a 2.2K resistor, even if no I2C peripheral is attached. 37 30 23 16 3G SDA OD Z Data for I2C compatible interface. Connect to VCC with a 2.2K resistor, even if no I2C compatible peripheral is attached. 2 1 6 55 5A VCC Power N/A VCC. Connect to 3.3 V power source. 26 20 18 11 1G VCC Power N/A VCC. Connect to 3.3 V power source. 43 33 24 17 7E VCC Power N/A VCC. Connect to 3.3 V power source. 48 38 VCC Power N/A VCC. Connect to 3.3 V power source. 64 49 34 27 8E VCC Power N/A VCC. Connect to 3.3 V power source. 68 53 VCC Power N/A VCC. Connect to 3.3 V power source. 81 66 39 32 5C VCC Power N/A VCC. Connect to 3.3 V power source. 100 78 50 43 5B VCC Power N/A VCC. Connect to 3.3 V power source. 107 85 VCC Power N/A VCC. Connect to 3.3 V power source. 3 2 7 56 4B GND Ground N/A Ground. 27 21 19 12 1H GND Ground N/A Ground. 49 39 GND Ground N/A Ground. 58 48 33 26 7D GND Ground N/A Ground. 65 50 35 28 8D GND Ground N/A Ground. 80 65 GND Ground N/A Ground. 93 75 48 41 4C GND Ground N/A Ground. 116 94 GND Ground N/A Ground. 125 99 4 53 4A GND Ground N/A Ground. 14 13 NC N/A N/A No Connect. This pin must be left open. 15 14 NC N/A N/A No Connect. This pin must be left open. 16 15 NC N/A N/A No Connect. This pin must be left open. Document #: 38-08032 Rev. *V Page 29 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 4. Register Summary FX2LP register bit definitions are described in the FX2LP TRM in greater detail. Table 11. FX2LP Register Summary Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access GPIF Waveform Memories E400 128 WAVEDATA GPIF Waveform D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW Descriptor 0, 1, 2, 3 data E480 128 reserved GENERAL CONFIGURATION E50D GPCR2 General Purpose Configu- reserved reserved reserved FULL_SPEE reserved reserved reserved reserved 00000000 R ration Register 2 D_ONLY E600 1 CPUCS CPU Control & Status 0 0 PORTCSTB CLKSPD1 CLKSPD0 CLKINV CLKOE 8051RES 00000010 rrbbbbbr E601 1 IFCONFIG Interface Configuration IFCLKSRC 3048MHZ IFCLKOE IFCLKPOL ASYNC GSTATE IFCFG1 IFCFG0 10000000 RW (Ports, GPIF, slave FIFOs) E602 1 PINFLAGSAB[11] Slave FIFO FLAGA and FLAGB3 FLAGB2 FLAGB1 FLAGB0 FLAGA3 FLAGA2 FLAGA1 FLAGA0 00000000 RW FLAGB Pin Configuration E603 1 PINFLAGSCD[11] Slave FIFO FLAGC and FLAGD3 FLAGD2 FLAGD1 FLAGD0 FLAGC3 FLAGC2 FLAGC1 FLAGC0 00000000 RW FLAGD Pin Configuration E604 1 FIFORESET[11] Restore FIFOS to default NAKALL 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx W state E605 1 BREAKPT Breakpoint Control 0 0 0 0 BREAK BPPULSE BPEN 0 00000000 rrrrbbbr E606 1 BPADDRH Breakpoint Address H A15 A14 A13 A12 A11 A10 A9 A8 xxxxxxxx RW E607 1 BPADDRL Breakpoint Address L A7 A6 A5 A4 A3 A2 A1 A0 xxxxxxxx RW E608 1 UART230 230 Kbaud internally 0 0 0 0 0 0 230UART1 230UART0 00000000 rrrrrrbb generated ref. clock E609 1 FIFOPINPOLAR[11] Slave FIFO Interface pins 0 0 PKTEND SLOE SLRD SLWR EF FF 00000000 rrbbbbbb polarity E60A 1 REVID Chip Revision rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 RevA R 00000001 E60B 1 REVCTL[11] Chip Revision Control 0 0 0 0 0 0 dyn_out enh_pkt 00000000 rrrrrrbb UDMA E60C 1 GPIFHOLDAMOUNT MSTB Hold Time 0 0 0 0 0 0 HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb (for UDMA) 3 reserved ENDPOINT CONFIGURATION E610 1 EP1OUTCFG Endpoint 1-OUT VALID 0 TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr Configuration E611 1 EP1INCFG Endpoint 1-IN VALID 0 TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr Configuration E612 1 EP2CFG Endpoint 2 Configuration VALID DIR TYPE1 TYPE0 SIZE 0 BUF1 BUF0 10100010 bbbbbrbb E613 1 EP4CFG Endpoint 4 Configuration VALID DIR TYPE1 TYPE0 0 0 0 0 10100000 bbbbrrrr E614 1 EP6CFG Endpoint 6 Configuration VALID DIR TYPE1 TYPE0 SIZE 0 BUF1 BUF0 11100010 bbbbbrbb E615 1 EP8CFG Endpoint 8 Configuration VALID DIR TYPE1 TYPE0 0 0 0 0 11100000 bbbbrrrr 2 reserved E618 1 EP2FIFOCFG[11] Endpoint 2 / slave FIFO 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb configuration E619 1 EP4FIFOCFG[11] Endpoint 4 / slave FIFO 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb configuration E61A 1 EP6FIFOCFG[11] Endpoint 6 / slave FIFO 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb configuration E61B 1 EP8FIFOCFG[11] Endpoint 8 / slave FIFO 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb configuration E61C 4 reserved E620 1 EP2AUTOINLENH[11 Endpoint 2 AUTOIN 0 0 0 0 0 PL10 PL9 PL8 00000010 rrrrrbbb Packet Length H E621 1 EP2AUTOINLENL[11] Endpoint 2 AUTOIN PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW Packet Length L E622 1 EP4AUTOINLENH[11] Endpoint 4 AUTOIN 0 0 0 0 0 0 PL9 PL8 00000010 rrrrrrbb Packet Length H E623 1 EP4AUTOINLENL[11] Endpoint 4 AUTOIN PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW Packet Length L E624 1 EP6AUTOINLENH[11] Endpoint 6 AUTOIN 0 0 0 0 0 PL10 PL9 PL8 00000010 rrrrrbbb Packet Length H E625 1 EP6AUTOINLENL[11] Endpoint 6 AUTOIN PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW Packet Length L E626 1 EP8AUTOINLENH[11] Endpoint 8 AUTOIN 0 0 0 0 0 0 PL9 PL8 00000010 rrrrrrbb Packet Length H E627 1 EP8AUTOINLENL[11] Endpoint 8 AUTOIN PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW Packet Length L E628 1 ECCCFG ECC Configuration 0 0 0 0 0 0 0 ECCM 00000000 rrrrrrrb E629 1 ECCRESET ECC Reset x x x x x x x x 00000000 W E62A 1 ECC1B0 ECC1 Byte 0 Address LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 00000000 R Note 11. Read and writes to these registers may require synchronization delay, see Technical Reference Manual for Synchronization Delay. Document #: 38-08032 Rev. *V Page 30 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 11. FX2LP Register Summary (continued) Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access E62B 1 ECC1B1 ECC1 Byte 1 Address LINE7 LINE6 LINE5 LINE4 LINE3 LINE2 LINE1 LINE0 00000000 R E62C 1 ECC1B2 ECC1 Byte 2 Address COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16 00000000 R E62D 1 ECC2B0 ECC2 Byte 0 Address LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 00000000 R E62E 1 ECC2B1 ECC2 Byte 1 Address LINE7 LINE6 LINE5 LINE4 LINE3 LINE2 LINE1 LINE0 00000000 R E62F 1 ECC2B2 ECC2 Byte 2 Address COL5 COL4 COL3 COL2 COL1 COL0 0 0 00000000 R E630 1 EP2FIFOPFH[11] Endpoint 2 / slave FIFO DECIS PKTSTAT IN:PKTS[2] IN:PKTS[1] IN:PKTS[0] 0 PFC9 PFC8 10001000 bbbbbrbb H.S. Programmable Flag H OUT:PFC12 OUT:PFC11 OUT:PFC10 E630 1 EP2FIFOPFH[11] Endpoint 2 / slave FIFO DECIS PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10 0 PFC9 IN:PKTS[2] 10001000 bbbbbrbb F.S. Programmable Flag H OUT:PFC8 E631 1 EP2FIFOPFL[11] Endpoint 2 / slave FIFO PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW H.S. Programmable Flag L E631 1 EP2FIFOPFL[11] Endpoint 2 / slave FIFO IN:PKTS[1] IN:PKTS[0] PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW F.S Programmable Flag L OUT:PFC7 OUT:PFC6 E632 1 EP4FIFOPFH[11] Endpoint 4 / slave FIFO DECIS PKTSTAT 0 IN: PKTS[1] IN: PKTS[0] 0 0 PFC8 10001000 bbrbbrrb H.S. Programmable Flag H OUT:PFC10 OUT:PFC9 E632 1 EP4FIFOPFH[11] Endpoint 4 / slave FIFO DECIS PKTSTAT 0 OUT:PFC10 OUT:PFC9 0 0 PFC8 10001000 bbrbbrrb F.S Programmable Flag H E633 1 EP4FIFOPFL[11] Endpoint 4 / slave FIFO PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW H.S. Programmable Flag L E633 1 EP4FIFOPFL[11] Endpoint 4 / slave FIFO IN: PKTS[1] IN: PKTS[0] PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW F.S Programmable Flag L OUT:PFC7 OUT:PFC6 E634 1 EP6FIFOPFH[11] Endpoint 6 / slave FIFO DECIS PKTSTAT IN:PKTS[2] IN:PKTS[1] IN:PKTS[0] 0 PFC9 PFC8 00001000 bbbbbrbb H.S. Programmable Flag H OUT:PFC12 OUT:PFC11 OUT:PFC10 E634 1 EP6FIFOPFH[11] Endpoint 6 / slave FIFO DECIS PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10 0 PFC9 IN:PKTS[2] 00001000 bbbbbrbb F.S Programmable Flag H OUT:PFC8 E635 1 EP6FIFOPFL[11] Endpoint 6 / slave FIFO PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW H.S. Programmable Flag L E635 1 EP6FIFOPFL[11] Endpoint 6 / slave FIFO IN:PKTS[1] IN:PKTS[0] PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW F.S Programmable Flag L OUT:PFC7 OUT:PFC6 E636 1 EP8FIFOPFH[11] Endpoint 8 / slave FIFO DECIS PKTSTAT 0 IN: PKTS[1] IN: PKTS[0] 0 0 PFC8 00001000 bbrbbrrb H.S. Programmable Flag H OUT:PFC10 OUT:PFC9 E636 1 EP8FIFOPFH[11] Endpoint 8 / slave FIFO DECIS PKTSTAT 0 OUT:PFC10 OUT:PFC9 0 0 PFC8 00001000 bbrbbrrb F.S Programmable Flag H E637 1 EP8FIFOPFL[11] Endpoint 8 / slave FIFO PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW H.S. Programmable Flag L E637 1 EP8FIFOPFL[11] Endpoint 8 / slave FIFO IN: PKTS[1] IN: PKTS[0] PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW F.S Programmable Flag L OUT:PFC7 OUT:PFC6 8 reserved E640 1 EP2ISOINPKTS EP2 (if ISO) IN Packets per AADJ 0 0 0 0 0 INPPF1 INPPF0 00000001 brrrrrbb frame (1-3) E641 1 EP4ISOINPKTS EP4 (if ISO) IN Packets per AADJ 0 0 0 0 0 INPPF1 INPPF0 00000001 brrrrrrr frame (1-3) E642 1 EP6ISOINPKTS EP6 (if ISO) IN Packets per AADJ 0 0 0 0 0 INPPF1 INPPF0 00000001 brrrrrbb frame (1-3) E643 1 EP8ISOINPKTS EP8 (if ISO) IN Packets per AADJ 0 0 0 0 0 INPPF1 INPPF0 00000001 brrrrrrr frame (1-3) E644 4 reserved E648 1 INPKTEND[11] Force IN Packet End Skip 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx W E649 7 OUTPKTEND[11] Force OUT Packet End Skip 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx W INTERRUPTS E650 1 EP2FIFOIE[11] Endpoint 2 slave FIFO Flag 0 0 0 0 EDGEPF PF EF FF 00000000 RW Interrupt Enable E651 1 EP2FIFOIRQ[11,12] Endpoint 2 slave FIFO Flag 0 0 0 0 0 PF EF FF 00000000 rrrrrbbb Interrupt Request E652 1 EP4FIFOIE[11] Endpoint 4 slave FIFO Flag 0 0 0 0 EDGEPF PF EF FF 00000000 RW Interrupt Enable E653 1 EP4FIFOIRQ[11,12] Endpoint 4 slave FIFO Flag 0 0 0 0 0 PF EF FF 00000000 rrrrrbbb Interrupt Request E654 1 EP6FIFOIE[11] Endpoint 6 slave FIFO Flag 0 0 0 0 EDGEPF PF EF FF 00000000 RW Interrupt Enable E655 1 EP6FIFOIRQ[11,12] Endpoint 6 slave FIFO Flag 0 0 0 0 0 PF EF FF 00000000 rrrrrbbb Interrupt Request E656 1 EP8FIFOIE[11] Endpoint 8 slave FIFO Flag 0 0 0 0 EDGEPF PF EF FF 00000000 RW Interrupt Enable E657 1 EP8FIFOIRQ[11,12] Endpoint 8 slave FIFO Flag 0 0 0 0 0 PF EF FF 00000000 rrrrrbbb Interrupt Request E658 1 IBNIE IN-BULK-NAK Interrupt 0 0 EP8 EP6 EP4 EP2 EP1 EP0 00000000 RW Enable E659 1 IBNIRQ[12] IN-BULK-NAK interrupt 0 0 EP8 EP6 EP4 EP2 EP1 EP0 00xxxxxx rrbbbbbb Request E65A 1 NAKIE Endpoint Ping-NAK / IBN EP8 EP6 EP4 EP2 EP1 EP0 0 IBN 00000000 RW Interrupt Enable E65B 1 NAKIRQ[12] Endpoint Ping-NAK / IBN EP8 EP6 EP4 EP2 EP1 EP0 0 IBN xxxxxx0x bbbbbbrb Interrupt Request E65C 1 USBIE USB Int Enables 0 EP0ACK HSGRANT URES SUSP SUTOK SOF SUDAV 00000000 RW Note 12. The register can only be reset, it cannot be set. Document #: 38-08032 Rev. *V Page 31 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 11. FX2LP Register Summary (continued) Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access E65D 1 USBIRQ[12] USB Interrupt Requests 0 EP0ACK HSGRANT URES SUSP SUTOK SOF SUDAV 0xxxxxxx rbbbbbbb E65E 1 EPIE Endpoint Interrupt EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN 00000000 RW Enables E65F 1 EPIRQ[12] Endpoint Interrupt EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN 0 RW Requests E660 1 GPIFIE[11] GPIF Interrupt Enable 0 0 0 0 0 0 GPIFWF GPIFDONE 00000000 RW E661 1 GPIFIRQ[11] GPIF Interrupt Request 0 0 0 0 0 0 GPIFWF GPIFDONE 000000xx RW E662 1 USBERRIE USB Error Interrupt ISOEP8 ISOEP6 ISOEP4 ISOEP2 0 0 0 ERRLIMIT 00000000 RW Enables E663 1 USBERRIRQ[12] USB Error Interrupt ISOEP8 ISOEP6 ISOEP4 ISOEP2 0 0 0 ERRLIMIT 0000000x bbbbrrrb Requests E664 1 ERRCNTLIM USB Error counter and limit EC3 EC2 EC1 EC0 LIMIT3 LIMIT2 LIMIT1 LIMIT0 xxxx0100 rrrrbbbb E665 1 CLRERRCNT Clear Error Counter EC3:0 x x x x x x x x xxxxxxxx W E666 1 INT2IVEC Interrupt 2 (USB) 0 I2V4 I2V3 I2V2 I2V1 I2V0 0 0 00000000 R Autovector E667 1 INT4IVEC Interrupt 4 (slave FIFO & 1 0 I4V3 I4V2 I4V1 I4V0 0 0 10000000 R GPIF) Autovector E668 1 INTSET-UP Interrupt 2&4 setup 0 0 0 0 AV2EN 0 INT4SRC AV4EN 00000000 RW E669 7 reserved INPUT / OUTPUT E670 1 PORTACFG I/O PORTA Alternate FLAGD SLCS 0 0 0 0 INT1 INT0 00000000 RW Configuration E671 1 PORTCCFG I/O PORTC Alternate GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFA0 00000000 RW Configuration E672 1 PORTECFG I/O PORTE Alternate GPIFA8 T2EX INT6 RXD1OUT RXD0OUT T2OUT T1OUT T0OUT 00000000 RW Configuration E673 4 reserved E677 1 reserved E678 1 I2CS I�C Bus START STOP LASTRD ID1 ID0 BERR ACK DONE 000xx000 bbbrrrrr Control & Status E679 1 I2DAT I�C Bus d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx RW Data E67A 1 I2CTL I�C Bus 0 0 0 0 0 0 STOPIE 400KHZ 00000000 RW Control E67B 1 XAUTODAT1 Autoptr1 MOVX access, D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW when APTREN=1 E67C 1 XAUTODAT2 Autoptr2 MOVX access, D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW when APTREN=1 UDMA CRC E67D 1 UDMACRCH[11] UDMA CRC MSB CRC15 CRC14 CRC13 CRC12 CRC11 CRC10 CRC9 CRC8 01001010 RW E67E 1 UDMACRCL[11] UDMA CRC LSB CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0 10111010 RW E67F 1 UDMACRC- UDMA CRC Qualifier QENABLE 0 0 0 QSTATE QSIGNAL2 QSIGNAL1 QSIGNAL0 00000000 brrrbbbb QUALIFIER USB CONTROL E680 1 USBCS USB Control & Status HSM 0 0 0 DISCON NOSYNSOF RENUM SIGRSUME x0000000 rrrrbbbb E681 1 SUSPEND Put chip into suspend x x x x x x x x xxxxxxxx W E682 1 WAKEUPCS Wakeup Control & Status WU2 WU WU2POL WUPOL 0 DPEN WU2EN WUEN xx000101 bbbbrbbb E683 1 TOGCTL Toggle Control Q S R I/O EP3 EP2 EP1 EP0 x0000000 rrrbbbbb E684 1 USBFRAMEH USB Frame count H 0 0 0 0 0 FC10 FC9 FC8 00000xxx R E685 1 USBFRAMEL USB Frame count L FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 xxxxxxxx R E686 1 MICROFRAME Microframe count, 0-7 0 0 0 0 0 MF2 MF1 MF0 00000xxx R E687 1 FNADDR USB Function address 0 FA6 FA5 FA4 FA3 FA2 FA1 FA0 0xxxxxxx R E688 2 reserved ENDPOINTS E68A 1 EP0BCH[11] Endpoint 0 Byte Count H (BC15) (BC14) (BC13) (BC12) (BC11) (BC10) (BC9) (BC8) xxxxxxxx RW E68B 1 EP0BCL[11] Endpoint 0 Byte Count L (BC7) BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW E68C 1 reserved E68D 1 EP1OUTBC Endpoint 1 OUT Byte 0 BC6 BC5 BC4 BC3 BC2 BC1 BC0 0xxxxxxx RW Count E68E 1 reserved E68F 1 EP1INBC Endpoint 1 IN Byte Count 0 BC6 BC5 BC4 BC3 BC2 BC1 BC0 0xxxxxxx RW E690 1 EP2BCH[11] Endpoint 2 Byte Count H 0 0 0 0 0 BC10 BC9 BC8 00000xxx RW E691 1 EP2BCL[11] Endpoint 2 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW E692 2 reserved E694 1 EP4BCH[11] Endpoint 4 Byte Count H 0 0 0 0 0 0 BC9 BC8 000000xx RW E695 1 EP4BCL[11] Endpoint 4 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW E696 2 reserved E698 1 EP6BCH[11] Endpoint 6 Byte Count H 0 0 0 0 0 BC10 BC9 BC8 00000xxx RW E699 1 EP6BCL[11] Endpoint 6 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW E69A 2 reserved E69C 1 EP8BCH[11] Endpoint 8 Byte Count H 0 0 0 0 0 0 BC9 BC8 000000xx RW E69D 1 EP8BCL[11] Endpoint 8 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW E69E 2 reserved Document #: 38-08032 Rev. *V Page 32 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 11. FX2LP Register Summary (continued) Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access E6A0 1 EP0CS Endpoint 0 Control and Sta- HSNAK 0 0 0 0 0 BUSY STALL 10000000 bbbbbbrb tus E6A1 1 EP1OUTCS Endpoint 1 OUT Control 0 0 0 0 0 0 BUSY STALL 00000000 bbbbbbrb and Status E6A2 1 EP1INCS Endpoint 1 IN Control and 0 0 0 0 0 0 BUSY STALL 00000000 bbbbbbrb Status E6A3 1 EP2CS Endpoint 2 Control and Sta- 0 NPAK2 NPAK1 NPAK0 FULL EMPTY 0 STALL 00101000 rrrrrrrb tus E6A4 1 EP4CS Endpoint 4 Control and Sta- 0 0 NPAK1 NPAK0 FULL EMPTY 0 STALL 00101000 rrrrrrrb tus E6A5 1 EP6CS Endpoint 6 Control and Sta- 0 NPAK2 NPAK1 NPAK0 FULL EMPTY 0 STALL 00000100 rrrrrrrb tus E6A6 1 EP8CS Endpoint 8 Control and Sta- 0 0 NPAK1 NPAK0 FULL EMPTY 0 STALL 00000100 rrrrrrrb tus E6A7 1 EP2FIFOFLGS Endpoint 2 slave FIFO 0 0 0 0 0 PF EF FF 00000010 R Flags E6A8 1 EP4FIFOFLGS Endpoint 4 slave FIFO 0 0 0 0 0 PF EF FF 00000010 R Flags E6A9 1 EP6FIFOFLGS Endpoint 6 slave FIFO 0 0 0 0 0 PF EF FF 00000110 R Flags E6AA 1 EP8FIFOFLGS Endpoint 8 slave FIFO 0 0 0 0 0 PF EF FF 00000110 R Flags E6AB 1 EP2FIFOBCH Endpoint 2 slave FIFO 0 0 0 BC12 BC11 BC10 BC9 BC8 00000000 R total byte count H E6AC 1 EP2FIFOBCL Endpoint 2 slave FIFO BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R total byte count L E6AD 1 EP4FIFOBCH Endpoint 4 slave FIFO 0 0 0 0 0 BC10 BC9 BC8 00000000 R total byte count H E6AE 1 EP4FIFOBCL Endpoint 4 slave FIFO BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R total byte count L E6AF 1 EP6FIFOBCH Endpoint 6 slave FIFO 0 0 0 0 BC11 BC10 BC9 BC8 00000000 R total byte count H E6B0 1 EP6FIFOBCL Endpoint 6 slave FIFO BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R total byte count L E6B1 1 EP8FIFOBCH Endpoint 8 slave FIFO 0 0 0 0 0 BC10 BC9 BC8 00000000 R total byte count H E6B2 1 EP8FIFOBCL Endpoint 8 slave FIFO BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R total byte count L E6B3 1 SUDPTRH Setup Data Pointer high A15 A14 A13 A12 A11 A10 A9 A8 xxxxxxxx RW address byte E6B4 1 SUDPTRL Setup Data Pointer low ad- A7 A6 A5 A4 A3 A2 A1 0 xxxxxxx0 bbbbbbbr dress byte E6B5 1 SUDPTRCTL Setup Data Pointer Auto 0 0 0 0 0 0 0 SDPAUTO 00000001 RW Mode 2 reserved E6B8 8 SET-UPDAT 8 bytes of setup data D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R SET-UPDAT[0] = bmRequestType SET-UPDAT[1] = bmRequest SET-UPDAT[2:3] = wValue SET-UPDAT[4:5] = wIndex SET-UPDAT[6:7] = wLength GPIF E6C0 1 GPIFWFSELECT Waveform Selector SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1 FIFOWR0 FIFORD1 FIFORD0 11100100 RW E6C1 1 GPIFIDLECS GPIF Done, GPIF IDLE DONE 0 0 0 0 0 0 IDLEDRV 10000000 RW drive mode E6C2 1 GPIFIDLECTL Inactive Bus, CTL states 0 0 CTL5 CTL4 CTL3 CTL2 CTL1 CTL0 11111111 RW E6C3 1 GPIFCTLCFG CTL Drive Type TRICTL 0 CTL5 CTL4 CTL3 CTL2 CTL1 CTL0 00000000 RW E6C4 1 GPIFADRH[11] GPIF Address H 0 0 0 0 0 0 0 GPIFA8 00000000 RW E6C5 1 GPIFADRL[11] GPIF Address L GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFA0 00000000 RW FLOWSTATE E6C6 1 FLOWSTATE Flowstate Enable and FSE 0 0 0 0 FS2 FS1 FS0 00000000 brrrrbbb Selector E6C7 1 FLOWLOGIC Flowstate Logic LFUNC1 LFUNC0 TERMA2 TERMA1 TERMA0 TERMB2 TERMB1 TERMB0 00000000 RW E6C8 1 FLOWEQ0CTL CTL-Pin States in CTL0E3 CTL0E2 CTL0E1/ CTL0E0/ CTL3 CTL2 CTL1 CTL0 00000000 RW Flowstate CTL5 CTL4 (when Logic = 0) E6C9 1 FLOWEQ1CTL CTL-Pin States in Flow- CTL0E3 CTL0E2 CTL0E1/ CTL0E0/ CTL3 CTL2 CTL1 CTL0 00000000 RW state (when Logic = 1) CTL5 CTL4 E6CA 1 FLOWHOLDOFF Holdoff Configuration HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD0 HOSTATE HOCTL2 HOCTL1 HOCTL0 00010010 RW E6CB 1 FLOWSTB Flowstate Strobe SLAVE RDYASYNC CTLTOGL SUSTAIN 0 MSTB2 MSTB1 MSTB0 00100000 RW Configuration E6CC 1 FLOWSTBEDGE Flowstate Rising/Falling 0 0 0 0 0 0 FALLING RISING 00000001 rrrrrrbb Edge Configuration E6CD 1 FLOWSTBPERIOD Master-Strobe Half-Period D7 D6 D5 D4 D3 D2 D1 D0 00000010 RW E6CE 1 GPIFTCB3[11] GPIF Transaction Count TC31 TC30 TC29 TC28 TC27 TC26 TC25 TC24 00000000 RW Byte 3 Document #: 38-08032 Rev. *V Page 33 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 11. FX2LP Register Summary (continued) Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access E6CF 1 GPIFTCB2[11] GPIF Transaction Count TC23 TC22 TC21 TC20 TC19 TC18 TC17 TC16 00000000 RW Byte 2 E6D0 1 GPIFTCB1[11] GPIF Transaction Count TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 00000000 RW Byte 1 E6D1 1 GPIFTCB0[11] GPIF Transaction Count TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 00000001 RW Byte 0 2 reserved 00000000 RW reserved reserved E6D2 1 EP2GPIFFLGSEL[11] Endpoint 2 GPIF Flag 0 0 0 0 0 0 FS1 FS0 00000000 RW select E6D3 1 EP2GPIFPFSTOP Endpoint 2 GPIF stop 0 0 0 0 0 0 0 FIFO2FLAG 00000000 RW transaction on prog. flag E6D4 1 EP2GPIFTRIG[11] Endpoint 2 GPIF Trigger x x x x x x x x xxxxxxxx W 3 reserved reserved reserved E6DA 1 EP4GPIFFLGSEL[11] Endpoint 4 GPIF Flag 0 0 0 0 0 0 FS1 FS0 00000000 RW select E6DB 1 EP4GPIFPFSTOP Endpoint 4 GPIF stop 0 0 0 0 0 0 0 FIFO4FLAG 00000000 RW transaction on GPIF Flag E6DC 1 EP4GPIFTRIG[11] Endpoint 4 GPIF Trigger x x x x x x x x xxxxxxxx W 3 reserved reserved reserved E6E2 1 EP6GPIFFLGSEL[11] Endpoint 6 GPIF Flag 0 0 0 0 0 0 FS1 FS0 00000000 RW select E6E3 1 EP6GPIFPFSTOP Endpoint 6 GPIF stop 0 0 0 0 0 0 0 FIFO6FLAG 00000000 RW transaction on prog. flag E6E4 1 EP6GPIFTRIG[11] Endpoint 6 GPIF Trigger x x x x x x x x xxxxxxxx W 3 reserved reserved reserved E6EA 1 EP8GPIFFLGSEL[11] Endpoint 8 GPIF Flag 0 0 0 0 0 0 FS1 FS0 00000000 RW select E6EB 1 EP8GPIFPFSTOP Endpoint 8 GPIF stop 0 0 0 0 0 0 0 FIFO8FLAG 00000000 RW transaction on prog. flag E6EC 1 EP8GPIFTRIG[11] Endpoint 8 GPIF Trigger x x x x x x x x xxxxxxxx W 3 reserved E6F0 1 XGPIFSGLDATH GPIF Data H D15 D14 D13 D12 D11 D10 D9 D8 xxxxxxxx RW (16-bit mode only) E6F1 1 XGPIFSGLDATLX Read/Write GPIF Data L & D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW trigger transaction E6F2 1 XGPIFSGLDATLNOX Read GPIF Data L, no D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R transaction trigger E6F3 1 GPIFREADYCFG Internal RDY, Sync/Async, INTRDY SAS TCXRDY5 0 0 0 0 0 00000000 bbbrrrrr RDY pin states E6F4 1 GPIFREADYSTAT GPIF Ready Status 0 0 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0 00xxxxxx R E6F5 1 GPIFABORT Abort GPIF Waveforms x x x x x x x x xxxxxxxx W E6F6 2 reserved ENDPOINT BUFFERS E740 64 EP0BUF EP0-IN/-OUT buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW E780 64 EP10UTBUF EP1-OUT buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW E7C0 64 EP1INBUF EP1-IN buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW E800 2048 reserved RW F000 1024 EP2FIFOBUF 512/1024 byte EP 2 / slave D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW FIFO buffer (IN or OUT) F400 512 EP4FIFOBUF 512 byte EP 4 / slave FIFO D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW buffer (IN or OUT) F600 512 reserved F800 1024 EP6FIFOBUF 512/1024 byte EP 6 / slave D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW FIFO buffer (IN or OUT) FC00 512 EP8FIFOBUF 512 byte EP 8 / slave FIFO D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW buffer (IN or OUT) FE00 512 reserved Document #: 38-08032 Rev. *V Page 34 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 11. FX2LP Register Summary (continued) Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access xxxx I�C Configuration Byte 0 DISCON 0 0 0 0 0 400KHZ xxxxxxxx n/a [14] Special Function Registers (SFRs) 80 1 IOA[13] Port A (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW 81 1 SP Stack Pointer D7 D6 D5 D4 D3 D2 D1 D0 00000111 RW 82 1 DPL0 Data Pointer 0 L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW 83 1 DPH0 Data Pointer 0 H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW 84 1 DPL1[13] Data Pointer 1 L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW 85 1 DPH1[13] Data Pointer 1 H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW 86 1 DPS[13] Data Pointer 0/1 select 0 0 0 0 0 0 0 SEL 00000000 RW 87 1 PCON Power Control SMOD0 x 1 1 x x x IDLE 00110000 RW 88 1 TCON Timer/Counter Control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00000000 RW (bit addressable) 89 1 TMOD Timer/Counter Mode GATE CT M1 M0 GATE CT M1 M0 00000000 RW Control 8A 1 TL0 Timer 0 reload L D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW 8B 1 TL1 Timer 1 reload L D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW 8C 1 TH0 Timer 0 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW 8D 1 TH1 Timer 1 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW 8E 1 CKCON[13] Clock Control x x T2M T1M T0M MD2 MD1 MD0 00000001 RW 8F 1 reserved 90 1 IOB[13] Port B (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW 91 1 EXIF[13] External Interrupt Flag(s) IE5 IE4 I�CINT USBNT 1 0 0 0 00001000 RW 92 1 MPAGE[13] Upper Addr Byte of MOVX A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW using @R0 / @R1 93 5 reserved 98 1 SCON0 Serial Port 0 Control SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00000000 RW (bit addressable) 99 1 SBUF0 Serial Port 0 Data Buffer D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW 9A 1 AUTOPTRH1[13] Autopointer 1 Address H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW 9B 1 AUTOPTRL1[13] Autopointer 1 Address L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW 9C 1 reserved 9D 1 AUTOPTRH2[13] Autopointer 2 Address H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW 9E 1 AUTOPTRL2[13] Autopointer 2 Address L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW 9F 1 reserved A0 1 IOC[13] Port C (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW A1 1 INT2CLR[13] Interrupt 2 clear x x x x x x x x xxxxxxxx W A2 1 INT4CLR[13] Interrupt 4 clear x x x x x x x x xxxxxxxx W A3 5 reserved A8 1 IE Interrupt Enable EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 00000000 RW (bit addressable) A9 1 reserved AA 1 EP2468STAT[13] Endpoint 2,4,6,8 status EP8F EP8E EP6F EP6E EP4F EP4E EP2F EP2E 01011010 R flags AB 1 EP24FIFOFLGS Endpoint 2,4 slave FIFO 0 EP4PF EP4EF EP4FF 0 EP2PF EP2EF EP2FF 00100010 R [13] status flags AC 1 EP68FIFOFLGS Endpoint 6,8 slave FIFO 0 EP8PF EP8EF EP8FF 0 EP6PF EP6EF EP6FF 01100110 R [13] status flags AD 2 reserved AF 1 AUTOPTRSETUP[13] Autopointer 1&2 setup 0 0 0 0 0 APTR2INC APTR1INC APTREN 00000110 RW B0 1 IOD[13] Port D (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW B1 1 IOE[13] Port E D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW (NOT bit addressable) B2 1 OEA[13] Port A Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW B3 1 OEB[13] Port B Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW B4 1 OEC[13] Port C Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW B5 1 OED[13] Port D Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW B6 1 OEE[13] Port E Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW B7 1 reserved B8 1 IP Interrupt Priority (bit ad- 1 PS1 PT2 PS0 PT1 PX1 PT0 PX0 10000000 RW dressable) B9 1 reserved BA 1 EP01STAT[13] Endpoint 0&1 Status 0 0 0 0 0 EP1INBSY EP1OUTBSY EP0BSY 00000000 R BB 1 GPIFTRIG[13, 11] Endpoint 2,4,6,8 GPIF DONE 0 0 0 0 RW EP1 EP0 10000xxx brrrrbbb slave FIFO Trigger BC 1 reserved BD 1 GPIFSGLDATH[13] GPIF Data H (16-bit mode D15 D14 D13 D12 D11 D10 D9 D8 xxxxxxxx RW only) Notes 13. SFRs not part of the standard 8051 architecture. 14. If no EEPROM is detected by the SIE then the default is 00000000. Document #: 38-08032 Rev. *V Page 35 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 11. FX2LP Register Summary (continued) Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access BE 1 GPIFSGLDATLX[13] GPIF Data L w/ Trigger D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW BF 1 GPIFSGLDATL- GPIF Data L w/ No Trigger D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R NOX[13] C0 1 SCON1[13] Serial Port 1 Control (bit SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00000000 RW addressable) C1 1 SBUF1[13] Serial Port 1 Data Buffer D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW C2 6 reserved C8 1 T2CON Timer/Counter 2 Control TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2 00000000 RW (bit addressable) C9 1 reserved CA 1 RCAP2L Capture for Timer 2, au- D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW to-reload, up-counter CB 1 RCAP2H Capture for Timer 2, au- D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW to-reload, up-counter CC 1 TL2 Timer 2 reload L D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW CD 1 TH2 Timer 2 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW CE 2 reserved D0 1 PSW Program Status Word (bit CY AC F0 RS1 RS0 OV F1 P 00000000 RW addressable) D1 7 reserved D8 1 EICON[13] External Interrupt Control SMOD1 1 ERESI RESI INT6 0 0 0 01000000 RW D9 7 reserved E0 1 ACC Accumulator (bit address- D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW able) E1 7 reserved E8 1 EIE[13] External Interrupt En- 1 1 1 EX6 EX5 EX4 EI�C EUSB 11100000 RW able(s) E9 7 reserved F0 1 B B (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW F1 7 reserved F8 1 EIP[13] External Interrupt Priority 1 1 1 PX6 PX5 PX4 PI�C PUSB 11100000 RW Control F9 7 reserved R = all bits read-only W = all bits write-only r = read-only bit w = write-only bit b = both read/write bit Document #: 38-08032 Rev. *V Page 36 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 5. Absolute Maximum Ratings 6. Operating Conditions Exceeding maximum ratings may shorten the useful life of the TA (ambient temperature under bias) device. User guidelines are not tested. Commercial .................................................... 0 �C to +70 �C Storage temperature ................................ 65 ��C to +150 ��C TA (ambient temperature under bias) Industrial................................................... 40 �C to +105 �C Ambient temperature with power supplied (commercial).......................... 0 �C to +70 �C Supply voltage ..........................................+3.00 V to +3.60 V Ambient temperature with Ground voltage ................................................................. 0 V power supplied (industrial)....................... 40 ��C to + 105 ��C FOSC (oscillator or crystal frequency) ..... 24 MHz � 100 ppm, Supply voltage to ground potential ............... 0.5 V to +4.0 V parallel resonant DC input voltage to any input pin[15]............................ 5.25 V DC voltage applied to outputs in high Z state ..................................... 0.5 V to VCC + 0.5 V Power dissipation ..................................................... 300 mW Static discharge voltage............. ...............................>2000 V Max output current, per I/O port .................................. 10 mA Max output current, all five I/O ports (128-pin and 100-pin packages).................................. 50 mA 7. Thermal Characteristics The following table displays the thermal characteristics of various packages: Table 12. Thermal Characteristics q�Jc q�Ja Ambient Junction to Case Junction to Ambient Package Temperature Thermal Resistance Thermal Resistance (�C) (�C/W) (�C/W) 56 SSOP 70 24.4 47.7 100 TQFP 70 11.9 45.9 128 TQFP 70 15.5 43.2 56 QFN 70 10.6 25.2 56 VFBGA 70 30.9 58.6 The junction temperature q�j, can be calculated using the following equation: q�j = P*q�Ja + q�a Where, P = Power q�Ja = Junction to ambient temperature (q�Jc + q�Ca) q�a = Ambient temperature (70 �C) The case temperature q�c, can be calculated using the following equation: q�c = P*q�Ca + q�a where, P = Power q�Ca = Case to ambient temperature q�a = Ambient temperature (70 �C) Note 15. Do not power I/O with chip power off. Document #: 38-08032 Rev. *V Page 37 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 8. DC Characteristics Table 13. DC Characteristics Parameter Description Conditions Min Typ Max Unit VCC Supply voltage 3.00 3.3 3.60 V VCC Ramp Up 0 to 3.3 V 200 m�s VIH Input HIGH voltage 2 5.25 V VIL Input LOW voltage 0.5 0.8 V VIH_X Crystal input HIGH voltage 2 5.25 V VIL_X Crystal input LOW voltage 0.5 0.8 V II Input leakage current 0< VIN < VCC �10 m�A VOH Output voltage HIGH IOUT = 4 mA 2.4 V VOL Output LOW voltage IOUT = 4 mA 0.4 V IOH Output current HIGH 4 mA IOL Output current LOW 4 mA CIN Input pin capacitance Except D+/D 10 pF D+/D 15 pF ISUSP Suspend current Connected 300 380[16] m�A CY7C68014/CY7C68016 Disconnected 100 150[16] m�A Suspend current Connected 0.5 1.2[16] mA CY7C68013/CY7C68015 Disconnected 0.3 1.0[16] mA ICC Supply current 8051 running, connected to USB HS 50 85 mA 8051 running, connected to USB FS 35 65 mA TRESET Reset time after valid power VCC min = 3.0 V 5.0 mS Pin reset after powered on 200 m�S 8.1 USB Transceiver USB 2.0 compliant in full speed and high speed modes. Note 16. Measured at Max VCC, 25 �C. Document #: 38-08032 Rev. *V Page 38 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9. AC Electrical Characteristics 9.1 USB Transceiver USB 2.0 compliant in full speed and high speed modes. 9.2 Program Memory Read Figure 9-1. Program Memory Read Timing Diagram tCL CLKOUT[17] tAV tAV A[15..0] tSTBH tSTBL PSEN# [18] tDH tACC1 D[7..0] data in tSOEL OE# tSCSL CS# Table 14. Program Memory Read Parameters Parameter Description Min Typ Max Unit Notes tCL 1/CLKOUT Frequency 20.83 ns 48 MHz 41.66 ns 24 MHz 83.2 ns 12 MHz tAV Delay from Clock to Valid Address 0 10.7 ns tSTBL Clock to PSEN Low 0 8 ns tSTBH Clock to PSEN High 0 8 ns tSOEL Clock to OE Low 11.1 ns tSCSL Clock to CS Low 13 ns tDSU Data Setup to Clock 9.6 ns tDH Data Hold Time 0 ns Notes 17. CLKOUT is shown with positive polarity. 18. tACC1 is computed from these parameters as follows: tACC1(24 MHz) = 3*tCL tAV tDSU = 106 ns. tACC1(48 MHz) = 3*tCL tAV tDSU = 43 ns. Document #: 38-08032 Rev. *V Page 39 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.3 Data Memory Read Figure 9-2. Data Memory Read Timing Diagram tCL Stretch = 0 CLKOUT[17] tAV tAV A[15..0] tSTBH tSTBL RD# tSCSL CS# tSOEL OE# tDSU [19] tDH tACC1 D[7..0] data in Stretch = 1 tCL CLKOUT[17] tAV A[15..0] RD# CS# tDSU tDH [19] tACC1 D[7..0] data in Table 15. Data Memory Read Parameters Parameter Description Min Typ Max Unit Notes tCL 1/CLKOUT frequency 20.83 ns 48 MHz 41.66 ns 24 MHz 83.2 ns 12 MHz tAV Delay from clock to valid address 10.7 ns tSTBL Clock to RD LOW 11 ns tSTBH Clock to RD HIGH 11 ns tSCSL Clock to CS LOW 13 ns tSOEL Clock to OE LOW 11.1 ns tDSU Data setup to clock 9.6 ns tDH Data hold time 0 ns When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD# or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the address valid time for which is based on the stretch value Note 19. tACC2 and tACC3 are computed from these parameters as follows: tACC2(24 MHz) = 3*tCL tAV tDSU = 106 ns. tACC2(48 MHz) = 3*tCL tAV tDSU = 43 ns. tACC3(24 MHz) = 5*tCL tAV tDSU = 190 ns. tACC3(48 MHz) = 5*tCL tAV tDSU = 86 ns. Document #: 38-08032 Rev. *V Page 40 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.4 Data Memory Write Figure 9-3. Data Memory Write Timing Diagram tCL CLKOUT tAV tSTBL tSTBH tAV A[15..0] WR# tSCSL CS# tON1 tOFF1 D[7..0] data out Stretch = 1 tCL CLKOUT tAV A[15..0] WR# CS# tON1 tOFF1 D[7..0] data out Table 16. Data Memory Write Parameters Parameter Description Min Max Unit Notes tAV Delay from clock to valid address 0 10.7 ns tSTBL Clock to WR pulse LOW 0 11.2 ns tSTBH Clock to WR pulse HIGH 0 11.2 ns tSCSL Clock to CS pulse LOW 13.0 ns tON1 Clock to data turn-on 0 13.1 ns tOFF1 Clock to data hold time 0 13.1 ns When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD# or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the address valid time for which is based on the stretch value. Document #: 38-08032 Rev. *V Page 41 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.5 PORTC Strobe Feature Timings The RD# and WR# are present in the 100-pin version and the The RD# signal prompts the external logic to prepare the next 128-pin package. In these 100-pin and 128-pin versions, an data byte. Nothing gets sampled internally on assertion of the 8051 control bit can be set to pulse the RD# and WR# pins when RD# signal itself, it is just a prefetch type signal to get the next the 8051 reads from or writes to PORTC. This feature is enabled data byte prepared. So, using it with that in mind easily meets the by setting PORTCSTB bit in CPUCS register. setup time to the next read. The RD# and WR# strobes are asserted for two CLKOUT cycles The purpose of this pulsing of RD# is to allow the external when PORTC is accessed. peripheral to know that the 8051 is done reading PORTC and the data was latched into PORTC three CLKOUT cycles before The WR# strobe is asserted two clock cycles after PORTC is asserting the RD# signal. After the RD# is pulsed, the external updated and is active for two clock cycles after that, as shown in logic can update the data on PORTC. Figure 9-4. Following is the timing diagram of the read and write strobing As for read, the value of PORTC three clock cycles before the function on accessing PORTC. Refer to Section 9.3 and Section assertion of RD# is the value that the 8051 reads in. The RD# is 9.4 for details on propagation delay of RD# and WR# signals. pulsed for 2 clock cycles after 3 clock cycles from the point when the 8051 has performed a read function on PORTC. Figure 9-4. WR# Strobe Function when PORTC is Accessed by 8051 tCLKOUT CLKOUT PORTC IS UPDATED tSTBL tSTBH WR# Figure 9-5. RD# Strobe Function when PORTC is Accessed by 8051 tCLKOUT CLKOUT 8051 READS PORTC DATA CAN BE UPDATED BY EXTERNAL LOGIC DATA MUST BE HELD FOR 3 CLK CYLCES tSTBL tSTBH RD# Document #: 38-08032 Rev. *V Page 42 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.6 GPIF Synchronous Signals Figure 9-6. GPIF Synchronous Signals Timing Diagram[20] tIFCLK IFCLK tSGA GPIFADR[8:0] RDYX tSRY tRYH DATA(input) valid tSGD tDAH CTLX tXCTL DATA(output) N N+1 tXGD Table 17. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK[20, 21] Typ Parameter Description Min Max Unit Min Max tIFCLK IFCLK Period 20.83 ns tSRY RDYX to Clock Setup Time 8.9 ns tRYH Clock to RDYX 0 ns tSGD GPIF Data to Clock Setup Time 9.2 ns tDAH GPIF Data Hold Time 0 ns tSGA Clock to GPIF Address Propagation Delay 7.5 ns tXGD Clock to GPIF Data Output Propagation Delay 11 ns tXCTL Clock to CTLX Output Propagation Delay 6.7 ns tIFCLKR IFCLK rise time 900 ps tIFCLKF IFCLK fall time 900 ps tIFCLKOD IFCLK Output duty cycle 49 51 % tIFCLKJ IFCLK jitter peak to peak 300 ps Table 18. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK[21] Parameter Description Min Max Unit tIFCLK IFCLK Period[22] 20.83 200 ns tSRY RDYX to Clock Setup Time 2.9 ns tRYH Clock to RDYX 3.7 ns tSGD GPIF Data to Clock Setup Time 3.2 ns tDAH GPIF Data Hold Time 4.5 ns tSGA Clock to GPIF Address Propagation Delay 11.5 ns tXGD Clock to GPIF Data Output Propagation Delay 15 ns tXCTL Clock to CTLX Output Propagation Delay 10.7 ns Notes 20. Dashed lines denote signals with programmable polarity. 21. GPIF asynchronous RDYx signals have a minimum setup time of 50 ns when using internal 48 MHz IFCLK. 22. IFCLK must not exceed 48 MHz. Document #: 38-08032 Rev. *V Page 43 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.1 Slave FIFO Synchronous Read Figure 9-7. Slave FIFO Synchronous Read Timing Diagram[20] tIFCLK IFCLK tSRD tRDH SLRD tXFLG FLAGS DATA N N+1 tOEon tXFD tOEoff SLOE Table 19. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK[21] Typ Parameter Description Min Max Unit Min Max tIFCLK IFCLK period 20.83 ns tSRD SLRD to clock setup time 18.7 ns tRDH Clock to SLRD hold time 0 ns tOEon SLOE turn on to FIFO data valid 10.5 ns tOEoff SLOE turn off to FIFO data hold 10.5 ns tXFLG Clock to FLAGS output propagation delay 9.5 ns tXFD Clock to FIFO data output propagation delay 11 ns tIFCLKR IFCLK rise time 900 ps tIFCLKF IFCLK fall time 900 ps tIFCLKOD IFCLK Output duty cycle 49 51 % tIFCLKJ IFCLK jitter peak to peak 300 ps Document #: 38-08032 Rev. *V Page 44 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 20. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK[21] Parameter Description Min Max Unit tIFCLK IFCLK period 20.83 200 ns tSRD SLRD to clock setup time 12.7 ns tRDH Clock to SLRD hold time 3.7 ns tOEon SLOE turn on to FIFO data valid 10.5 ns tOEoff SLOE turn off to FIFO data hold 10.5 ns tXFLG Clock to FLAGS output propagation delay 13.5 ns tXFD Clock to FIFO data output propagation delay 15 ns 9.8 Slave FIFO Asynchronous Read Figure 9-8. Slave FIFO Asynchronous Read Timing Diagram[20] tRDpwh SLRD tRDpwl tXFLG tXFD FLAGS DATA N N+1 tOEon tOEoff SLOE Table 21. Slave FIFO Asynchronous Read Parameters[23] Parameter Description Min Max Unit tRDpwl SLRD pulse width LOW 50 ns tRDpwh SLRD pulse width HIGH 50 ns tXFLG SLRD to FLAGS output propagation delay 70 ns tXFD SLRD to FIFO data output propagation delay 15 ns tOEon SLOE turn-on to FIFO data valid 10.5 ns tOEoff SLOE turn-off to FIFO data hold 10.5 ns Note 23. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz. Document #: 38-08032 Rev. *V Page 45 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.9 Slave FIFO Synchronous Write Figure 9-9. Slave FIFO Synchronous Write Timing Diagram[20] tIFCLK IFCLK tWRH SLWR tSWR DATA Z N Z tSFD tFDH FLAGS tXFLG Table 22. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK[21] Parameter Description Min Max Unit tIFCLK IFCLK period 20.83 ns tSWR SLWR to clock setup time 10.4 ns tWRH Clock to SLWR hold time 0 ns tSFD FIFO data to clock setup time 9.2 ns tFDH Clock to FIFO data hold time 0 ns tXFLG Clock to FLAGS output propagation time 9.5 ns Table 23. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK[21] Parameter Description Min Max Unit tIFCLK IFCLK Period 20.83 200 ns tSWR SLWR to clock setup time 12.1 ns tWRH Clock to SLWR hold time 3.6 ns tSFD FIFO data to clock setup time 3.2 ns tFDH Clock to FIFO data hold time 4.5 ns tXFLG Clock to FLAGS output propagation time 13.5 ns Document #: 38-08032 Rev. *V Page 46 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.10 Slave FIFO Asynchronous Write Figure 9-10. Slave FIFO Asynchronous Write Timing Diagram[20] tWRpwh SLWR SLWR/SLCS# tWRpwl tSFD tFDH DATA tXFD FLAGS Table 24. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK [23] Parameter Description Min Max Unit tWRpwl SLWR pulse LOW 50 ns tWRpwh SLWR pulse HIGH 70 ns tSFD SLWR to FIFO DATA setup time 10 ns tFDH FIFO DATA to SLWR hold time 10 ns tXFD SLWR to FLAGS output propagation delay 70 ns 9.11 Slave FIFO Synchronous Packet End Strobe Figure 9-11. Slave FIFO Synchronous Packet End Strobe Timing Diagram[20] IFCLK tPEH PKTEND tSPE FLAGS tXFLG Table 25. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK[21] Parameter Description Min Max Unit tIFCLK IFCLK period 20.83 ns tSPE PKTEND to clock setup time 14.6 ns tPEH Clock to PKTEND hold time 0 ns tXFLG Clock to FLAGS output propagation delay 9.5 ns Table 26. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK[21] Parameter Description Min Max Unit tIFCLK IFCLK period 20.83 200 ns tSPE PKTEND to clock setup time 8.6 ns tPEH Clock to PKTEND hold time 2.5 ns tXFLG Clock to FLAGS output propagation delay 13.5 ns Document #: 38-08032 Rev. *V Page 47 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A There is no specific timing requirement that should be met for caused the last byte or word to be clocked into the previous auto asserting PKTEND pin to asserting SLWR. PKTEND can be committed packet. Figure 9-12 shows this scenario. X is the asserted with the last data value clocked into the FIFOs or value the AUTOINLEN register is set to when the IN endpoint is thereafter. The setup time tSPE and the hold time tPEH must be configured to be in auto mode. met. Figure 9-12 shows a scenario where two packets are committed. Although there are no specific timing requirements for the The first packet gets committed automatically when the number PKTEND assertion, there is a specific corner case condition that of bytes in the FIFO reaches X (value set in AUTOINLEN needs attention while using the PKTEND to commit a one byte register) and the second one byte/word short packet being or word packet. There is an additional timing requirement that committed manually using PKTEND. needs to be met when the FIFO is configured to operate in auto Note that there is at least one IFCLK cycle timing between the mode and it is required to send two packets back to back: a full assertion of PKTEND and clocking of the last byte of the previous packet (full defined as the number of bytes in the FIFO meeting packet (causing the packet to be committed automatically). the level set in AUTOINLEN register) committed automatically Failing to adhere to this timing results in the FX2 failing to send followed by a short one byte or word packet committed manually the one byte or word short packet. using the PKTEND pin. In this scenario, the user must ensure to assert PKTEND at least one clock cycle after the rising edge that Figure 9-12. Slave FIFO Synchronous Write Sequence and Timing Diagram[20] tIFCLK IFCLK tSFA tFAH FIFOADR >= tSWR >= tWRH SLWR tSFD tFDH tSFD tFDH tSFD tFDH tSFD tFDH tSFD tFDH tSFD tFDH X-4 X-2 X-1 1 X-3 X DATA At least one IFCLK cycle tSPE tPEH PKTEND 9.12 Slave FIFO Asynchronous Packet End Strobe Figure 9-13. Slave FIFO Asynchronous Packet End Strobe Timing Diagram[20] tPEpwh PKTEND tPEpwl FLAGS tXFLG Table 27. Slave FIFO Asynchronous Packet End Strobe Parameters[23] Parameter Description Min Max Unit tPEpwl PKTEND pulse width LOW 50 ns tPWpwh PKTEND pulse width HIGH 50 ns tXFLG PKTEND to FLAGS output propagation delay 115 ns Document #: 38-08032 Rev. *V Page 48 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.13 Slave FIFO Output Enable Figure 9-14. Slave FIFO Output Enable Timing Diagram[20] SLOE tOEoff tOEon DATA Table 28. Slave FIFO Output Enable Parameters Parameter Description Min Max Unit tOEon SLOE assert to FIFO DATA output 10.5 ns tOEoff SLOE deassert to FIFO DATA hold 10.5 ns 9.14 Slave FIFO Address to Flags/Data Figure 9-15. Slave FIFO Address to Flags/Data Timing Diagram[20] FIFOADR [1.0] tXFLG FLAGS tXFD DATA N N+1 Table 29. Slave FIFO Address to Flags/Data Parameters Parameter Description Min Max Unit tXFLG FIFOADR[1:0] to FLAGS output propagation delay 10.7 ns tXFD FIFOADR[1:0] to FIFODATA output propagation delay 14.3 ns 9.15 Slave FIFO Synchronous Address Figure 9-16. Slave FIFO Synchronous Address Timing Diagram[20] IFCLK SLCS/FIFOADR [1:0] tSFA tFAH Table 30. Slave FIFO Synchronous Address Parameters [21] Parameter Description Min Max Unit tIFCLK Interface clock period 20.83 200 ns tSFA FIFOADR[1:0] to clock setup time 25 ns tFAH Clock to FIFOADR[1:0] hold time 10 ns Document #: 38-08032 Rev. *V Page 49 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.16 Slave FIFO Asynchronous Address Figure 9-17. Slave FIFO Asynchronous Address Timing Diagram[20] SLCS/FIFOADR [1:0] tFAH tSFA SLRD/SLWR/PKTEND Table 31. Slave FIFO Asynchronous Address Parameters[23] Parameter Description Min Max Unit tSFA FIFOADR[1:0] to SLRD/SLWR/PKTEND setup time 10 ns tFAH RD/WR/PKTEND to FIFOADR[1:0] hold time 10 ns 9.17 Sequence Diagram 9.17.1 Single and Burst Synchronous Read Example Figure 9-18. Slave FIFO Synchronous Read Sequence and Timing Diagram[20] tIFCLK IFCLK tSFA tSFA tFAH tFAH FIFOADR t=0 T=0 tSRD tRDH >= tSRD >= tRDH SLRD t=3 t=2 T=3 T=2 SLCS tXFLG FLAGS tXFD tXFD tXFD tXFD Data Driven: N N+4 N+1 N+1 N+2 N+3 DATA tOEon tOEon tOEoff tOEoff SLOE t=4 T=4 T=1 t=1 Figure 9-19. Slave FIFO Synchronous Sequence of Events Diagram IFCLK IFCLK IFCLK IFCLK IFCLK IFCLK IFCLK IFCLK IFCLK IFCLK NN N+1 N+1 N+1 N+2 N+3 N+4 N+4 N+4 FIFO POINTER SLOE SLOE SLRD SLOE SLRD SLRD SLOE SLRD FIFO DATA BUS Not Driven Driven: N N+1 Not Driven N+1 N+2 N+3 N+4 N+4 Not Driven Document #: 38-08032 Rev. *V Page 50 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 9-18 on page 50 shows the timing relationship of the �% The FIFO pointer is updated on the rising edge of the IFCLK, SLAVE FIFO signals during a synchronous FIFO read using while SLRD is asserted. This starts the propagation of data IFCLK as the synchronizing clock. The diagram illustrates a from the newly addressed location to the data bus. After a single read followed by a burst read. propagation delay of tXFD (measured from the rising edge of IFCLK) the new data value is present. N is the first data value �% At t = 0 the FIFO address is stable and the signal SLCS is read from the FIFO. To have data on the FIFO data bus, SLOE asserted (SLCS may be tied low in some applications). Note MUST also be asserted. that tSFA has a minimum of 25 ns. This means when IFCLK is The same sequence of events are shown for a burst read and running at 48 MHz, the FIFO address setup time is more than are marked with the time indicators of T = 0 through 5. one IFCLK cycle. Note For the burst mode, the SLRD and SLOE are left asserted �% At t = 1, SLOE is asserted. SLOE is an output enable only, during the entire duration of the read. In the burst read mode, whose sole function is to drive the data bus. The data that is when SLOE is asserted, data indexed by the FIFO pointer is on driven on the bus is the data that the internal FIFO pointer is the data bus. During the first read cycle, on the rising edge of the currently pointing to. In this example it is the first data value in clock the FIFO pointer is updated and increments to point to the FIFO. Note: the data is pre-fetched and is driven on the bus address N+1. For each subsequent rising edge of IFCLK, while when SLOE is asserted. the SLRD is asserted, the FIFO pointer is incremented and the �% At t = 2, SLRD is asserted. SLRD must meet the setup time of next data value is placed on the data bus. tSRD (time from asserting the SLRD signal to the rising edge of the IFCLK) and maintain a minimum hold time of tRDH (time from the IFCLK edge to the deassertion of the SLRD signal). If the SLCS signal is used, it must be asserted before SLRD is asserted (The SLCS and SLRD signals must both be asserted to start a valid read condition). 9.17.2 Single and Burst Synchronous Write Figure 9-20. Slave FIFO Synchronous Write Sequence and Timing Diagram[20] tIFCLK IFCLK tSFA tSFA tFAH tFAH FIFOADR >= tWRH t=0 tSWR tWRH T=0 >= tSWR SLWR T=2 T=5 t=2 t=3 SLCS tXFLG tXFLG FLAGS tSFD tFDH tSFD tFDH tSFD tFDH tSFD tFDH N+1 N+3 N N+2 DATA T=3 T=4 t=1 T=1 tSPE tPEH PKTEND Document #: 38-08032 Rev. *V Page 51 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 9-20 shows the timing relationship of the SLAVE FIFO There is no specific timing requirement that should be met for signals during a synchronous write using IFCLK as the asserting PKTEND signal with regards to asserting the SLWR synchronizing clock. The diagram illustrates a single write signal. PKTEND can be asserted with the last data value or followed by burst write of 3 bytes and committing all 4 bytes as thereafter. The only requirement is that the setup time tSPE and a short packet using the PKTEND pin. the hold time tPEH must be met. In the scenario of Figure 9-20, the number of data values committed includes the last value �% At t = 0 the FIFO address is stable and the signal SLCS is written to the FIFO. In this example, both the data value and the asserted. (SLCS may be tied low in some applications) Note PKTEND signal are clocked on the same rising edge of IFCLK. that tSFA has a minimum of 25 ns. This means when IFCLK is PKTEND can also be asserted in subsequent clock cycles. The running at 48 MHz, the FIFO address setup time is more than FIFOADDR lines should be held constant during the PKTEND one IFCLK cycle. assertion. �% At t = 1, the external master/peripheral must outputs the data Although there are no specific timing requirement for the value onto the data bus with a minimum set up time of tSFD PKTEND assertion, there is a specific corner case condition that before the rising edge of IFCLK. needs attention while using the PKTEND to commit a one byte/word packet. Additional timing requirements exists when �% At t = 2, SLWR is asserted. The SLWR must meet the setup the FIFO is configured to operate in auto mode and it is desired time of tSWR (time from asserting the SLWR signal to the rising to send two packets: a full packet (full defined as the number of edge of IFCLK) and maintain a minimum hold time of tWRH (time bytes in the FIFO meeting the level set in AUTOINLEN register) from the IFCLK edge to the deassertion of the SLWR signal). committed automatically followed by a short one byte or word If the SLCS signal is used, it must be asserted with SLWR or packet committed manually using the PKTEND pin. before SLWR is asserted (The SLCS and SLWR signals must both be asserted to start a valid write condition). In this case, the external master must ensure to assert the PKTEND pin at least one clock cycle after the rising edge that �% While the SLWR is asserted, data is written to the FIFO and on caused the last byte or word that needs to be clocked into the the rising edge of the IFCLK, the FIFO pointer is incremented. previous auto committed packet (the packet with the number of The FIFO flag is also updated after a delay of tXFLG from the bytes equal to what is set in the AUTOINLEN register). Refer to rising edge of the clock. Figure 9-12 on page 48 for further details on this timing. The same sequence of events are also shown for a burst write and are marked with the time indicators of T = 0 through 5. Note For the burst mode, SLWR and SLCS are left asserted for the entire duration of writing all the required data values. In this burst write mode, after the SLWR is asserted, the data on the FIFO data bus is written to the FIFO on every rising edge of IFCLK. The FIFO pointer is updated on each rising edge of IFCLK. In Figure 9-20, after the four bytes are written to the FIFO, SLWR is deasserted. The short 4 byte packet can be committed to the host by asserting the PKTEND signal. Document #: 38-08032 Rev. *V Page 52 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.17.3 Sequence Diagram of a Single and Burst Asynchronous Read Figure 9-21. Slave FIFO Asynchronous Read Sequence and Timing Diagram[20] tFAH tSFA tFAH tSFA FIFOADR t=0 tRDpwl tRDpwh tRDpwl tRDpwh tRDpwl tRDpwh tRDpwl tRDpwh T=0 SLRD t=3 t=2 T=2 T=3 T=4 T=5 T=6 SLCS tXFLG tXFLG FLAGS tXFD tXFD tXFD tXFD Data (X) N+3 N N N+1 N+2 DATA Driven tOEon tOEoff tOEon tOEoff SLOE t=4 T=1 T=7 t=1 Figure 9-22. Slave FIFO Asynchronous Read Sequence of Events Diagram SLOE SLRD SLRD SLOE SLOE SLRD SLRD SLRD SLRD SLOE FIFO POINTER NN N N+1 N+1 N+1 N+1 N+2 N+2 N+3 N+3 FIFO DATA BUS Not Driven Driven: X N N Not Driven N N+1 N+1 N+2 N+2 Not Driven Figure 9-21 shows the timing relationship of the SLAVE FIFO �% The data that is driven, after asserting SLRD, is the updated signals during an asynchronous FIFO read. It shows a single data from the FIFO. This data is valid after a propagation delay read followed by a burst read. of tXFD from the activating edge of SLRD. In Figure 9-21, data N is the first valid data read from the FIFO. For data to appear �% At t = 0 the FIFO address is stable and the SLCS signal is on the data bus during the read cycle (SLRD is asserted), SLOE asserted. must be in an asserted state. SLRD and SLOE can also be tied together. �% At t = 1, SLOE is asserted. This results in the data bus being driven. The data that is driven on to the bus is previous data, The same sequence of events is also shown for a burst read it data that was in the FIFO from a prior read cycle. marked with T = 0 through 5. �% At t = 2, SLRD is asserted. The SLRD must meet the minimum Note In burst read mode, during SLOE is assertion, the data bus active pulse of tRDpwl and minimum de-active pulse width of is in a driven state and outputs the previous data. After SLRD is tRDpwh. If SLCS is used then, SLCS must be asserted before asserted, the data from the FIFO is driven on the data bus (SLOE SLRD is asserted (The SLCS and SLRD signals must both be must also be asserted) and then the FIFO pointer is asserted to start a valid read condition.) incremented. Document #: 38-08032 Rev. *V Page 53 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 9.17.4 Sequence Diagram of a Single and Burst Asynchronous Write Figure 9-23. Slave FIFO Asynchronous Write Sequence and Timing Diagram[20] tSFA tFAH tSFA tFAH FIFOADR t=0 T=0 tWRpwl tWRpwh tWRpwl tWRpwh tWRpwl tWRpwh tWRpwl tWRpwh SLWR t =1 t=3 T=4 T=1 T=3 T=6 T=7 T=9 SLCS tXFLG tXFLG FLAGS tSFD tFDH tSFD tFDH tSFD tFDH tSFD tFDH N N+1 N+2 N+3 DATA t=2 T=8 T=2 T=5 tPEpwl tPEpwh PKTEND Figure 9-23 shows the timing relationship of the SLAVE FIFO The same sequence of events are shown for a burst write and is write in an asynchronous mode. The diagram shows a single indicated by the timing marks of T = 0 through 5. write followed by a burst write of 3 bytes and committing the 4 Note In the burst write mode, after SLWR is deasserted, the data byte short packet using PKTEND. is written to the FIFO and then the FIFO pointer is incremented to the next byte in the FIFO. The FIFO pointer is post �% At t = 0 the FIFO address is applied, insuring that it meets the incremented. setup time of tSFA. If SLCS is used, it must also be asserted (SLCS may be tied low in some applications). In Figure 9-23 after the four bytes are written to the FIFO and SLWR is deasserted, the short 4 byte packet can be committed �% At t = 1 SLWR is asserted. SLWR must meet the minimum to the host using the PKTEND. The external device should be active pulse of tWRpwl and minimum de-active pulse width of designed to not assert SLWR and the PKTEND signal at the tWRpwh. If the SLCS is used, it must be asserted with SLWR or same time. It should be designed to assert the PKTEND after before SLWR is asserted. SLWR is deasserted and met the minimum deasserted pulse �% At t = 2, data must be present on the bus tSFD before the width. The FIFOADDR lines have to held constant during the deasserting edge of SLWR. PKTEND assertion. �% At t = 3, deasserting SLWR causes the data to be written from the data bus to the FIFO and then increments the FIFO pointer. The FIFO flag is also updated after tXFLG from the deasserting edge of SLWR. Document #: 38-08032 Rev. *V Page 54 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 10. Ordering Information Table 32. Ordering Information 8051 Address Ordering Code Package Type RAM Size # Prog I/Os Serial Debug[24] /Data Busses Ideal for Battery Powered Applications CY7C68014A-128AXC 128 TQFP Pb-free 16 K 40 16-/8-bit Y CY7C68014A-100AXC 100 TQFP Pb-free 16 K 40 Y CY7C68014A-56PVXC 56 SSOP Pb-free 16 K 24 N CY7C68014A-56LTXC 56 QFN - Pb-free 16 K 24 N CY7C68016A-56LTXC 56 QFN - Pb-free 16 K 26 N CY7C68016A-56LTXCT 56 QFN - Pb-free 16 K 26 N Ideal for Non Battery Powered Applications CY7C68013A-128AXC 128 TQFP Pb-free 16 K 40 16-/8-bit Y CY7C68013A-128AXI 128 TQFP Pb-free (Industrial) 16 K 40 16-/8-bit Y CY7C68013A-100AXC 100 TQFP Pb-free 16 K 40 Y CY7C68013A-100AXI 100 TQFP Pb-free (Industrial) 16 K 40 Y CY7C68013A-56PVXC 56 SSOP Pb-free 16 K 24 N CY7C68013A-56PVXCT 56 SSOP Pb-free 16 K 24 N CY7C68013A-56PVXI 56 SSOP Pb-free (Industrial) 16 K 24 N CY7C68013A-56BAXC 56 VFBGA Pb-free 16 K 24 N CY7C68013A-56BAXCT 56 VFBGA Pb-free 16 K 24 N CY7C68013A-56LTXC 56 QFN Pb-free 16 K 24 N CY7C68013A-56LTXCT 56 QFN Pb-free 16 K 24 N CY7C68013A-56LTXI 56 QFN Pb-free (Industrial) 16 K 24 N CY7C68015A-56LTXC 56 QFN Pb-free 16 K 26 N Development Tool Kit CY3684 EZ-USB FX2LP development kit Reference Design Kit CY4611B USB 2.0 to ATA/ATAPI reference design using EZ-USB FX2LP Ordering Code Definitions CY 7 C 68 XXXX - XXXXX (C, I) (T) Tape and Reel Thermal Rating: C = Commercial I = Industrial Package Type: LTX = QFN (Saw Type) Pb-free LFX = QFN (Punch Type) Pb-free Part Number Family Code: 68 = USB Technology Code: C = CMOS Marketing Code: 7 = Cypress Products Company ID: CY = Cypress Note 24. As UART is not available in the 56-pin package of CY7C68013A, serial port debugging using Keil Monitor is not possible. Document #: 38-08032 Rev. *V Page 55 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 11. Package Diagrams The FX2LP is available in five packages: �% 56-pin SSOP �% 56-pin QFN �% 100-pin TQFP �% 128-pin TQFP �% 56-ball VFBGA Figure 11-1. 56-Pin Shrunk Small Outline Package O56 (51-85062) 51-85062 *E Document #: 38-08032 Rev. *V Page 56 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 11-2. 56-Pin QFN 8 � 8 mm Sawn Version (001-53450) 001-53450 *B Document #: 38-08032 Rev. *V Page 57 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 11-3. 100-Pin Thin Plastic Quad Flatpack (14 � 20 � 1.4 mm) A100RA (51-85050) 51-85050 *D Document #: 38-08032 Rev. *V Page 58 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 11-4. 128-Pin Thin Plastic Quad Flatpack (14 � 20 � 1.4 mm) A128 (51-85101) 51-85101 *E Document #: 38-08032 Rev. *V Page 59 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 11-5. 56-Pin VFBGA (5 � 5 � 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56 (001-03901) 001-03901 *E Document #: 38-08032 Rev. *V Page 60 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 12. PCB Layout Recommendations Follow these recommendations to ensure reliable high �% Bypass and flyback caps on VBus, near connector, are performance operation:[25] recommended. �% Four layer impedance controlled boards are required to �% DPLUS and DMINUS trace lengths should be kept to within maintain signal quality. 2 mm of each other in length, with preferred length of 20 to 30 mm. �% Specify impedance targets (ask your board vendor what they can achieve). �% Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to split under these traces. �% To control impedance, maintain trace widths and trace spacing. �% Do not place vias on the DPLUS or DMINUS trace routing. �% Minimize stubs to minimize reflected signals. �% Isolate the DPLUS and DMINUS traces from all other signal �% Connections between the USB connector shell and signal traces by no less than 10 mm. ground must be near the USB connector. Note 25. Source for recommendations: EZ-USB FX2"!PCB Design Recommendations, http://www.cypress.com and High Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf. Document #: 38-08032 Rev. *V Page 61 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 13. Quad Flat Package No Leads (QFN) Package Design Notes Electrical contact of the part to the Printed Circuit Board (PCB) For further information on this package design refer to is made by soldering the leads on the bottom surface of the Application Notes for Surface Mount Assembly of Amkor's package to the PCB. Hence, special attention is required to the MicroLeadFrame (MLF) Packages. You can find this on Amkor's heat transfer area below the package to provide a good thermal website http://www.amkor.com. bond to the circuit board. Design a Copper (Cu) fill in the PCB as The application note provides detailed information about board a thermal pad under the package. Heat is transferred from the mounting guidelines, soldering flow, rework process, etc. FX2LP through the device s metal paddle on the bottom side of Figure 13-1 shows a cross-sectional area underneath the the package. Heat from here is conducted to the PCB at the package. The cross section is of only one via. The solder paste thermal pad. It is then conducted from the thermal pad to the template should be designed to allow at least 50% solder PCB inner ground plane by a 5 � 5 array of via. A via is a plated coverage. The thickness of the solder paste template should be through hole in the PCB with a finished diameter of 13 mil. The 5 mil. Use the No Clean type 3 solder paste for mounting the part. QFN s metal die paddle must be soldered to the PCB s thermal Nitrogen purge is recommended during reflow. pad. Solder mask is placed on the board top side over each via to resist solder flow into the via. The mask on the top side also Figure 13-2 is a plot of the solder mask pattern and Figure 13-3 minimizes outgassing during the solder reflow process. displays an X-Ray image of the assembly (darker areas indicate solder). Figure 13-1. Cross-section of the Area Underneath the QFN Package 0.017 dia Solder Mask Cu Fill Cu Fill 0.013 dia PCB Material PCB Material Via hole for thermally connecting the This figure only shows the top three layers of the QFN to the circuit board ground plane. circuit board: Top Solder, PCB Dielectric, and the Ground Plane Figure 13-2. Plot of the Solder Mask (White Area) Figure 13-3. X-ray Image of the Assembly Document #: 38-08032 Rev. *V Page 62 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Acronyms Document Conventions Acronyms Used in this Document Units of Measure Acronym Description Symbol Unit of Measure ASIC application specific integrated circuit KHz kilohertz ATA advanced technology attachment mA milliamperes DID device identifier Mbps megabits per second DSL digital service line MBPs megabytes per second DSP digital signal processor MHz megahertz ECC error correction code uA microamperes EEPROM electrically erasable programmable read only V volts memory EPP enhanced parallel port FIFO first in first out GPIF general programmable interface GPIO general purpose input output I/O input output LAN local area network MPEG moving picture experts group PCMCIA personal computer memory card international association PID product identifier PLL phase locked loop QFN quad flat no leads RAM random access memory SIE serial interface engine SOF start of frame SSOP super small outline package TQFP thin quad flat pack USARTS universal serial asynchronous receiver/trans- mitter USB universal serial bus UTOPIA universal test and operations physical-layer interface VFBGA very fine ball grid array VID vendor identifier Document #: 38-08032 Rev. *V Page 63 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document History Page Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB� FX2LP"! USB Microcontroller High- Speed USB Peripheral Controller Document Number: 38-08032 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 124316 VCS 03/17/03 New datasheet *A 128461 VCS 09/02/03 Added PN CY7C68015A throughout datasheet Modified Figure 2-1 to add ECC block and fix errors Removed word compatible where associated with I2C Corrected grammar and formatting in various locations Updated Sections 3.2.1, 3.9, 3.11, Table 8, Section 5.0 Added Sections 3.15, 3.18.4, 3.20 Modified Figure 2-5 for clarity Updated Figure 11-2 to match current spec revision *B 130335 KKV 10/09/03 Restored PRELIMINARY to header (had been removed in error from rev. *A) *C 131673 KKU 02/12/04 Section 8.1 changed certified to compliant Table 13 added parameter VIH_X and VIL_X Added Sequence diagrams Section 9.16 Updated Ordering information with lead-free parts Updated Registry Summary Section 3.12.4:example changed to column 8 from column 9 Updated Figure 9-3 memory write timing Diagram Updated section 3.9 (reset) Updated section 3.15 ECC Generation *D 230713 KKU See ECN Changed Lead free Marketing part numbers in Table 32 as per spec change in 28-00054. *E 242398 TMD See ECN Minor Change: datasheet posted to the web, *F 271169 MON See ECN Added USB-IF Test ID number Added USB 2.0 logo Added values for Isusp, Icc, Power Dissipation, Vih_x, Vil_x Changed VCC from + 10% to + 5% Changed PKTEND to FLAGS output propagation delay (asynchronous interface) in Table 27 from a max value of 70 ns to 115 ns *G 316313 MON See ECN Removed CY7C68013A-56PVXCT part availability Added parts ideal for battery powered applications: CY7C68014A, CY7C68016A Provided additional timing restrictions and requirement about the use of PKETEND pin to commit a short one byte/word packet subsequent to committing a packet automatically (when in auto mode). Added Min Vcc Ramp Up time (0 to 3.3v) *H 338901 MON See ECN Added information about the AUTOPTR1/AUTOPTR2 address timing with regards to data memory read/write timing diagram. Removed TBD for Min value of Clock to FIFO Data Output Propagation Delay (tXFD) for Slave FIFO Synchronous Read Changed Table 32 to include part CY7C68016A-56LFXC in the part listed for battery powered applications Added register GPCR2 in register summary *I 371097 MON See ECN Added timing for strobing RD#/WR# signals when using PortC strobe feature (Section 9.5) *J 397239 MON See ECN Removed XTALINSRC register from register summary. Changed Vcc margins to +10% Added 56-pin VFBGA Pin Package Diagram Added 56-pin VFBGA definition in pin listing Added RDK part number to the Ordering Information table *K 420505 MON See ECN Remove SLCS from figure in Section 9.10. Removed indications that SLRD can be asserted simultaneously with SLCS in Section 9.17.2 and Section 9.17.3 Added Absolute Maximum Temperature Rating for industrial packages in Section 5. Changed number of packages stated in the description in Section 3. to five. Added Table 12 on Thermal Coefficients for various packages Document #: 38-08032 Rev. *V Page 64 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB� FX2LP"! USB Microcontroller High- Speed USB Peripheral Controller Document Number: 38-08032 Orig. of Submission Rev. ECN No. Description of Change Change Date *L 2064406 CMCC/ See ECN Changed TID number PYRS Removed T0OUT and T1OUT from CY7C68015A/16A Updated tSWR Min value in Figure 9-9 Updated 56-lead QFN package diagram *M 2710327 DPT 05/22/2009 Added 56-Pin QFN (8 X 8 mm) package diagram Updated ordering information for CY7C68013A-56LTXC, CY7C68013A-56LTXI, CY7C68014A-56LTXC, CY7C68015A-56LTXC, and CY7C68016A-56LTXC parts. *N 2727334 ODC 07/01/09 Removed sentence on E-Pad size change from *F revision in the Document History Page Updated 56-Pin Sawn Package Diagram *O 2756202 ODC 08/26/2009 Updated Ordering Information table and added note 24. *P 2785207 ODC 10/12/2009 Added information on Pb-free parts in the Ordering information table. *Q 2811890 ODC 11/20/2009 Updated Program I/Os for the CY7C68016A-56LTXC and CY7C68016A-56LTXCT parts in Ordering Information on page 55. *R 2896281 ODC 03/19/10 Removed inactive parts from the ordering information table. Updated package diagrams.Updated links in Sales, Solutions and Legal Information. *S 3035980 ODC 09/22/10 Updated template. Changed PPM requirement for the external crystal from +/- 10 ppm to +/- 100 ppm under Electrical specifications. Added table of contents, ordering code definitions, acronym table, and units of measure. *T 3161410 AAE 02/03/2011 Replaced 56-Pin QFN 8 � 8 mm Punch Version Package Diagram (Figure 11.2) and 56-Pin QFN 8 � 8 mm Sawn Version Package Diagram (Figure 11.3). Updated Package Diagrams (Figure 11.4, Figure 11.5). *U 3195232 ODC 03/14/2011 Updated table numbering. Added typical values to Table 17 on page 43 and Table 19 on page 44 based on data obtained from SHAK-63 and SHAK 69. Updated Table 12, Thermal Characteristics, on page 37 (CDT 89510) Updated package diagram 001-03901 to *D. *V 3512313 GAYA 02/01/2012 Removed obsolete part CY7C68014A-56BAXC Removed pruned part CY7C68016A-56LFXC Added parts CY7C68013A-56BAXCT and CY7C68013A-56PVXCT Updated Package Diagrams Document #: 38-08032 Rev. *V Page 65 of 66 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive cypress.com/go/automotive PSoC Solutions Clocks & Buffers cypress.com/go/clocks psoc.cypress.com/solutions Interface cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 Lighting & Power Control cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory Optical & Image Sensing cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless � Cypress Semiconductor Corporation, 2003-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-08032 Rev. *V Revised February 7, 2012 Page 66 of 66 > FX2LP is a trademark and EZ-USB is a registered trademark of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.

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