9728252543

Filtr FIR programowalny realizacja VHDL

— It uses W1 signed bit data/coefficients bi LIBRARY Ipm;

USE lpm.lpm_components.ALL;

LIBRARY ieee;

1 1 64 Al

USE ie.

ENTITY fir.prog IS

CENERIC (W1 : integer := 9; — Input bit width

W2 : integer := 18: — Multiplier bit width 2'W1 W3 : integer := 19; — Adder width = W2+log2(L)-l W4 : integer := 11; — Output bit width

Mpipe : integer := 3); — Pipeline steps of multiplier PORT (clk : IN STD.LOGIC;

Load_x : IN STD.LOCIC;

x_in : IN STD_L0CIC_VECT0R(W1-1 DOWNTO 0); y.out : OUT STD_L0CIC_VECT0R(W4-1 DOWNTO 0)1; END fir.prog; ż. rawef i orriascewtcz

Politechnika Warszawska