Cyrix/TI/IBM/ST CPU identification




Identification of Cyrix/TI/IBM/ST CPUs
Copyright 1996-7 by Grzegorz Mazur
All the brand names used here belong to their owners.
Last update: 1997-01-29
Changes: 971014 - some updates on new Cyrix CPUs 970129 - M2, Gx86
and 6x86 info added/corrected 970127 - 6x86 info corrected and expanded
961126 - TI 486 SXL identification described 961119 - 6x86 info expanded
1996-05-20 - numbers corrected for 5x86, 6x86



If got this far, we are sure we have Cyrix or alike (TI, SGS-Thomson) - we
performed the appropriate tests before. The following checks were performed:
CPU compatibility is at least 486 (AC bit in EFLAGS can be toggled).
Divide test gives value 0000, 0004, 0044 (or different from 0095 and 0010).
CPUID is not supported or vendor ID string is "CyrixInstead".



Accessing CPU control registersOur CPU has several internal registers.
The registers are byte-wide and areaccessed using non-interrupted sequence of
two instructions:

write register number to port 22h
read or write the register's content from/to port 23h We shall
write two routines (read and write) providing a convenient means for accessing
the registers.



Checking for DIRsNow we can perform a simple test: if bit 4 of regiter
C3 (MAPEN in CCR3) in CPU control space can be toggled, we are happy to have
Device Identification Registers on chip. So we should read DIRs and look-up the
DIR table below.



Detecting Cx486S with no DIRsIf there are no DIRs and bit 2 of register
C2 can be toggled, we have a rare variety - early Cx486S.



Detecting Cx/TI 486 SLC/DLC and TI 486SXLC/SXLIf there are no DIRs and
the CPU is not Cx486s, it may be one of the following:
Cx/TI 486 SLC/DLC
TI 486 SXLC/SXL
IBM 486SLC/SLC2
IBM CPUs have MSRs and can be detected based on their presence. (This will be
described...)
If there are no MSRs, we should perform two tests: SXL detection and bus width.
SXL family has 8 KB on-chip cache, SLC/DLC - only 1KB. Cache size can be
detected using cache test mechanism (registers TR4 and TR5). The procedure is as
follows:
disable cache
write 200h to TR4
write 1 to TR5
write 2 to TR5
read TR4
if bit 9 of TR4 is set, the CPU has 1 KB cache, otherwise it is SXL-family
chip with 8 KB cache.
Then look up the following table:  




16-bit bus
32-bit bus

1KB cache
Cx486SLC
Cx486DLC

8 KB cache
TI486SXLC
TI486SXLIf we want to be very precise, we can try
to distinguish A/B steppings of these chips by checking for SMM support.



Identification of A/B stepping of 486 SLC/DLC/SXLC/SXLA-step chips do
not support SMM, B-step chips do. The method (published by TI) enables SMM
instructions and checks if a particular SMM instruction is legal. (Coming
soon...)



Identifying the CPU based on DIR contentsThere are two DIR registers
present in most Cyrix chips: DIR0 holds CPU type and DIR1 holds mask revision
info. DIR0 is located at FEh in CPU control register set. DIR1 is located at
FFh. Newer chips may contain three more DIR registers - described in Cx
undocumented section.
On 6x86 CPU DIR access may be blocked, so first we have to enable DIR accesss
by setting MAPEN field of CCR3 register to 0001. The value of CCR3 should be
restored after reading DIRs.
Note that info returned by RESET signature or CPUID may or may NOT resemble
DIR0:DIR1, depending on particular chip type and revision.
The following table lists all the values of DIR0 known to me.

00-0B - 486-like CPUs with 386-like bus

00 486SLC
01 486DLC
02 486SLC2
03 486DLC2
04 486SRx
05 486DRx
06 486SRx2
07 486DRx2
08 486SRu
09 486DRu
0A 486SRu2
0B 486DRu2
10-1F - 486-like CPUs with 486-like bus

10 486S
11 486S2
12 486Se
14 486Se
16 486Se
13 486S2e
15 486S2e
17 486S2e
1A 486DX
1B 486DX2 or DX4 in 2xCLK mode, DIR1 info below:

30 - version 4.0
31 - v4.1
32 - v.4.2
34 - v.4.4
36 - v4.6 (DX4)
1F 486DX4 in 3xCLK mode, DIR1 info below

36 - v4.6
20..27 - early 6x86 CPUs (can be found, I got one with DIR1 = 12) - see
30..37 for more info

21 - 2xCLK

12 -
28..2F - 5x86 CPU (486-like socket)

28 1xCLK, S
29 2xCLK, S
2A 1xCLK, P
2B 2xCLK, P
2C 4xCLK, S
2D 3xCLK, S
2E 4xCLK, P
2F 3xCLK, P Known versions of 5x86 (DIR1 contents):

05
13
30..37 - 6x86 (Pentium-like socket and architecture, 486-like programming
model) (see also 20..27), DIR1 info follows

20, 30 1xCLK, S
21, 31 2xCLK , S
22, 32 1xCLK, P
23, 33 2xCLK, P
24, 34 4xCLK, S
25, 35 3xCLK, S
26, 36 4xCLK, P
27, 37 3xCLK, P DIR1:

0x - very early 6x86 ?
1x - "classic" 6x86

14 - v2.4
15 - v2.5
16 - v2.6
17 - v2.7 or 3.7 - the first with no NT 4.0 problems and the first
with SLOP bit
2x - 6x86L - dual voltage, lower power

20, 21 - preproduction?, believed to support SLOP bit in CCR5
22 - v4.0 - the first commercial version, SLOP no longer supported

4x - MediaGX family - almost complete, 5x86 based PC on a single
chipIf DIR1 is 3xh, the CPU is GXm, otherwise "classic" MediaGX

40 - GXm, 4xCLK
41 - GXi, 3xCLK or GXm, 6xCLK
42 - GXm, 4xCLK
43 - GXm, 6xCLK
44 - MediaGX, 4xCLK, S or GXm, 7xCLK
45 - MediaGX, 3xCLK, S or GXm, 8xCLK
46 - MediaGX, 4xCLK, P or GXm, 7xCLK
47 - MediaGX, 3xCLK, P or GXm, 5xCLK
50..5F - 6x86MX, alias M2 (enhanced 6x86 with MMX)

50 - 1.5xCLK, S
51 - 2xCLK, S
52 - 2.5xCLK, S
53 - 3xCLK, S
54 - 3.5xCLK, S
55 - 4xCLK, S
56 - 4.5xCLK, S
57 - 5xCLK, S
58 - 1.5xCLK, P
59 - 2xCLK, P
5A - 2.5xCLK, P
5B- 3xCLK, P
5C - 3.5xCLK, P
5D - 4xCLK, P
5E - 4.5xCLK, P
5F - 5xCLK, P


Copyright 1996-7 by Grzegorz
Mazur