Lab 7 1

^DX^L WINDLX

Total:

1485 Cycle(s) executed.

ID executed by 1063 Instruction(s). 2 Instruction(s) currently in Pipeline.

Haurdvfir e conf icjuiraifc ioti:

Memory size: 32768 Bytes faddEX-Stages: 1, required Cycles: 2 fmulEX-Stages: 1, required Cycles: 5 fdivEX-Stages: 1, required Cycles: 19 Forwarding enabled.

RAW stalls: 260 (17.51 % of all Cycles). thereof:

LD stalls: 50 (19.23% of RAW stalls) Branch/Jump stalls: 110 (42.31 % of RAW stalls) Floating point stalls: 100 (38.46% of RAW stalls) WAW stalls: 0 (0.00% of all Cycles)

Structural stalls: 0 (0.00% of all Cycles)

Control stalls: 158 (10.64% of all Cycles)

T rap stalls: 3 (0.20% of all Cycles)

Total: 421 Stall(s) (28.35% of all Cycles)

Condicional Eranches):

T otal: 160 (15.05% of all Instructions), thereof: taken: 158 (98.75% of all cond. Branches) not taken: 2 (1.25% of all cond. Branches)

L o ai cł— /Store-Instr uc t ions :

Total: 263 (24.74% of all Instructions), thereof:

Loads: 102 (38.78% of Load-/Store-lnstructions)

Stores: 161 (61.22% of Load-/Store-lnstructions)

Floating point stage instructions:

Total: 50 (4.70% of all Instructions), thereof:

Additions: 0 (0.00% of Floating point stage inst.) Multiplications: 50 (100.00% of Floating point stage inst.) Divisions: 0 (0.00% of Floating point stage inst.)

Tłtaips! :

Traps: 1 (0.09% of all Instructions)