Komparator 2-bitowy:
module compare_2_bit (a_lt_b, a_gt_b, a_eq_b, a1, a0, b0' b1, c0, c1);
input a1, a0, b1, b0;
output a_lt_b, a_gt_b, a_eq_b;
assign a_lt_b= (~a1)&b1|(~a1)&(~a0)&b0|(~a0)&b1&b0;
assign a_gt_b= a1&(~b1)|a0&(~b1)&(~b0)|a1&a0&(~b0);
assign a_eq_b= (~a1)&(~a0)&(~b1)&(~b0)|(~a1)&a0&(~b1)&b0
|a1&a0&b1&b0|a1&(~a0)&b1&(~b0);
endmodule
Komparator 2-bitowy:
module compare2bit (A, B, EQ, GT);
input [1:0] A, B;
output EQ, GT;
wire [1:0] A_B, B_B;
assign A_B[0] = ~A[0];
assign A_B[1] = ~A[1];
assign B_B[0] = ~A[0];
assign B_B[1] = ~A[1];
assign EQ = (A[1]&A[0]&B[1]&B[0]) | (A[1]&A_B[0]&B[1]&B_B[0]) | (A_B[1]&A[0]&B_B[1]&B[0]) | (A_B[1]&A_B[0]&B_B[1]&B_B[0]);
assign GT = (A[1]&B_B[1]) | (A[0]&B_B[1]&B_B[0]) | (A[1]&A[0]&B_B[0]);
endmodule
Komparator 2-bitowy:
module comparator_2bit ( a ,b ,equal ,greater ,lower );
output equal ;
output greater ;
output lower ;
input [1:0] a ;
input [1:0] b ;
assign equal = (a==b) ? 1 : 0;
assign greater = (a>b) ? 1 : 0;
assign lower = (a<b) ? 1 : 0;
endmodule
Grey na binarny:
module GTBmod(out,in);
input [3:0]in;
output [3:0]out;
assign out[3]=in[3];
xor(out[2],out[3],in[2]);
xor(out[1],out[2],in[1]);
xor(out[0],out[1],in[0]);
endmodule
Binarny na Greya:
module bin_to_gray(
input clk,
input [2:0]gray_input,
output reg [2:0]bin_out
);
always@(posedge clk)
begin
bin_out[2] <= gray_input[2];
bin_out[1] <= bin_out[2] ^ gray_input[1];
bin_out[0] <= bin_out[1] ^ gray_input[0];
end
endmodule
Binarny na Greya:
module bintogray(a, b);
input [3:0] a;
output [3:0] g;
assign g(3)=b(3);
assign g(2)=b(3) ^ b(2);
assign g(1)=b(2) ^ b(1);
assign g(0)=b(1) ^ b(0);
endmodule
BCD Watts
0 0000
1 0001
2 0011
3 0010
4 0110
5 1110
6 1010
7 1011
8 1001
9 1000
http://www2.engr.arizona.edu/~slysecky/resources/verilog_tutorial.html
XOR:
module XOR2gate(A, B, F);
input A;
input B;
output F;
reg F;
always @ (A or B)
begin
F <= A ^ B;
end
endmodule
XNOR:
module XNOR2gate(A, B, F);
input A;
input B;
output F;
reg F;
always @ (A or B)
begin
F <= A ~^ B;
end
endmodule
NOR:
module NOR2gate(A, B, F);
input A;
input B;
output F;
reg F;
always @ (A or B)
begin
F <= ~(A | B);
end
endmodule
NAND:
module NAND2gate(A, B, F);
input A;
input B;
output F;
reg F;
always @ (A or B)
begin
F <= ~(A & B);
end
endmodule
AND:
module AND2gate(A, B, F);
input A;
input B;
output F;
reg F;
always @ (A or B)
begin
F <= A & B;
end
endmodule
OR:
module OR2gate(A, B, F);
input A;
input B;
output F;
reg F;
always @ (A or B)
begin
F <= A | B;
end
endmodule
NOT:
module NOTgate1(A, F);
input A;
output F;
reg F;
always @ (A)
begin
F <= ~A;
end
endmodule