L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

L4: Sequential Building Blocks

(Flip

flops, Latches and Registers)

Acknowledgements:

J. Rabaey, A. Chandrakasan, B. Nikolic. Digital Integrated Circuits: A Design Perspective.

Prof. Randy Katz (Unified Microelectronics Corporation Distinguished Professor in

Electrical Engineering and Computer Science at the University of California, Berkeley)

and Prof. Gaetano Borriello (University of Washington Department of Computer

Science & Engineering) from Chapter 2 of R. Katz, G. Borriello. Contemporary Logic Design.

Materials in this lecture are courtesy of the following sources and are used with permission.

2nd ed. Prentice-Hall/Pearson Education, 2005.

Prentice Hall/Pearson, 2003.

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

Combinational Logic Review

Combinational logic circuits are memoryless

No feedback in combinational logic circuits

Output assumes the function implemented by the

logic network, assuming that the switching
transients have settled

Outputs can have multiple logical transitions

before settling to the correct value

Combinational

Circuit

N-1

M-1

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

A Sequential System

Sequential circuits have memory (i.e., remember the past)

The current state is “held” in memory and the next state is
computed based the current state and the current inputs

In a synchronous systems, the

clock signal

orchestrates the

sequence of events

COMBINATIONAL

LOGIC

Registers

Outputs

Next state

CLK

Current State

Inputs

Memory element

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

A Simple Example

N-1

Adding N inputs (N-1 Adders)

D Q

reset

clk

Current_Sum

Using a sequential (serial) approach

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

Implementing State: Bi

stability

i 1

= V

i 2

= V

= V

Point C is

Metastable

= V

Points A and

B are stable

(represent 0 & 1)

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

NOR

based Set

Reset (SR)

Flipflop

Flip-flop refers to a bi-stable element

(

edge-triggered registers are also

called flip-flops

) – this circuit is not clocked and outputs change

“asynchronously” with the inputs

Q Q

0 1

1 0

0 0

SR = 1 0

SR = 0 1

SR = 1 1

SR = 1 0

SR = 1 1

SR = 00, 01

SR = 00, 10

SR = 0 0

SR = 11

SR = 0 0

Reset

Hold

Set

Reset

Forbidden State

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

Making a Clocked Memory Element:

Positive D

Latch

CLK

clk

A Positive D-Latch

Passes input D to output Q when CLK is

high and holds state when clock is low (i.e., ignores input D)

A Latch is level-sensitive:

invert clock for a negative latch

clock

R and S

sample

hold

sample

hold

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

Multiplexor

Based Positive & Negative Latch

out

SEL

Out = sel * in

+ sel * in

2:1 multiplexor

CLK

Positive Latch

CLK

Negative Latch

"remember"

"load"

"data"

"stored value"

clk

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

74HC75 (Positive Latch)

1-2

3-4

Operating Modes

Inputs

Outputs

n-n

Data Enabled

Data Latched

Figures by MIT OpenCourseWare.

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

Building an Edge

Triggered Register

Master-Slave Register

Use negative clock phase to latch inputs into first latch

Use positive clock to change outputs with second latch

View pair as one basic unit

master-slave flip-flop twice as much logic

Master

Slave

CLK

CLK

CLK

D Q

Negative latch

Positive latch

Image by MIT OpenCourseWare.

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

Latches vs. Edge

Triggered Register

Edge triggered device sample inputs on the event edge

Transparent latches sample inputs as long as the clock is
asserted

Timing Diagram:

Behavior the same unless input changes

while the clock is high

7474

7475

Bubble here

for negative

edge triggered

register

Positive edge-triggered

Level-sensitive

latch

D Q

Clk

7474

7475

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

Important Timing Parameters

Setup Time (T

)

Clock:

Periodic Event, causes state of memory
element to change

memory element can be updated on the:
rising edge, falling edge, high level, low level

There is a timing

"window" around the

clocking event

during which the

input must remain

stable and

unchanged in order

to be recognized

There is a timing

"window" around the

clocking event

during which the

input must remain

stable and

unchanged in order

to be recognized

Minimum time before the clocking event by
which the input must be stable

Hold Time (T

)

Minimum time after the clocking event during
which the input must remain stable

Input

Clock

Propagation Delay (T

for an edge-triggered

register and T

for a latch)

Delay overhead of the memory element

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

The J

K Flip

Flop

Eliminate the forbidden state of the SR Flip-flop

Use output feedback to guarantee that R and S are
never both one

Q+

\ Q

100

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

K Master

Slave Register

Correct Toggle

Operation

Master

outputs

Slave

outputs

Set Reset

oggle

1's

Sample inputs while clock high

Sample inputs while clock low

Catch

100

Clk

\ P

\ Q

Is there a problem with this circuit?

CLK

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

Pulse Based Edge

Triggered J

K Register

JK Register Schematic

JK Register Logic Symbol

Input

Output

Input

Output

pLH

Schematic

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

Pulse

Triggered Registers

Ways to design an edge-triggered sequential cell:

Pulse-Based Register

Master-Slave Latches

Clk

Data

Clk

Latch

Data

Clk

Short pulse around clock edge

Pulse registers are widely used in high-performance

microprocessor chips (Sun Microsystems, AMD, Intel, etc.)

The can have a negative setup time!

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

D Flip

Flop vs. Toggle Flip

Flop

Clk

T (Toggle)

Flip-Flop

N-1

Clk

D Flip-Flop

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

Realizing Different Types of Memory

Elements

Characteristic Equations

J-K:

Q+ = D

Q+ = J Q + K Q

Q+ = T Q + T Q

E.g., J=K=0, then Q+ = Q

J=1, K=0, then Q+ = 1
J=0, K=1, then Q+ = 0
J=1, K=1, then Q+ = Q

Implementing One FF in Terms of Another

D implemented with J-K

J-K implemented with D

D Q

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

Design Procedure

Excitation Tables: What are the necessary inputs to cause a particular kind of
change in state?

Implementing D FF with a J-K FF:

1) Start with K-map of Q+ = ƒ(D, Q)

2) Create K-maps for J and K with same inputs (D, Q)

3) Fill in K-maps with appropriate values for J and K

to cause the same state changes as in the original K-map

E.g., D = Q= 0, Q+ = 0

then J = 0, K = X

0 1

Q + = D

0 1

X X

1 0

K = D

0 1

X X

J = D

0 1

D
0
1
0
1

0
1
1
0

0
1
0
1

0
0
1
1

K
X
X

1
0

0
1

X
X

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

Design Procedure (cont.)

Implementing J-K FF with a D FF:

1) K-Map of Q+ = F(J, K, Q)

2,3) Revised K-map using D's excitation table

its the same! that is why design procedure with D FF is simple!

Resulting equation is the combinational logic input to D

to cause same behavior as J-K FF. Of course it is identical
to the characteristic equation for a J-K FF.

0 1 1

1 0 0 1

00 01 11 10

= D = JQ + KQ

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

System Timing Parameters

Clk

Combinational

Logic

Clk

Register Timing Parameters

: worst case rising edge

clock to q delay

cq, cd

: contamination or

minimum delay from
clock to q

: setup time

: hold time

Logic Timing Parameters

logic

: worst case delay

through the combinational
logic network
T

logic,cd

: contamination or

minimum delay
through logic network

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

System Timing (I): Minimum Period

Clk

Combinational

Logic

Clk

CLK

cq,cd

FF1

CLout

l,cd

su2

logic

T > T

+ T

logic

+ T

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

System Timing (II): Minimum Delay

Clk

Combinational

Logic

Clk

CLK

cq,cd

FF1

CLout

l,cd

cq,cd

+ T

logic,cd

> T

hold

CLout

L4: 6.111 Spring 2006

Introductory Digital Systems Laboratory

Shift

Register

all measurements are made

from the clocking event that is,

the rising edge of the clock

Typical parameters for Positive edge-triggered D Register

5ns

Tw 25ns

Tplh

25ns

13ns

Tphl

40ns

25ns

Tsu

20ns

CLK

Tsu

20ns

5ns

CLK

100

CLK

OUT

Shift-register

Document Outline

L4: Sequential Building Blocks(Flip-flops, Latches and Registers)
Combinational Logic Review
A Sequential System
A Simple Example
Implementing State: Bi-stability
NOR-based Set-Reset (SR) Flipflop
Making a Clocked Memory Element:Positive D-Latch
Multiplexor Based Positive & Negative Latch
74HC75 (Positive Latch)
Building an Edge-Triggered Register
Latches vs. Edge-Triggered Register
Important Timing Parameters
The J-K Flip-Flop
J-K Master-Slave Register
Pulse Based Edge-Triggered J-K Register
D Flip-Flop vs. Toggle Flip-Flop
Realizing Different Types of Memory Elements
Design Procedure
Design Procedure (cont.)
System Timing Parameters
System Timing (I): Minimum Period
System Timing (II): Minimum Delay
Shift-Register

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