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h, November. The early sunsets, final leaves
dropping off the trees, and 30° nights here in the
Northeast remind me that the holidays are upon us. It’s
time to prepare for family get-togethers with enormous
meals and never-ending towers of desserts. And the questions are mounting.
Who’s hosting what this year? Who wants what this year? But, before you get
wrapped up in the frenzy, take some time for yourself.
This year, one of your gifts comes early. We’re kicking off the holiday sea-
son with our tightly packed Embedded Development issue. Instead of shop-
ping, shopping, and then shopping some more (think of Pamplona during the
running of the bulls), you can get busy planning your next application. The
ideas you get from reading about the interesting projects in this issue will
keep you down in your own Circuit Cellar throughout the cold winter.
Why not start off by designing an embedded thermal sensor system? A
group of five engineers lead by Divyata Kakumanu joined efforts to create a
stand-alone temperature-sensing system that uses low amounts of power.
Designed with wireless remote sensors, this project could be used for any
number of applications that require electronic control of computing and com-
munication. It is suitable for everything from coffee makers to industrial appli-
cations, in which effective thermal sensing can be critical.
If you work with Java, or perhaps you’ve just been wondering about it,
make sure you turn to page 12 to read Shahzad Umar’s article, “Embedded
Real-Time Java in an MPU.” As he explains, in recent years, Java has
become widely accepted and its popularity continues to grow. Shahzad uses
the Motorola 68HC11 microprocessor to demonstrate the quality of Java tech-
nology. With the Java programming language, you can utilize the full set of
features on the 68HC11.
Also this month, the wait is over for those of you who entered the PSoC
Design Challenge 2002. Using the Cypress MicroSystems PSoC devices, the
entrants produced skillful designs that I’m sure you’ll want to read about. Be
sure you head over to our web site, too, for expanded coverage of the entries.
For the first time, we’re posting the full projects including source code for all
of the winning entries. Additionally, we’ve chosen a number of distinctive
entries to post.
So relax, and forget about dealing with whatever holidays you celebrate.
Forget about getting a turkey, tagging a tree, picking up your in-laws, buying
gifts for every niece and nephew, stringing up lights, and the imminent Secret
Santa fiasco. Unwrap our present to you, and then hibernate in your work-
room. OK, so the hibernation advice is facetious (you’ll still have to pick up
your in-laws), but you should slip away for some much needed relaxation.
4
Issue 148 November 2002
www.circuitcellar.com
CIRCUIT CELLAR
®
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CIRCUIT CELLAR®, THE MAGAZINE FOR COMPUTER APPLICATIONS (ISSN 1528-0608) and Circuit Cellar Online are pub-
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Circuit Cellar® makes no warranties and assumes no responsibility or liability of any kind for errors in these programs or schematics or for the
consequences of any such errors. Furthermore, because of possible variation in the quality and condition of materials and workmanship of read-
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a
’Tis the Season
jennifer.huber@circuitcellar.com
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6
Issue 148 November 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
Embedded Real-Time Java in an MPU
PSoC Design Challenge 2002
Winners Announcement
Efficient, Practical Adders for FPGAs
Vitit Kantabutra, Ph.D., Pasquale Corsonello,
Stefania Perri, Ph.D., and Maria Antonia Iachino
A Low-Power Embedded Thermal Sensor System
Divyata Kakumanu, Joel Jorgenson, Tristan Simetkosky, Conrad
Thomas, and Brian Morlock
ARMs to ARMs
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Task Manager
Jennifer Huber
’Tis the Season
New Product News
edited by John Gorsky
Advertiser’s Index
December Preview
Priority Interrupt
Steve Ciarcia
As Long as the Green Light
Goes On
148
FEATURES
Contest Related Articles
Check out AVR today at www.atmel.com/ad/fastavr
Introducing the Atmel AVR
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can help you beat the pants off your competition.
AVR is a RISC CPU running single cycle instructions.
With its rich, CISC-like instruction set and 32 working registers,
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© 2002 Atmel Corporation. Atmel and the Atmel logo are registered trademarks of Atmel Corporation.
8
Issue 148 November 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
NEW PRODUCT
REPROGRAMMABLE ASIC POSTAGE STAMP
The MUSKETEER is the industry’s first reprogramma-
ble ASIC on a postage-stamp size circuit board that can
be programmed with a vendor’s microcontroller IP by
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The MUSKETEER is directly compatible with STAPL
files created by Actel’s Libero design environment soft-
ware and can be programmed using a host PC’s RS-232
port. The MUSKETEER requires no
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The pictured implementation com-
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Edited by John Gorsky
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www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 148 November 2002
11
Problem 3
—You wish to design a four-way set
associative cache with a total of 8 KB of data
cache. Addresses are 16 bits in length. How
many address bits will be in the tag field?
Contributed by Naveen PN
Problem 4
—The greatest common divisor of two
positive integers x and y, written gcd (x, y), is the
largest integer that divides evenly both x and y.
Write a recursive algorithm to find the GCD of
two numbers.
Contributed by Naveen PN
Problem 1
—A computer with a 64-bit wide data
bus uses 1 Mb × 1 DRAM memory chips. What is
the smallest memory in bytes that this computer
can have?
Contributed by Naveen PN
Problem 2
—An oil-filled capacitor consists of two
plates separated by a dielectric made of oil with a
dielectric constant of 10. The capacitance is 10 µF
and it is charged to 10 V. The oil is drained, leav-
ing air between the plates. The capacitance falls to
1 µF. Does the stored energy level change? If so,
where did the extra energy come from or go to?
Contributed by Naveen PN
You may contact the quizmasters at eq@circuitcellar.com
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STATEMENT REQUIRED BY THE ACT OF AUGUST 12, 1970, TITLE 39, UNITED STATES CODE SHOWING THE OWNERSHIP, MANAGEMENT AND CIRCULATION OF CIRCUIT CELLAR, THE MAGAZINE FOR COMPUTER APPLICATIONS, published monthly at 4 Park Street,
Vernon, CT 06066. Annual subscription price is $21.95. The names and addresses of the Publisher, Editorial Director, and Managing Editor are: Publisher, Daniel Rodrigues, 4 Park Street, Vernon, CT 06066; Editorial Director, Steven Ciarcia, 4 Park Street, Vernon, CT 06066; Managing
Editor, Jennifer Huber, 4 Park Street, Vernon, CT 06066. The owner is Circuit Cellar, Inc., Vernon, CT 06066. The names and addresses of stockholders holding one percent or more of the total amount of stock are: Steven Ciarcia, 4 Park Street, Vernon, CT 06066. The average number of
copies of each issue during the preceding twelve months is: A) Total number of copies printed (net press run) 25,607; B) Paid/Requested Circulation (1) Mail subscriptions: 15,496; (3) Sales through dealers and carriers, street vendors and counter sales: 6,603, C) Total paid circulation:
22,099; D) Free distribution by mail (samples, and other free issues): 0; E) Free distribution outside the mail (carrier, or other means): 302; F) Total free distribution: 302; G) Total Distribution: 22,401; H) Copies not distributed: (1) Office use leftover, estimated newsstand returns, spoiled after
printing: 3,206; I) Total: 25,607. Percent paid and/or requested circulation: 98.65%. Actual number of copies of the single issue published nearest to filing date is October 2002, Issue #147; A) Total number of copies printed (net press run) 24,245; B) Paid/Requested Circulation (1) Mail sub-
scriptions: 14,700; (3) Sales through dealers and carriers, street vendors and counter sales: 5,649, C) Total paid circulation: 20,349; D) Free distribution by mail (samples, and other free issues): 0; E) Free distribution outside the mail (carrier, or other means): 300; F) Total free distribution:
300; G) Total Distribution: 20,649; H) Copies not distributed: (1) Office use leftover, estimated newsstand returns, spoiled after printing: 3,596; I) Total: 24,245. Percent paid and/or requested circulation: 98.55%. I certify that the statements made by me above are correct and complete.
Daniel Rodrigues, Publisher.
CIRCUIT CELLAR
Test Y
Your E
EQ
12
Issue 148 November 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
ecently, Java
technologies
including the Java
programming language
and Java Virtual Machine (JVM) have
received broad acceptance. Today, the
technology is used in embedded sys-
tems and real-time applications. RTJ
Computing made such an effort by
executing a clean-room implementa-
tion of real-time Java with a JVM that
requires no more than 9.8 KB of code
memory and only 100 bytes of data
memory. These specifications make
this version of JVM suitable for test-
ing Java’s real-time capabilities at a
low cost and in an easy-to-manage
embedded system.
For this project, I select-
ed the JVM for the
68HC11-Beta 2. I made
this decision because of
it’s low cost and the avail-
ability of the Motorola
68HC11 8-bit microproces-
sor, which incorporates
various functionalities like
a versatile timing system,
analog-to-digital converter,
serial communication
interface, serial peripheral
interface, and maskable
interrupts. I utilized all of
the inherent properties of this power-
ful microprocessor to test the real-
time implementation of JVM.
My analysis and experimental work
is in accordance with standardized
real-time specifications for Java. These
specifications include the following:
thread scheduling and dispatching;
memory management and hardware
interaction; asynchronous event han-
dling; asynchronous transfer of con-
trol; thread termination; and physical
memory access. Furthermore, I
developed a transaction approach
mechanism (TAM) to render real-
time Java with attributes that can
handle time-triggered events.
In this article, I’ll provide you with
a detailed analysis of the 68HC11’s
timing system and its Java imple-
mentation to exploit its functionali-
ties. This implementation includes
Java class files to implement the
real-time timer required to record
the actual time for various events.
Additionally, I’ll describe the garbage
collector that’s incorporated by this
particular JVM version.
Some constraints were imposed by
the limitations of both the JVM and
68HC11. The most apparent was a
limited memory, so my aim was to
make all of the programs I wrote as
small as possible. Furthermore, I
wrote native methods while imple-
menting various Java class files; there-
fore, the code I’m presenting is not
100% pure Java.
JAVA DEVELOPMENT 101
A battle is taking place over the use
of Java in one of the most important
products in the computer industry, the
Embedded Real-Time
Java in an MPU
r
Java technology is
rapidly gaining accept-
ance among develop-
ers all over the world.
In this article, Shahzad
will walk you through
the process of embed-
ding real-time Java on
a 68HC11. As he
explains the process,
think about ways to
apply the technology
to your own designs.
Shahzad Umar
FEATURE
ARTICLE
Figure 1—
The 32-bit wide data memory blocks have assumed loca-
tions and contents. Accumulator D holds the address of the first location
of the data memory blocks.
0000FA38
Null
Null
Null
Null
Null
Null
Null
3345
First parameter
32-bit Array elements
Memory location 0x3349
Accumulator A
Accumulator B
Memory address of first byte
of first parameter
Accumulator D
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 148 November 2002
13
ments a class CPU that
includes these methods.
Assume that you’re
required to write a native
method that will read an
integer at a specified memo-
ry address supplied as a
parameter. You can see an
example of this in Listing 1).
When this program is run
and the native method is
invoked, the JVM will perform two jobs.
First, the JVM passes the pointer to
an array of 32-bit long data elements
to the underlying CPU. In this case,
the pointer is passed to the 16-bit
accumulator register D of the
68HC11. Each array element con-
tains one parameter as specified by
the Java method prototype. The first
method parameter is at array posi-
tion zero, and the second parameter
is at position one.
If the native method wasn’t declared
to receive any parameters, then the
array pointer will have an undefined
value and should not be accessed by
the native method.
In this example, the prototype
method is
readInteger, and the
parameter is mem_address of type int.
Assuming that the array is placed in
memory location 0x3345, the high
word from the first parameter—which
is at index 0 of the array—will be
stored at locations 0x3345 to 0x3346.
The low word will be stored at loca-
tions 0x3347 to 0x3348 (see Figure 1).
Next, the JVM places an absolute
memory address onto the stack. This
address specifies the memory location
where the native method will place
the return values. If the native
method is declared to return a value,
then the native method must write a
return value at the specified address.
Return values are always 32 bits long
regardless of how the native method is
declared in the Java application.
Native methods must make sure that
unused high-order bytes are set to
zero. Methods not returning values,
which are declared as void, should
ignore this parameter.
Assume that the absolute memory
address for the return value is
0x0000AB32. For the particular exam-
ple I’m using, this is the memory
smart appliance. Developers
want to be able to use Java
to write a real-time embed-
ded application for multi-
ple platforms. One such
platform is the 68HC11
microprocessor.
Java development starts
with an analysis of function-
al requirements. During the
analysis, you must decide,
among other things, which software
components can be implemented in
Java and which ones must be pro-
grammed using native methods.
Obviously, time-critical actions, or
those that require access to the hard-
ware of the target device, must be
implemented as native methods.
After the analysis is complete, the
coding of the Java application can
begin. You can utilize all of the fea-
tures of object-oriented programming
such as inheritance, method overload-
ing, and data encapsulation. The only
limitation that you must keep in
mind is that the software will run on
an 8-bit 68HC11 system with a limit-
ed amount of heap memory. Garbage
collection is provided; however, the
allocation of a large number of active
objects may cause VM to generate an
out-of-memory exception. Also, there
are a limited number of library class-
es. At the moment, these include
classes in the java.lang and
hw.mot68hc11 packages.
To compile class files, the standard
Java compiler is used. The ClassLinker
provided by RTJ Computing performs
class linking and optimization. This
involves reading all of the class files
that comprise the application, replac-
ing symbolic references with offsets
and indexes, and generating the out-
put files. GNU ASXXX assembler ver-
sion 2.10 is used to code native meth-
ods. After coding all of the Java class
and native files, the code is down-
loaded to the target device.
HARDWARE INTERACTION
Interacting with the hardware on
embedded systems is straightforward.
The only requirement is to have a
good understanding of how the JVM
invokes and passes its parameters to
underlying native methods. Embedded
systems are mostly 8- or 16-bit sys-
tems. On the other hand, Java is
designed for 32-bit systems. It might
seem strange, but the following exam-
ple will help to make this clear.
All of the hardware interaction in
an embedded system is based on regis-
ter-based input and output; therefore,
it’s convenient to have Java methods
that can directly read or write byte,
short, and int at the specified memory
address. The hw.mot68hc11 package
provided along with the JVM imple-
Listing 1—
As you can see, this example class file describes native methods in Java. It calls a native
method within its main method to read a memory location.
class Example {
static void main(){
Example my_example = new Example ();
//Creating object of the class example
my_example.readInt(0xFA38);
//Address in hexadecimal at which the integer is suppose
to be read
}
public int readInt(int address){
return readInteger(address);
}
public native int readIntger(int mem_address);
}
0000
AB32
Memory address placed
by JVM onto stack
Stack pointer register
0x9766
Stack
Figure 2—
Take a look at the 68HC11’s 16-bit stack and stack pointer register. A 32-
bit return address is placed on the stack by JVM, whereas the stack pointer register
gives the top of the stack.
14
Issue 148 November 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
address where the native method
readInteger will store the return
value (see Figure 2).
If you’re interested in studying a
Java implementation for a 16-chan-
nel, built-in, A/D converter, then
you may download the source code
from the Circuit Cellar ftp site and
experiment with it.
THE TIMER SYSTEM
A real-time system can be pretty
convenient for analyzing the real-time
performance of various tasks per-
formed by the JVM. Some examples
include: calculating the time required
for various numbers of iterations to do
the same job; thread switching time;
and creating a timer that’s supposed to
trigger an event or job the instant it
expires. You can use this timer to cre-
ate a time-triggered environment.
The 68HC11 microcontroller pro-
vides a versatile timing system, giv-
ing a time resolution as low as
500 ns, assuming an 8-MHz crystal
base. There is a free-running 16-bit
counter in the 68HC11 that starts
counting as soon as the processor
comes out of reset. The time that the
counter requires to increment by a
single count can be adjusted, the
minimum of which can be 500 ns.
The maximum can be 8 µs with an
8-MHz crystal base.
For example, if the counter is set
to increment by a single count in a
period of 500 ns, then the time after
which the counter will reach 0xFFFF
will be 65,535 multiplied by 500 ns,
giving a 32.768-ms time period. I pro-
vided examples of this for various
frequencies, which you can down-
load from the Circuit Cellar ftp site.
This counter is a part of the 68HC11
timing system that constitutes the
following registers to provide the
full functionality.
The Timer/Counter register is a
16-bit, read-only register. The con-
tents of this register hold the
prescaled value and can be read at
any instant. The 68HC11 can read
only 1 byte in a single CPU cycle,
which can pose a problem because
the contents of this register regarding
the lower byte will change for the
next CPU cycle.
Listing 2The class file implements basic methods to handle asynchronous events.
class RTasynchEvent extends Thread{
int eventId;
int count;
***************************************************************
The following table will hold the addresses of memory space
where the event occurring will be registered. Note that its a
class table not an object table.
***************************************************************
static int [] eventCountTable =
{0x0010,0x0012,0x0014,0x0016};
public void run(){
while(true){
count = eventCount(eventCountTable[eventId]);
if(count>0){
fire(count);
}
else{
yield(); //If an event isnt registered, move on
to the next.
}
}
***************************************************************
The class constructor enables specific event IDs.
***************************************************************
public RTasynchEvent(int ev_Id){
comm = new CommThread();
eventId = ev_Id;
enableEvent(eventId);
}
***************************************************************
The following method will disable an event, after which JVM
will no longer register and respond to asynchronous events
with this ID.
***************************************************************
public void excludeEvent(){
disableEvent(eventId);
}
//Set the event type (0 to 2)
public void setEventType(int type){
eventType(eventId,type);
}
public void fire(int number){
if(eventId == 0){
for(int x=0;x<number;x++){
//Insert application-specific code to be executed in response
to event 0.
}
}
if(eventId == 1){
for(int x=0;x<number;x++){
//Insert application-specific code to be executed in response
to event 1.
}
}
if(eventId == 2){
for(int x=0;x<number;x++){
//Insert application-specific code to be executed in response
to event 2.
}
}
if(eventId == 3){
for(int x=0;x<number;x++){
//Insert application-specific code to be executed in response
to event 3.
}
}
(Continued)
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Issue 148 November 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
To cope with this, the contents of
the least significant byte are latched
into a buffer as soon as the most sig-
nificant byte is read for the next CPU
cycle. So, the double byte read of this
register returns the 16-bit state of the
counter during the most significant
byte read cycle.
Bit 7 of the Timer Interrupt Flag 2
register holds the flag for the timer
overflow interrupt. This flag is set
whenever the Timer/Counter register
rolls from 0xFFFF to 0x0000.
The Timer Interrupt Mask 2 regis-
ter is used to enable the timer over-
flow interrupt. To enable this inter-
rupt, bit 7 of the TMSK2 register is
set or cleared. If this bit is set, an
interrupt is generated as soon as the
timer overflow flag is set.
The last two bits of this register
can be used to set the prescaled
value for the count period. For
example, clearing these two bits
gives a single count period of 500 ns
and an overflow period of 32.768 ms,
again assuming that there’s an 8-
MHz crystal base.
JAVA IMPLEMENTATION
You may download the code for a
Java implementation for the basic real-
time timing functions from the Circuit
Cellar
ftp site. The
timerSys class
uses the
CPU.java class provided in RTJ
Computing’s hw.mot68hc11 package.
If you download the code, you will
see that the
timerSys class creates
and defines integral methods to fully
implement the real-time functionali-
ties of the 68HC11 platform. The
implementation of the real-time
class and its methods is based on the
free-running counter in the 68HC11
system. The free-running counter is
prescaled by one as the default set-
ting, giving a prescaled count period
of 500 ns and timer overflow period
of 32.768 ms with an 8-MHz crystal
}
***************************************************************
Calling the following method will elevate the priority of this
event over all other events.
***************************************************************
public void setCriticalPriority(){
eventCriticalPriority(eventId);
}
public native void eventCriticalPriority(int ev_Id);
public native void eventType(int ev_Id,int type);
public native void enableEvent(int ev_Id);
public native int eventCount(int table_Id);
public native void disableEvent(int ev_Id);
}
Listing 2Continued
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www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 148 November 2002
19
base. Also, the class uses the first
four bytes of the 68HC11’s internal
RAM, so be careful.
EVENT-TRIGGERED SYSTEMS
In event-triggered systems, you use
interrupts to trigger a particular rou-
tine that will handle asynchronous
events, analyze them, and respond to
them fast enough to be able to influ-
ence the interrupt-requesting environ-
ment in a desired fashion. These
interrupts form the building unit of
what we call the real-time asynchro-
nous event handling systems.
In contrast to what I’ll describe
later (i.e., time-triggered systems),
event-triggered systems carry out all
of their activities in response to rele-
vant events that are external to the
system. These interrupts are not
synchronized to any clock, which is
why they’re suitable for handling
asynchronous events.
The version of a JVM by RTJ
Computing for the 68HC11 doesn’t
provide class or native files to build
such a system and analyze its per-
formance. But you can’t forgo your
real-time analysis without having
resolved this issue. Your system
should be able to handle asynchro-
nous events with some timing con-
straints in order to check that the
JVM is performing in real time.
To write Java support for asynchro-
nous events, you must mask the
68HC11 input capture functions to
serve your purpose. Using these func-
tions, you can write a Java program
for asynchronous event handling.
Because the Java program will require
intensive interaction with low-level
hardware, many of the methods are
written natively.
JAVA CLASS DETAILS
Now, let’s move on and discuss
the attributes of the Java class imple-
mentation. The first point to note is
that the unique events occurring
asynchronously can be detected and
served by four corresponding Java
threads. External asynchronous
events can be registered and served
only if their corresponding Java
event objects have been created by
the running Java application.
Secondly, the Java
event object with ID 0
has the highest priority,
and the event object
with ID 3 has the lowest
priority. However, if an
event object has an ID
above zero, and if at any
time it’s supposed to
handle a critical asyn-
chronous event, its pri-
ority can be elevated
above all event objects.
It’s important to note
that even after the eleva-
tion of an event object’s
priority, it will register
the asynchronous event
at a higher priority than
others but still cannot
serve it a higher priority
basis. This is because
JVM for the 68HC11
does not support priori-
ties for threads.
A third feature of this particular
Java implementation is that it can
register and serve three different types
of external asynchronous events.
These types range from zero to two.
Type 0 defines an external event to be
registered at a rising edge, type 1
defines it to be registered at falling
edge, and type 2 defines it to be regis-
tered at any edge.
To clarify these terms, assume that
you construct a Java event object of
ID 0 and type 0. You send a binary
sequence of 0 to 15 in order. Because
a Java event object is ID 0, it will reg-
ister an event corresponding to the
least significant bit only. Furthermore,
this Java event object is of type 0. It
will register only eight external asyn-
chronous events, because the least
significant bit in a binary sequence of
0–15 has eight rising edges. Take a
look at Listing 2 for the Java imple-
mentation of asynchronous event
handling with the 68HC11.
Figure 3 demonstrates the fourth
notable feature of the Java implemen-
tation. You can assume that all four
Java event objects (of any type) are
enabled. So, for the maximum delays,
all four Java event objects incorporate
an equal amount of external asyn-
chronous events. Furthermore, it
would take 3 ms to serve an external
asynchronous event. Because all four
events are enabled, four corresponding
Java threads will run as well.
A scheduler that’s preemptive in
nature schedules these threads. The
threads have a time span (i.e., peri-
od when the CPU is dedicated to
threads) equal to the 68HC11’s real-
time interrupt (RTI). Assuming an
RTI of 4 ms, each thread will have
only 4 ms to perform its task. A
thread is bound to wait for 12 ms
to complete the next portion of its
remaining task, because there are
four running Java threads.
As you can see in Figure 3, the
Java event object with ID 0 regis-
ters three external events—
t1
Scheduler-triggering (real-time interrupt) latency
t2
t3
Context-switching latency
Execution time for thread
t1
t2
t3
Time quanta for scheduler
Transaction < t3
Figure 4This time scale representation provides a general
idea of the time chunk thats available for a transaction.
4
8
12
16
20
24
28
32
3 ms
15 ms
10 ms
event_0_thread running
event_1_thread running
event_2_thread running
event_3_thread running
event_id_0 registered _1
event_id_0 registered _2
event_id_0 registered _3
event_id_0 served _1
event_id_0 served _2
event_id_0 served _3
Time (ms)
Figure 3The event registering and serving latencies are the result of the
equal priority thread scheduling by the JVM implementation.
20
Issue 148 November 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
ing which the data out from these
sensors can be read and recorded.
Because you know in advance that
the sensors won’t change their data in
less than 1 s, it’s easy to schedule
things. In this case, you can prevent
interrupt-related latencies, saving you
from a considerable overhead of dis-
patch latencies, as was the case for
the event-triggered system.
THREAD SCHEDULING
The JVM version for the 68HC11
that I’m using implements only non-
daemon threads. There can be a
maximum of eight user-level threads.
Furthermore, the JVM for the
68HC11 runs as a stand-alone RTOS,
depicting many-to-one thread models.
There are no priorities among
threads. All threads are of the same
priority and are scheduled by pre-
emptive time-slice scheduling.
Because these threads are of the
same priorities, they are better suit-
ed for a time-triggered system than
for an event-triggered system.
Figure 4 depicts the amount of time
a transaction that’s related to a par-
ticular thread can have. Scheduler
triggering is dependent on a real-
time interrupt. For a masked inter-
rupt, the latency can be as long as
10.5 ms. Context-switching latency
depends on the number of threads
running concurrently. This time can
be a maximum in the case of eight
threads, and a minimum in the case
of one thread.
The execution time for the thread
is the time period during which the
CPU is dedicated to a particular
thread. So, it’s obvious that the
transaction should be less than or
equal to the net execution time for a
particular thread.
A real-time scheduler schedules
threads. This scheduler is triggered by
the RTI. In this simple real-time Java
event_id_0 registered_1, event_id_0
registered_2, and event_id_0 regis-
tered_3—at time instants of 5, 7, and
13 ms. These events are registered
apart from the threads at the native
level, so they will be registered as
soon as they occur. On the other
hand, you can see that the first exter-
nal event (event_id_0 served_1) occurs
at 8 ms, with a latency of zero. Only
3 ms are required to perform the
desired task related to that event.
A second event (event_id_0 served 2)
occurs at 22 ms, with a latency of
12 ms (22-7-3). Similarly, the third
event (event_id_0 served 3) occurs at
23 ms, with a latency of 7 ms (23-
13-3). Note that the third event,
despite being registered late, has a
lesser latency than the second event,
which was registered earlier. This is
because all of the threads in the
68HC11 JVM are scheduled on an
equal-priority basis.
Note that the latencies are reduced
to a minimum by using a yield
method for threads in the Java class
implementation for asynchronous
event handling.
TIME-TRIGGERED SYSTEM
In a time-triggered system, all of
the events that will be triggered are
time-dependent. System implemen-
tations dependent on time require
prior information about the events
that will occur.
Because I’m working with the
68HC11, which has limited accessi-
ble memory, many of the routines
do not have complex calculations.
Thus, it’s possible to allocate them a
time duration, which is the maxi-
mum time for execution. These
deadlines are transaction times.
For example, a system incorporat-
ing 1000 sensors that change their
output every second should have a
transaction time of 1 ms or less, dur-
scheduler, the CPU generates the RTI.
In response to this, the scheduler is
triggered, calling the VMTimeSlice
method from the JVM. This method
is preemptive in nature, and will ded-
icate the CPU to the next usable
thread in the queue. So, you can say
that there is a scheduler that’s sched-
uling the threads at definite periods of
time that are determined by the RTI.
The RTI can be 4, 8, 16, or 32 ms
when you’re working with an 8-MHz
crystal. The RTI’s time can be adjust-
ed by setting or clearing the last two
bits in the pulse accumulator control
register (PACTL) of the 68HC11.
Table 1 summarizes the RTI periods
for various oscillator frequencies.
Note that E equals the crystal fre-
quency divided by four.
If you can set a zero reference
time, then you can accurately deter-
mine which thread is running or will
run for a particular period of time.
For example, if you set the RTI to
occur every 4 ms for a program that
incorporates four threads (i.e., T_1,
T_2, T_3, and T_4), then starting
from a zero reference time after
exactly 12 ms, T_4 will be dedicated
to the CPU, keeping aside the laten-
cies for a moment.
EVENT OCCURRENCES
Now, you can assign any task to a
particular thread that will be per-
formed accurately in a fixed period of
time. For example, to generate a pulse
train of 12 ms, a pulse width of T_4
can be assigned a task to toggle an
I/O pin between logic 0 and 1 with an
RTI time period of 4 ms.
For the system described here to
work correctly, it’s assumed that
there are no other kernel-level
threads, and the only user-level
threads are T_1 , T_2 , T_3 , and T_4.
Figure 5 shows the scheme opted by
the real-time Java thread scheduler.
PRIORITY APPROACH
The thread-scheduling scheme for
handling time-based events has one
obvious drawback. Because all of the
threads are scheduled by a single
RTI, you can’t have different trans-
action times for different events. If
one event or thread requires an RTI
PACTL bits [1:0]
E = 3 MHz
E = 2 MHz
E = 1 MHz
E = x MHz
00
2.731 ms
4.096 ms
8.192 ms
E/2
13
01
5.461 ms
8.192 ms
16.384 ms
E/2
14
10
10.923 ms
16.384 ms
32.768 ms
E/2
15
11
21.845 ms
32.768 ms
65.536 ms
E/2
16
Table 1Note that this real-time interrupt period depends on the PACTL registers last two bits for a particular E
clock frequency.
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 148 November 2002
21
of, say, 4 ms, then all of the
other events and threads are
constrained to have this
period.
To cope with this situa-
tion, I’ll define another
mechanism for time-based
triggering. I call this mecha-
nism the transaction
approach mechanism (TAM),
because it schedules based on
priority. TAM doesn’t depend
on any other processes like
thread, for example.
All events are to be scheduled and
executed at a fixed instance of time,
irrespective of any other event or
process. As soon as the moment for
that particular event arrives, all of the
system’s resources will be dedicated
to that event.
The rate at which these time-
based events will execute is variable;
it can be an integer multiple of the
68HC11’s free-running counter over-
flow period (the minimum of which
is 33 ms). It’s possible to reduce the
minimum time to the counter’s
increment rather than its overflow,
but I did not implement this in my
code. In the latter case, an event can
have a rate as small as 500 ns.
All time-based events are defined
by their IDs. For the 68HC11, you
can have a maximum of four time-
based events, with IDs of zero to
three.
The reference time method is
used to set the moments of which
all priority events will be based.
Transaction times for every event is
independent and will have an inde-
pendent reference time. So,
every event can be scheduled
at a different rate.
As with other scheduling
schemes, events are catego-
rized by their type. An event
can have any type from zero to
two. These types define the
external response made at the
time the event is scheduled to
occur. Type 0 will toggle the
output, type 1 will put a logic 0
at the output, and type 2 will
put a logic 1 at the output in
response to a time-based event. You
may refer to Listing 3 for the Java
implementation of TAM.
SYSTEM GARBAGE COLLECTOR
The newer version of JVM (i.e., Beta
2) supports the collection of unused
objects, or garbage, from the Java heap.
Adding support for the garbage collec-
tion increases the versatility of the Java
VM because it’s not limited to the
static allocation of objects.
You can use the new operator virtu-
ally without restriction. However,
T_1
T_4
T_3
T_2
T_1
T_4
T_4
T_3
T_2
T_1
T_2
T_3
CPU
Real-time interrupt
Real-time interrupt
CPU
Figure 5For the JVM real-time scheduler, threads are scheduled by the
VMTimeSlice method.
have not been reached
are marked white.
Then begins the sweep
phase during which all
of the white objects
are removed.
COLLECTOR
PERFORMANCE
The duration of
garbage collection
depends on the size of the heap,
number of objects created by the
running Java application, and
whether or not the heap compaction
is required. Typically, a 24-KB heap
garbage collection can be completed
in 40 to 250 ms, according to the
specs from RTJ Computing.
Like other garbage collectors in
various JVMs, this collector doesn’t
require your attention. However, it
can be invoked explicitly by the
System.gc( ) method. Or, the
garbage collector can be invoked by
the JVM on the following occasions:
when there isn’t enough memory on
the heap for the new object; when
the strings table is full; when the
references table is full; or if there is
not enough room on the heap for a
new method frame.
ALL IN ALL
Not all of the analysis could be per-
formed because of the memory limita-
tions and restrictions imposed by the
implementation of the JVM. On the
whole, I believe that Java is suited for
real-time applications that do not
require strict timing constraints and
in which a slight relaxation of
response can be tolerated.
The experiments that I performed
regarding the implementations that
are included in this research provided
a brighter picture of real-time Java on
the time-triggered side. My experience
in handling events that were known
in advance was more promising than
those events that occurred asynchro-
nously. One such experiment included
sending binary pulses at port A of the
68HC11 at a known rate. I should note
that fully comparing the time-triggered
system to the event-triggered system
requires more resources than this JVM
and 68HC11 can provide.
22
Issue 148 November 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
because of the limited memory
resources, the allocation of large
objects or having a large number of
active objects may cause Java VM to
run out of resources. As a conse-
quence, an out-of-memory exception
can be generated. The allocation of a
memory heap of a Java application
depends on the amount of memory
available in the system. This range
can be adjusted by two parameters in
the native linker file.
As you can see in Figure 6, the
garbage collector in the JVM for the
68HC11 uses a three-color technique
to mark objects on a heap: white
objects are garbage that can be reused;
black objects are active arrays and
system classes; and gray objects are
all other class objects (including
arrays of objects) that require revisit-
ing by the GC because they may con-
tain references to other objects.
Garbage collection is performed in
two phases, mark phase and sweep
phase. During the mark phase, all of
the objects are traversed by the graph
reachability algorithm depth-first
search (DFS). At the start of the tra-
versal, all of the objects are marked
white. As the traversal proceeds
along a branch, the objects are
changed from white to gray. Marking
an object gray means that it has been
reached by a branch, but there is still
an object down the branch that has
not been reached.
After the branch node has been
reached, the object at the terminal is
marked black. Then, the traversal
starts backwards along the same
branch. When all of the objects below
that object have been marked black,
that object is marked black too.
At the end of this mark phase, all
of the objects that are reachable have
been marked black; the objects that
Shahzad Umar recently graduated
from the University of Engineering
and Technology in Lahore, Pakistan.
Currently, he is a teaching assistant
at the university. Shahzad’s interests
include embedded systems, real-time
operating systems, and digital com-
munication systems. You may reach
him at swetword@yahoo.com.
To download the code, go to
ftp.circuitcellar.com/pub/Circuit_
Cellar/2002/148/.
SOURCES
68HC11 Microprocessor
Motorola, Inc.
(847) 576-5000
simpleRTJ, ClassLinker program
RTJ Computing
www.rtjcom.com
RESOURCES
G. Bollella, “Real-Time Java
Architecture and Prototyping,”
Embedded Systems Conference,
1999.
G. Bollella and J. Gosling, “Real-
Time Specifications for Java,”
IEEE Computer Conference, June
2000.
D. Mulchandani, “Java for
Embedded Systems,” Dr. Dobb’s
Journal,
February 2000.
K. Nelson, “Embedded Real-Time
Development in the Java
Language,” NewMonics, Inc.
S. Ortiz, Jr., “The Battle Over
Real-Time Java,” IEEE Computer,
June 1999.
RTJ Computing, JVM for 68HC11
and other related files, www.rtj-
com.com/6811/download/down-
load.html.
Gray
Black
White
Objects require revisiting by GC
Active arrays and system classes
Garbage
Figure 6The garbage collector classifies these objects. The JVMs
garbage collector uses this color scheme during garbage collection.
All of the Java source code avail-
able on the Circuit Cellar ftp site is
fully functional. Source code for the
native methods is not included, but
can be requested for experimental
and research purposes.
I
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The PSoC Range Finder is a simple, inexpensive ultrasonic dis-
tance meter that requires only a PSoC device, two 40-kHz ultra-
sonic transducers, two resistors, and two capacitors. Typical
applications include positioning for robotics, generic distance
measurement, and liquid-level measurement without contact.
The main program first sets up the analog and digital blocks,
and then tests for JP1 to determine whether to initialize Normal
or Calibration mode. In the former, the software continuously
runs the transmitted ultrasonic burst (ping) and, after a period of
time, waits for a returned ultrasonic signal (pong). The time
between the start of a transmitted burst and the start of a
received burst is proportional to the distance between the PSoC Range Finder and an obstacle. Polling the com-
parator bus register, you can measure this time and store it in a RAM location. Finally, the range value is written
to the LCD (if present) and sent to the serial interface. Then, the PWM duty cycle is set to a value proportional to
the distance between the PSoC Range Finder and the obstacle.
In Calibration mode, the software is similar to Normal mode, but the measured value is compared to a constant
value (50). The resultant offset is stored in EEPROM and added to the range measured in Normal mode.
TimeBase_int is the interrupt subroutine for the time base 8-bit counter. When Timer 1 is greater than the pro-
grammed delay (a delay is necessary to prevent false echoes caused by the lateral receiving of a transmitted
40-kHz burst), the software tests the logic value of the comparator. If a pong is received, Timer 1 is stored in the
RAM location “range” and the time base interrupt is disabled, so the value stored in the range location represents
the measured distance. If the comparator output is equal to zero, then a PGA_1 gain is dynamically incremented
in 16 steps to modify the corresponding gain register, so the far echoes are amplified.
Fabio Piana
Italy
fabiopia@tiscali.it
The task was grueling, but our intrepid judges have chosen the winners of the Cypress MicroSystems
PSoC Design Challenge 2002. Entries poured in from every part of the United States and the rest of the
world—Italy, India, Ukraine, Luxembourg, Singapore, and more. With so many intriguing entries to
review, the competition was fierce. We’re sure you will be just as impressed as we were with the top
entries. Awards were given for First, Second, and Third Prize as well as 10 Honorable Mention awards.
Recognition was also awarded to the entrants whose projects displayed the effective dynamic reconfigu-
ration, optimum use of the components, and most novel design. Here, we’ve included photos of the top
three prize-winning projects along with brief descriptions of every winning entry.
1st Place — PSoC Range Finder
Brought to you by:
The Cypress logo mark is a registered trademark of Cypress Semiconductor and Cypress MicroSystems, PSoC, and Programmable System-on-Chip are trademarks of Cypress Microsystems Inc. The
Circuit Cellar name is a registered trademark of Circuit Cellar Inc.
Bonus Award: Effective Dynamic
Reconfiguration
OnTV-21 is a small and relatively simple
device that allows you to stay in touch
with other people while you’re watching
television. The application is based on the
PSoC CY8C26443 microcontroller. OnTV-
21 includes a wireless link to a PC that
can collect information about incoming e-
mails and chat room requests. OnTV-21 is
coupled to a telephone line so that it can
collect caller ID information. The device
displays the information it receives on the
TV using the closed-captioned decoder.
OnTV-21 gets its name from the fact that
the closed-captioned information is broadcast on the twenty-first line of the video frame.
OnTV-21 is inserted in the video link between a TV receiver (tuner) and a TV that has been set to accept an
external video input. The information collected by OnTV-21 is displayed seamlessly using the closed-captioned
decoder on modern televisions. Despite the high bit rate (503.5 KHz) of the closed-captioned information, OnTV-
21 generates the closed-captioned bitstream in the software. To stay in touch, the TV has to be set to permanent-
ly decode the closed-captioned information. OnTV-21 automatically strips the closed-captioned information gener-
ated by the network or cable operator.
OnTV-21 serves as the analog interface to the telephone line and performs caller ID demodulation. Additionally,
OnTV-21 maintains synchronization with incoming video and filters unwanted closed-captioned data.
Bernard Debbasch
U.S.
bernard.debbasch@mail.com
2nd Place — OnTV-21
The full projects and source code
The Vector-SoC is a low-cost RF vectorial network ana-
lyzer (VNA) built around a CY8C26443 chip. The testing
instrument is designed to apply a frequency ramp to a
device being tested, measure the signal at the output of
the device, and plot the corresponding gain and phase
transfer curves over frequency. The Vector-SoC accurate-
ly measures and displays frequency responses as narrow
as a SAW filter. The device gives an accurate and stable
display thanks to the automatic calibration routines.
Key specifications of the Vector-SoC include: a PC-based
instrument with a 57.6-Kbps serial connection; Windows-
based user interface; and real-time refresh of all curves
and measurements (2.5 frames per second).
The Vector-SoC offers full coverage from 0 to more than 1 GHz in one band with 50-kHz resolution. It achieves a
gain/loss measurement from 5 to –35 dB with 0.25-dB resolution (up to –45 dB from 0 to 300 MHz). In addition,
the phase measurement is from –90°C to 90°C with three degrees of resolution. The Vector-SoC includes two
VCOs. A receiver module gets the reference signal from the generator as well as the signal that went through the
device being tested. The third module is a simple prescaler used to measure the actual frequency through the
PSoC. Lastly, the main module, which is built around the PSoC chip, takes care of everything else, closing the
loop between the generator, receiver, prescaler, and host PC.
Robert Lacoste
France
robert_lacoste@yahoo.fr
3rd Place — Vector-SoC
A 1-GHz Vectorial Network Analyzer
Precision Digital Controller Using the PSoC CY8C26443-24PI
Microcontroller
The precision digital controller is designed for fully automatic microcontroller-controlled
reaction vessels. With high mass-transfer efficiency, this controller is used for developing and
manufacturing fine chemicals and bioengineered products as well as drugs and their inter-
mediates. Such applications impose stringent requirements on temperature and pH mainte-
nance, foaming, and oxygen content over extended periods of time (i.e., exceeding
48 hours). Such a facility would help research labs and pharmaceuticals to define applica-
tion-specific control formats for multi-loop and cascade-control configurations.
The heart of the system is the CY8C26443-24PI. The ADC, PWM, PGA, and timer blocks
of the microcontroller were configured to meet the application's requirements. An LCD panel
is connected to port 1 to display the values of the parameters dynamically. Also, an audio
buzzer is connected to port 2 to warn about parameter values that exceed the range. A timer
module counts the on time.
H.N. Naveen and S. G. Sriharsha
India
navmys@lycos.com, sriharshasg@yahoo.co.in
Intelligent Light Effects Controller for Entertainment Systems
Bonus Award: Most Effective Use of Internal Hardware Integration
The light effects controller creates visual effects that can be used for various applications,
including concerts, discotheques, variety shows, and presentations. As opposed to prepro-
grammed or manually/sound-controlled lighting systems, a novel approach for the generation
of visual effects is proposed. The participants' movements are used to create visual effects in
a developed system. The Doppler effect on ultrasound frequency is used for obtaining infor-
mation about participants’ movements. The controller performs Doppler frequency spectrum
analysis to determine the participants’ speed and rhythm of movement, and then creates cor-
responding visual effects.
For data exchange and remote control, the full galvanic isolated RS-485 interface under
DMX protocol is implemented. This interface type is commonly used for controlling various
lighting systems in entertainment, concert, and theater systems.
Honorable Mention
The controller can be used easily to modernize existing lighting systems, because the sev-
eral most popular load types are supported as well. The device can be controlled remotely via
a standard lighting system RS-485 interface or can serve as the master for controlling existing
lighting equipment, which allows a rapid retrofit of existing systems with minimal cost and time.
Victor Kremin
Ukraine
vkremin@polynet.lviv.ua
LCR Meter
The LCR Meter measures the characteristics of a passive component: capacitance,
inductance, resistance, quality factor, dissipation factor, and phase angle of a component's
impedance. The resistance, capacitance or inductance, and one selectable third result are
displayed simultaneously on a large, low-cost LCD. The LCR Meter can display the resistive
and reactive parts of either a series or parallel equivalent circuit, as well. With a rotary
encoder and small keyboard, the LCR Meter provides an simple user interface.
This project features a resistance range from 100.0 m
Ω (0.1-mΩ resolution) to 1.000 MΩ.
The capacitance ranges from 100.0 pF (0.1-pF resolution) to 10.00 mF. And, the inductance
range is from 10.00 µH (10-nH resolution) to 10.00 mH. In non-exhaustive accuracy tests,
the LCR Meter recorded errors of only 0.07% at 10 nF, 0.16% at 10 k
Ω, and 2.4% at 100 uH.
Stimulus frequency ranges from 50 Hz to 10 kHz are supported in 195 user-selectable, crys-
tal-controlled discrete steps. Stimulus AC amplitude is selectable from three different values:
250 mV, 500 mV, and 1 V. The stimulus DC bias can be set internally to 2 V or externally to
up to 50 V. A four-wire measurement interface compensates for test setup contact resistance.
Laurent Lamesch
Luxembourg
lla@iee.lu
Simple Wireless Bluetooth Mobile Phone Headset
The Simple Wireless Bluetooth Mobile Phone Headset was built using a Bluetooth mod-
ule and PSoC CY8C26443 microcontroller. Few other components were needed because of
the PSoC microcontroller’s beneficial internal peripherals. The other components used
include: a 3.3-V power supply; 16-V, 47-µF electrolytic capacitor; two 300-
Ω resistors; two
SPST push-button switches; and two LEDs.
The device consists of two units. One unit is worn by the user as the headset; the other
unit is connected to the mobile phone via its handset interface connections. The Bluetooth
module provides the wireless interface between the mobile phone and headset. The
CY8C26443 controls this module via a UART interface running at 57.6 kbps, 8 bits, 1 stop
bit, and no parity. Another interface, from the Bluetooth module to the CY8C26443, enables
voice data to be transmitted.
Steven Wong Kai Juan
Singapore
askjwong@ntu.edu.sg
Low-Power “Contactless” Tag Reader
Like similar radio frequency identification devices, the Low-Power “Contactless” Tag
Reader is useful for various electronics projects such as access control, object identification,
and automotive applications. The 125-kHz reader is designed around the PSoC CY8C26233.
The CY8C26233 has sufficient memory and processing power to be programmed in C, thus
making it easy to upgrade and adapt for future extensions.
A built-in boost converter enables an interesting feature: the reader can function at volt-
ages as low as 2 V. The detection mechanism reduces the mean power consumption to low
levels and makes this reader design a good choice for portable applications.
No external components other than the input stage (using only passive parts) are
required. The analog conditioning stage can be reconfigured and the firmware repro-
grammed to adjust to a particular encoding scheme. The reader features 3 to 5 KB of flash
memory and 25 bytes of RAM. It averages power consumption at rates of: 5 V at 50 µA (best
sensitivity); 3.5 V at 20 µA; 3.2 V at 120 µA with the internal boost converter; and 2.2 V at
220 µA with the internal boost converter.
Chanh Ho Minh
France
chanh@itronic.com
PSoC-Based Audio Analyzer
The PSoC-Based Audio Analyzer consists of two major functional blocks: a white noise gen-
erator to act as a broadband stimulus, and an eight-band spectral analyzer to measure the fre-
quency-specific system response and display the results. The analyzer is built around the
PSoC CY8C26443. White noise is generated by clocking a 24-bit, pseudo-random sequence
generator at 40 kHz, and then moving the lower six bits to the input of a DAC. This produces a
randomly fluctuating analog output with spectral components up to 20 kHz and a repetition rate
of 7 min. An FFT of the data shows a frequency spectrum with a flat response of 20 kHz.
A stereo patch cable is run between the RCA jacks on the side of the analyzer to an
appropriate input on the rear of the amplifier being tested. Then, the stereo is turned on and
the input is selected. While standing in the desired listening location, the user turns on the
analyzer and selects the stereo channel to test. As white noise emits from the speaker, the
user adjusts the equalizer settings on the amplifier until a flat response is observed on the
display.
Jerry Wasinger
U.S.
webmaster@web-ee.com
Audiometer
Designed for doctors in India who must travel to rural communities, the Audiometer Extreme
is portable and rugged. The integrated analog and digital blocks of the PSoC microcontroller
enable the use of fewer support chips, thus reducing the size and cost of the audiometer.
Key features of the Audiometer Extreme include: a digitally generated sine wave at fre-
quencies up to 8 kHz; noise generated using on-chip PRBS modules; and both narrowband
and wide-band noise available for masking. The narrowband noise is generated from wide-
band noise using on-chip band-pass filter modules. A 2 × 16 LCD displays information in a
clear and logical manner; the LCD contract can be adjusted digitally. The audiometer also
features an on-chip ADC that generates a bar graph display on the LCD when the selected
input is speech. An on-chip DAC generates the control voltage for the voltage-controlled
amplifier. The DAC voltage ramps up and down with programmable slopes so that the inter-
ruption of tone or speech is smooth.
Amit Davjekar
India
amit_dav@satyam.net.in
Sonoran: An Ultrasonic Cave-Mapping Platform
As a device that can accurately measure cave and tunnel dimensions, Sonoran is ideal
for industrial applications in mining, drilling, and drainage, as well as in geological studies
and for military reconnaissance. The small, untethered, self-contained nature of the platform
allows the device to travel farther into the subterranean realm than current GPS-based sys-
tems allow and where the environment is too hazardous for humans.
Sonoran's ultrasonic cave-mapping platform combines an ultrasonic ranging system, a
scanning solar assembly, and a six-degrees-of-freedom inertial navigation system (INS).
Sonoran takes precise measurements of cave and tunnel dimensions as the vehicle upon
which it is mounted navigates the cave or tunnel. The INS is capable of measuring speeds
up to 45 mph, with rotational rates up to 300° per second. The ultrasonic ranging system can
probe up to 35
′ with 1% error.
The drop-in flexibility of the PSoC CY8C26443 microcontroller allows for advanced appli-
cations like: coupling the INS with GPS, and using the former in a gap-filling mode to interpo-
late between two points; quickly adding gas, humidity, temperature, and PIR sensors to cre-
ate a complete survey of the target environment; and configuring the platform to run as a
slave, and using the ultrasonic ranging data to continuously recalibrate the navigation system.
John Neumann
U.S.
neumann@post.harvard.edu
Remote Human Health Monitoring System
The Remote Human Health Monitoring System monitors the organism state of diseased
individuals, persons who are located in dangerous environments (e.g., firemen and rescuers),
sportsmen during training, and automobile/train drivers. The portable, small, autonomous sys-
tem can be used for on-line and off-line human organism state monitoring. Electrocardiogram
sensors, two-way light pulsometer sensors, and accelerometers all are supported. The sensor
combination used allows analysis of heart rate, respiratory activity, blood oxygen saturation
level, and individual movement activity. The sensor data can be used to predict various dan-
gerous states (e.g., detect loss of consciousness or a heart infarct).
The monitor system consists of two main units: the portable, autonomous unit, which is
carried by an individual, and data communication unit, which receives the data collected and
transmits it to the PC for analysis. The data communication unit also sends the control com-
mands to the monitor. A wireless data link enables a central monitoring center. The bidirec-
tional data link option allows the user to send commands or other information. The monitor
also can collect sensor data from internal nonvolatile data memory and transmit it to a PC for
processing. This operation mode is intended for the diagnosis of various cardiac diseases or
collection of data during athletic training.
Victor Kremin
Ukraine
vkremin@polynet.lviv.ua
Neurochip: Using Configurable Microelectronics to Study Neurobiology
and Animal Behavior
Bonus Award: Most Novel Application
Biological neural networks form intricate configurations that sense and modulate an
organism's thoughts and behavior. To understand these networks, neurobiologists often use
stationary (not portable) instrumentation, which skews the quality of the information gathered.
The Neurochip was designed to gather more accurate data by placing miniaturized instru-
mentation onto animals, and then studying their natural neurobiological behavior (i.e., collect
neuromuscular data while observing behavior and even provide external stimuli).
The Neurochip is small and lightweight enough to be carried by a moth. Using a high-
speed video to capture the intricate maneuvers of moth flight while the moth hovers on a
flower or flies in a wind tunnel, scientists can draw a correlation between video and biological
signals, and perhaps answer some of the long unanswered questions of insect flight and
intelligence. Furthermore, by adding controlled motion to the flower and disturbances to wind
currents, you can begin to understand how biological control systems adapt to changing
environmental stimuli.
An 8-bit PSoC microcontroller running at 3 MHz is the core of the Neurochip. The PSoC
device enables the Neurochip to acquire data from two sets of muscles or neurons, and then
digitize and compress the data. The Neurochip then stores the data on an Atmel serial flash
memory device.
Jaideep Mavoori, Mark Enstrom, Mike Tu, Chris Diorio, and Tom Daniel
U.S.
jaideep@washington.edu
Honorable Mention
The full projects and source code
28
Issue 148 November 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
dders are a part
of the critical path
in virtually all practi-
cal digital systems,
because every arithmetic operation
requires one. Thus, the speed and area
efficiency of adders is important when
you’re designing a circuit. A fairly large
body of literature exists for adder design
in today’s standard cell and custom IC
technologies, but little success has been
reported in the realm of the increasing-
ly important FPGA technologies.
The history of adder optimization
long predates electronic computers. In
his 1851 treatise on calculating engines,
Charles Babbage wrote about the “four
cases of obstacles presenting the appear-
ance of impossibilities” that he encoun-
tered as he designed the analytical
engine, which was the mechanical
prototype for modern computers. [1]
The first of these difficulties, which
he encountered in an early stage of the
design process, was concerned with
the efficiency of the addition process.
So, Babbage went on to provide a prac-
tical solution that can be adapted for
use in VLSI technology, including
today’s FPGA technology.
In this article, Babbage’s solution,
now called carry-skip or carry-bypass
adders, will be explained, and we’ll
show you how we adapted them to be
used for FPGAs. We focused on two
families of FPGAs for this project, the
Atmel AT40K and Xilinx Virtex.
ADDERS FOR ATMEL
For the Atmel AT40K FPGAs, we
designed a 16- and 32-bit adder (see
Figure 1). The former of the two is
approximately 23.5% faster than its
ripple counterpart and 37% larger.
The latter is 34% faster than its ripple
counterpart, while using only 28%
more cells. On the contrary, a 16-bit
carry-select adder automatically gen-
erated by Atmel’s IDS is more than
three times as large as the ripple adder
and sometimes operates more slowly
than ripple adders in practice.
Unlike Atmel’s IDS carry-select
adders, our carry-skip adders don’t
duplicate ripple chains for any bit posi-
tion. Instead, our adders divide the
adder’s bit positions into groups. In
addition, they inexpensively determine
whether or not the carry into a group
will be propagated through to the carry
out of that group. If so, that group is
said to be “skipped.” The carry out of a
skipped group of bits can be determined
with a multiplexer without having to
wait for the carry in to ripple slowly
through the bit positions of that group.
In our 16-bit adder, the 16 bit posi-
tions are divided into three blocks of
sizes of 5, 6, and 5. Our 32-bit adder is
divided into three blocks of sizes 10,
12, and 10. In both adders, the most
and least significant blocks are just
ordinary ripple adder blocks. The mid-
dle block, however, is a special block
with a skip mechanism. No carry sig-
nal ripples slowly all the way through
from the least significant bit to the
most significant bit, making the
worst-case delay much better than
that of the ripple adder.
ADDERS FOR XILINX
Now we’ll describe the adders on
Xilinx FPGAs. Xilinx FPGAs present
the circuit design community with a
difficult challenge. The Xilinx XC4000
and Virtex families use a fast, gate-
based, ripple-carry circuit instead of the
conventional, look-up table-based cir-
cuitry. Additionally, specialized ultra-
fast routing resources exist that favor
Efficient, Practical
Adders for FPGAs
a
In the 1800s, Charles
Babbage developed
calculating engines
that made addition
more efficient. Today,
carry-skip adders are
used in many digital
systems. Recently, a
group of engineers
took the technology a
step further by design-
ing efficient carry-skip
adders for FPGAs.
Vitit Kantabutra, Ph.D.,
Pasquale Corsonello,
Stefania Perri, Ph.D., and
Maria Antonia Iachino
FEATURE
ARTICLE
block is equal to one, then the carry out
of the block is also one. If a carry into
the middle block is equal to zero, then
the carry out is also zero. We call this
property of a bit block the skip property.
COMPUTE THE SKIP
The skip property of a bit block is
easy to compute, because it’s the AND
of the XORs of each bit position’s two
operands. The circuit in Figure 2 com-
putes the DO_SKIP function, which is a
Boolean flag indicating that the middle
contains the skip property.
USE THE DO_SKIP
Take another look at Figure 1. Note
that the DO_SKIP signal can be used
as an input to a multiplexer select line
to choose the carry into the most sig-
nificant block, as follows:
It’s important to recognize
that for custom and standard
cell technologies, we would
normally make the carry
into each position in the
middle block equal to the
carry into the block, provid-
ed DO_SKIP is equal to one.
However, this would require
a multiplexer for selecting
the carry into each bit,
which is inefficient in typi-
IN
OUT
OUT
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 148 November 2002
29
the ripple adder over all other forms of
adders. Even though these design choic-
es are a boon for ripple adders, it makes
it nearly impossible to design a speed-
up mechanism for adders.
However, it’s been proven that you
can speed up wide adders in the Virtex
and related products without sacrificing
too much space. [2] Such wide adders
can be useful in applications such as
cryptographic systems, for which FPGA
technology has been shown to be a
promising means of implementation. [3,
4] Specifically, we’ll describe how a
128-bit carry-skip adder can be realized
on a Virtex chip that shows a gain in
speed over a ripple adder of up to 47%
while requiring only 28% more area.
CARRY-SKIP ADDERS
Both the carry-skip adder and carry-
look-ahead adder stem from the ideas
posited by Charles Babbage in
Exposition of 1851
. If a block of con-
tiguous decimal digit positions in an
adder has the property that
in each position the two
operand digits add up to
nine, then the carry into
each position within the
block, as well as the carry
out of the most significant
digit of the block, will be
the same as the carry into
the block. Conversely, if
this condition is not met,
then the carry output of the
block is independent of the carry
input. And the carry into each position
within the block is also independent of
the block carry input. The following
depicts the main principle behind
Babbage’s fast carry mechanism:
What does this mean in modern
terms? In a binary adder, suppose you
have a 16-bit adder and you partition
the bit positions into three blocks:
These bit blocks are in a modern carry-
skip adder (i.e., our 16-bit adder). Note
that the middle block has the following
property: In each individual position,
the two operand bits add up to one.
Therefore, if a carry into the middle
01010 101011 10101
01101
010100 11011
+
C
OUT
= C
IN
C
OUT
C
IN
23423523 5213426 35367435
23636345 4786573 74674645
+
L9
PAD
P[210] SUM_OUTER[15:0]
P[210]
P[210]
OUT
SUM[15:0]
L11
OPAD
C_OUT_OUTER
C_OUT
C_OUT
0
+ –
B[4:0]
A[4:0]
C_IN
SUM[4:0]
ADD_SUB
SUM[15:11]
RIPPLE_MS_BLOCK
DO_SKIP
SKIP
A[6:0]
B[6:0]
B[15:11]
A[15:11]
µ2_1 D0
D1
D2
ADD_SUB
ADD_SUB
RIPPLE_MIDDLE BLOCK
C_IN_OUTER
IBUF
IPAD
C_IN
RIPPLE_LS_BLOCK
SUM[4:0]
SUM[10:5]
MUX
SKIPCCT
+
+
B[10:5]
A[10:5]
B[10:5]
A[10:5]
B[4:0]
A[4:0]
A[5:0]
B[5:0]
C_IN
+
+
A[5:0]
B[5:0]
C_OUT
C_OUT
SUM[5:0]
SUM[5:0]
A[15:0]
B[15:0]
A_OUTER[15:0]
B_OUTER[15:0]
L8
L7
PAD
PAD
[210]
P[210]
[210]
P[210]
P[210]
P[210]
L5
L6
IN
IN
C_IN
Figure 1—
The 16-bit carry-skip adder for the Atmel AT40K FPGA chip includes three ripple adder blocks, but the middle block has additional circuitry. This circuitry is called
the “skip mechanism,” and its function is to prevent the carry signal from rippling slowly all the way through the block.
B[5:0]
A[5:0]
A0
A1
A2
A3
A4
A5
B0
B1
B2
B3
B4
B5
X0R2
X0R2
X0R2
X0R2
X0R2
X0R2
ANDA0 ANDA1 ANDA2 ANDA3 ANDA4 ANDA5
L12
A[5:0]
0
DO_SKIP
AND
ANDA[5:0]
Figure 2—
A circuit detects whether or not the middle block can be skipped. If the
block can be skipped, then a multiplexer can be used to select the block carry-out sig-
nal. This circuit is small in comparison to the ripple adder in the middle block.
16-BIT CARRY-SKIP
As you can see in Figure 1, the cir-
cuit consists of five modules, namely
two 5-bit ripple cells, one 6-bit ripple
cell, one skip circuit for the 6-bit mid-
dle block, and one two-to-one multi-
plexer. You may download the layouts
for our 16-bit carry-skip adder (on an
AT40K) and 16-bit carry-select adder
(generated by Atmel’s IDS) from the
Circuit Cellar
ftp site.
Note that the skip circuit could have
been one cell shorter, but we stretched
it out to shorten some wiring. You can
30
Issue 148 November 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
cal FPGA architecture, including the
AT40K. Thus, instead we let the carry
ripple through the middle block.
However, the rippling always ends
there, rather than propagating into the
most significant block, because the
most significant block gets its carry in
much quicker through a multiplexer.
ATMEL IMPLEMENTATION
Let’s take a look at the AT40K logic
cell in Figure 3 before discussing the
adders. At the heart of the cell, you’ll
find two look-up tables (LUTs), which
are memory cells. The AT40K cell is
smaller than those of other FPGAs,
yet versatile enough to be useful.
The LUTs can be configured in sever-
al different ways (or modes). If you’re
interested in reviewing some of the
AT40K cell modes, you may download
descriptions of three modes—Synthesis
mode, Arithmetic mode, and Tri-
state/Mux mode—from the Circuit
Cellar
ftp site. More modes exist, but
these are the modes required by our
adders. Note that inter-cell connections
are not shown on the ftp site, but they
are not a problem for our adders.
compare this to the much larger layout
of the slower 16-bit carry-select adder
generated by the Atmel IDS.
TIMING
Timing was performed for the
AT40K40 at a speed level of –2. The
worst-case readings were taken with
the timing analyzer that comes with
the Atmel IDS. There were a few con-
tenders for the worst-case times. The
first was the path from the least sig-
nificant bit (either the operands or
C
IN
; there isn’t much difference
between the two) rippling through the
least significant block, and then rip-
pling through the middle block. The
worst case we found was 17.29 ns.
When the middle block is skipped,
there are two possible contenders for
the critical delay. One of the con-
tenders is from setting up the mux
that selects the carry into the most
significant block. This path is the sum
of the longest delay of the skip circuit,
the mux delay (select to output), and
the ripple delay of the most significant
block. This delay is 16.18 ns in the
worst case. The other contender is the
carry delay itself (i.e., in case the mid-
dle block is skipped), which is 19.5 ns.
Clearly, the latter case gave the
longest delay (i.e., 19.5 ns for our carry-
skip adder). Thus, this is the worst-case
delay for the adder. Of course, this is
measured without load, but the meas-
urement can be compared honestly
with the same type of measurement
for other adders with no load. Using
this kind of measurement, the carry-
select adder generated by Atmel IDS
has a worst-case delay of 22.3 ns, but
it could be worse in practice.
1 NW NE SE SW
1
1
N
E S W
X
W
Y
8 × 1 LUT
OUT
8 × 1 LUT
0
1
1 0
Z
D
Q
< Clock
*RESET
SET
NW NE SE SW
N
E
S
W
X
Y
OUT
1
FB
Z
X
W
Y
X
X
X
X
X
X
X
X
X
X
V1
H1
V2
V3
V4
V5
H2
H3
H4
H5
X
X
X
X
X
1 OE
H
OE
V
L
Pass gates
X = Diagonal direct connection or bus
Y = Orthogonal direct connection or bus
W = Bus connection
Z = Bus connection
FB = Internal feedback
Figure 3—
The Atmel logic cell has two small look-up tables (LUTs), a few multiplexers, and several other compo-
nents. Unlike Xilinx and Lucent FPGAs, Atmel opted for a clean and simple design that usually handles only one
bit position at a time in a multi-bit arithmetic operation.
a(k-1:0) b(k-1:0)
c
IN
c
OUT
s(k-1:0)
a(k-1:0) b(k-1:0)
c
IN
c
OUT
s(k-1:0)
a(k-1:0) b(k-1:0)
s(k-1:0)
a(k-1:0) b(k-1:0)
Bp
a(2k-1:k) b(2k-1:k)
a(k-1:0) b(k-1:0)
c
IN
c
OUT
s(k-1:0)
a(k - 1:0) b(k-1:0)
c
IN
c
OUT
s(k- 1:0)
a(k-1:0) b(k-1:0)
Bp
m-2
c
OUT
a(2k-1:k) b(2k-1:k)
s(2k -1:k)
Bp
1
Bp
c
IN
Figure 4—
Take a look at the top-level architecture of the proposed carry-skip adders on the Xilinx Virtex architecture.
HC08 Q FAMILY OF 8-BIT MICROCONTROLLERS
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Office.
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or
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names
are
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Inc.
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Issue 148 November 2002
CIRCUIT CELLAR
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32-BIT CARRY-SKIP
You may download the
layout for our 32-bit carry-
skip adder from the Circuit
Cellar
ftp site. The only part
that was cut off consists of
eight ripple cells to the
right. The worst-case delay
of this at a speed level of –2
is 35.5 ns, which represents a
34% improvement when
compared to the ripple adder
delay of 53.77 ns.
XILINX IMPLEMENTATION
It’s extremely challenging
to design an adder (other than a ripple
adder) for many Xilinx architectures.
Is there a reason? Yes. Many Xilinx
architectures, such as Virtex, were
optimized for ripple adders to the
extent that any significant speed
improvement was often thought to be
next to impossible. [5]
This ripple optimization is the
result of two factors. First, Xilinx’s
fast carry propagation circuit is based
on gates rather than a look-up table,
and the fastest routing is made avail-
able to the carry ripple circuitry pro-
vided the bit positions in the adder
follow a certain topology. However,
sometimes there’s a need to improve
adder speed. Optimized they may be,
but ripple adders are always ripple
adders, and as such they’re not
always speedy enough for some mod-
ern applications (e.g., cryptography).
In fact, wide adders are usually
required for cases like this.
A group of slow intercon-
nections is inevitably intro-
duced in the carry propaga-
tion path when such an
adder is realized using Virtex
chips. [5] Because the delay
that results from these slow
nets could be greater than
that of the logic of the entire
adder, sudden performance
degradation occurs.
We will now present a way
to achieve an inexpensive but
effective speed improvement
in wide adders (i.e., 96 bits
and up). Our method allows
the delay of carry propagation to be
reduced by means of bypass elements,
which effectively eliminate slow nets
out of the critical path. The scheme
presented here is suitable not only for
Virtex chips, but also for related Xilinx
architectures such as the XC4000X,
Spartan, Spartan XL, and Virtex II.
THE PROPOSAL
Figures 4 and 5 reveal the architec-
ture of the proposed carry-skip adders
a0
b0
a1
b1
P(0)(1)
0
1
0
1
MUXCY
a2
b2
a3
b3
P(2)(3)
0
0
1
MUXCY
ak-2
bk-2
ak-1
bk-1
P(k-2)(k-1)
0
0
1
MUXCY
Bp
I3
I2
I1
I0
FMAP
0
a0
b0
a1
b1
P(0)(1)
I3
I2
I1
I0
FMAP
0
a2
b2
a3
b3
P(2)(3)
I3
I2
I1
I0
FMAP
0
ak-2
bk-2
ak-1
bk-1
P(k-2)(k-1)
Figure 5—
This is the bypass or carry-skip logic for the proposed Xilinx adder.
Visit us on the web www.jkmicro.com
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CIRCUIT CELLAR
®
Issue 148 November 2002
35
on the Xilinx Virtex. Figure 4 depicts
the top-level architecture, in which
each block of k bits represents a col-
umn of k/2 slices. The bypass (carry-
skip) action takes place when a carry
is propagated by the least significant
to the most significant bit position of
a block, depending on the logic value
of the signal’s Bp
i
(i = 1, … , m – 2).
The latter are obtained by means of
the circuit depicted in Figure 5. In
order to assure that the signal’s Bp
i
is
valid before the incoming carry
arrives, the circuit is realized using
the fast logic and routing resource
available in CLBs.
The Xilinx Virtex architecture pres-
ents another noteworthy challenge.
Because of a limitation in the routing
resources, the propagate signals for
the skipped blocks must be repeated.
To see why, examine the Virtex slice
structure shown in Figure 6.
At first, you might expect that the
propagated signals internally computed
in the second k-bit block could be used
to form the signal’s Bp
1
. However, by
examining the slice depicted in Figure 6,
it should be clear that the propagated
signals (i.e., the output of the LUTs)
could be made available only on the y
and x output lines of the slice through
the multiplexing elements M1 and M2.
Because those output lines are
already used to lead out the sum bits
obtained by the XORCY gates, signals
from LUTs can’t be used as slice out-
puts. Thus, the portion of logic needed
to compute p
1
has to be duplicated.
Anyway, this does not significantly
increase the area requirement. In fact,
the logic AND between the outputs of
two two-input XOR gates have been
mapped to one LUT (see Figure 5).
This efficient implementation also
allows the area overhead to be restrained
with respect to a simple ripple-carry
adder. More precisely, the generic
bypass logic block will occupy just k/4
slices. Each bypassing 2:1 multiplexer
will need just one auxiliary slice.
From this discussion you can con-
clude that for the generic group of k
bit positions, two separated propaga-
tion chains exist. The first, because of
the full-adders, represents the actual
carry-chain and occupies a column of
slices S1. The other chain, needed by
the bypass or carry-skip logic, occu-
pies the adjacent column of slices S0.
LAYOUT-LEVEL RESULTS
Figure 7 shows the layout of an adder
designed using the new approach; it
includes the case in which a 4k-bit
adder is realized with four k-bit
blocks. This organization has been
used to realize 96- and 128-bit adders
in an XCV50P240 Virtex device. For
the purposes of comparison, 96- and
128-bit conventional adders have been
also implemented. Because of the col-
umn capacity of this device (i.e., 16-
slice columns), we used 32-bit blocks
to realize both circuits.
You may download the layouts for
the 128-bit macro-generated adder and
proposed 128-bit adder from the Circuit
Cellar
ftp site. As expected, for the new
implementation, four columns of 16 S1
slices are used for full adders, whereas
only two half-columns of S0 slices are
needed to implement the bypass logic.
The bypassing 2:1 multiplexers used
to separate 32-bit blocks are placed at
the bottom side into the columns of
S0 slices. This allows the horizontal
paths, which are needed to transfer
I3
I2
I1
I0
LUT
WE
DI
O
G4
G3
G2
G1
BY
F5IN
0
1
0
1
C
OUT
MUXCY
XORCY
MI
YB
Y
INIT
D
CE
Q
REV
YQ
XB
F6
F5
Ck
WSO
WE
A4 WSH
BY DG
BX DI
MUXCY
0
1
I3
WE
I2
I1
I0
LUT
DI
O
BX
F4
F3
F2
F1
SR
CLK
CE
0
1
C
IN
XORCY
M2
INIT
D
CE
Q
REV
XQ
X
Figure 6—
A Virtex slice is essentially the same as a slice of the well-known Xilinx 4000-series CLB. The architec-
ture is much more complex than that of the Atmel cell in Figure 3, and it can handle more data as well. The includ-
ed fast-carry logic (C
IN
to C
OUT
) propagates carries extremely quickly because it uses gates instead of the much
slower look-up table logic.
Adder
Delay
Frequency Area
Area
(ns)
increase (%)
(n. CLB)
increase (%)
96-bit RCA
14.7
–
48
–
96-bit Bypass
11.6
26.7
58
20.8
128-bit RCA
20.3
–
64
–
128-bit Bypass
13.8
47.1
82
28.1
64-bit RCA
9.16
63.7
32
0
64-bit RCA
15
–
32
–
Block 16
64-bit Bypass
9.9
33.3
42
31.2
Block 16
Table 1—
As you can see from these results, we’ve gained some speed by removing nets from the critical path.
36
Issue 148 November 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
the output of these multiplex-
ers to the adjacent columns of
S1 slices, to be as short as pos-
sible. This is the key to ensur-
ing that the time needed for a
propagating carry to reach the
subsequent columns of S1
slices is much less than the
time required by a correspon-
ding adder without a bypass or
carry-skip mechanism.
The same considerations are
valid for the 96-bit implemen-
tation in which three columns
of S1 slices and one half-col-
umn of S0 slices are necessary.
On the contrary, in the lay-
outs of the conventional
schemes, only three columns
of S1 slices are needed.
Timing analysis has been
performed on both kinds of
adders and for both 96- and 128-bit
operand word lengths. Delay measure-
ments have shown that in both adders,
the worst addition operation takes
place when a carry is generated at the
least significant bit position and subse-
quently propagated all of the way to
the most significant bit position. This
explains why the proposed implemen-
tation does not use bypass logic for the
least or most significant block of bits.
Note that if the adder is used as part
of an adder for even longer
operands, then you should
consider using bypass logic
for the most or least signifi-
cant blocks of this adder.
As you can see in Table 1,
we achieved significant gains
in speed, particularly in com-
parison to macro-generated
ripple adders. This was
accomplished by eliminating
nets from the critical path
through which carries propa-
gate from a column of slices
to the subsequent ones.
Moreover, by using the pro-
posed approach, this speed
advantage is achieved with a
reasonable increase in the
number of occupied slices.
Obviously, the percentage
increase on the running fre-
quency and area overhead will grow as
the operand word length increases. For
the sake of completeness, several 64-bit
wide adders were also realized and
compared. The first is a macro-generat-
ed 64-bit conventional adder mapped
C
IN
C
OUT
Skipping mux
C
IN
third block
C
IN
fourth block
B
P
second block
C
OUT
second block
C
OUT
first block = C
IN
second block
C
OUT
third block
Column of slice S1 for carry-chains
Column of slice S0 for skip logic
B
P
second block
Figure 7—
Here is a rough sketch of our Virtex adder’s layout.
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 148 November 2002
37
into only two adjacent columns of
slice S1. The second implementation
is obtained by assuming that just
eight slices per column were available
in the area in which the adder had to
be placed. In this case, four columns
of slice S1 were needed. Finally, a
64-bit adder consisting of four 16-bit
blocks based on the logic we’ve pro-
posed has been realized.
The results and comparisons
obtained in this case are also reported
in Table 1. As expected, the layout
involving just one column of slice S1
ensures the most efficient implemen-
tation to be achieved. However, it can
be also noted that the 64-bit adder real-
ized with this approach exhibits speed
performance almost equal to that
reached by the optimum conventional
implementation. This demonstrates
that even at the 64-bit word length,
the new design still can be useful.
Specifically, if a completely vertical
routing cannot be ensured for lack of
layout space, the proposed bypassing
logic offers an efficient alternative to
the conventional scheme.
SECRET TO SUCCESS
We’ve presented fast and relatively
small carry-skip or bypass adders for
the Atmel AT40K and Xilinx Virtex
families of FPGAs. In the case of the
Atmel architecture, the previously
existing choices of available adders
were either the ripple adders or carry-
select adders. The ripple adders were
small but slow, and the carry-select
adders were large and slow. In the case
of the Xilinx architecture, none of the
previously known adders that were
faster than ripple adders were effective
enough (with respect to speed and
area) to be widely used.
Although carry-skip adders stemmed
from an idea developed by Charles
Babbage in the 1800s, they have not
been recognized in the industry until
recently. Even after they were accepted
for standard cell and custom imple-
mentations, they remained virtually
unknown in the world of FPGAs.
There’s a reason for this, though. It’s
challenging to design adders that are
faster than ripple adders for FPGAs
because interconnections are slow, and
the cells are optimized for rippling.
Vitit Kantabutra received his Ph.D. in
Electrical Engineering and Computer
Science from Johns Hopkins
University in 1985. He’s an associate
professor at Idaho State University in
Pocatello, Idaho. You may reach him
at vkantabu@computer.org.
Pasquale Corsonello earned his M.S.
in Electronics Engineering from the
University of Naples in 1988. He is an
associate professor at the University
of Reggio Calabria. You may reach
him at corsonello@ing.unirc.it.
Stefania Perri received a Ph.D. in
Electronics Engineering from the
University of Calabria in 2000.
Currently, she’s an adjunct professor at
the University of Calabria. You may
reach Stefania at perri@deis.unical.it.
Maria Antonia Iachino earned a
degree in Electronics Engineering
from the University of Messina, Italy
in 1997. She’s working toward a
Ph.D. at the University of Reggio
Calabria. You may reach Maria at
iachinom@ing.unirc.it.
SOURCES
AT40K FPGAs, IDS
Atmel Corp.
(408) 441-0311
www.atmel.com
Virtex FPGAs, XC4000, Spartan,
Spartan XL
Xilinx, Inc.
(408) 559-7778
www.xilinx.com
REFERENCES
[1] C. Babbage, “Calculating
Engines,” Exposition of 1851,
chap. XIII. Reprinted in P.
RESOURCES
P. Chan, M. Schlag, C.
Thomborson, and V. Oklobdzija,
“Delay Optimization of Carry-
skip Adders and Block Carry-
lookahead Adders,” Proceedings
of the 10th Symposium on
Computer Arithmetic, Grenoble,
France, 1991.
V. Kantabutra, “Designing
Optimum Carry-skip Adders,”
Proceedings of the 10th
Symposium on Computer
Arithmetic, Grenoble, France 1991.
V. Kantabutra, S.Perri, and
P.Corsonello, “Tradeoffs in Digital
Binary Adders,” in B. Lu, D. Du,
and S. Sapatnekar, Layout
Optimizations in VLsi Design
,
Kluwer Academic Publisher,
Dordrecht, Netherlands, 2001.
S. Turrini, “Optimal Group
Distribution in Carry-skip
Adders,” Proceedings of the 9th
Symposium on Computer
Arithmetic, Santa Monica,
California, 1989.
Morrison and E. Morrison,
Charles Babbage and His
Calculating Engines
, Dover
Publications, New York, 1961.
[2] S. Perri, M. Antonia Iachino,
and P. Corsonello, “Speed-
Efficient Wide Adders for
Virtex FPGAs,” ICECS 2002,
Dubrownik, Croatia, 2002.
[3] A. Buldas, J. Poldre, “A VLSI
Implementation of RSA and
IDEA Encryption Engine,”
Proceedings of the NorChip
Conference, Tallinn, Estonia,
1997.
[4] A. Elbirt, W. Yip, B. Chetwynd,
and C. Paar, “An FPGA
Implementation and
Performance Evaluation of the
AES Block Cipher Candidate
Algorithm Finalists,”
Proceedings of the AES
Candidate Conference, Rome,
Italy, 1999.
[5] Xilinx, Inc., Virtex Series
FPGAs, www.xilinx.com/part-
info/databook.htm.
Therefore, the secret to success that
we’ve presented is clear: use fairly long
ripple chains (because they’re fast), and
keep the entire design simple in order
to avoid excessive interconnections.
I
38
Issue 148 November 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
here are many
uses for a wireless
remote sensor in the
world of thermal-embed-
ded and stand-alone systems. We’ve
designed a wireless thermal sensor sys-
tem that’s low-powered, modular, and
can adapt to other sensor applications.
Being aware of external conditions
is one of life’s necessities. For embed-
ded electronics, sensors are the ele-
ments that translate physical, chemi-
cal, and environmental entities into
meaningful terms. Electronics sys-
tems ranging in complexity from
cruise controls to coffee makers rely
on sensing systems for control, com-
puting, and communication.
For many applications, thermal
sensing is critically important,
because the temperature of the envi-
ronment or host may indicate
mechanical failure, specific stages of
chemical reactions, or the need for the
electronic control of thermostats and
heating/cooling agents. Our intention
was to design a low-cost, low-power,
wireless thermal sensor system that
can operate at a range of 100
′
.
This thermal sensor system consists
of two circuit cards: a printed circuit
card that processes and transmits ther-
mal data wirelessly, and a receiver
board that translates the received data
into a serial RS-232 data packet. A
host computer that’s connected to the
receiver board acquires and displays
the data in real time through a graphi-
cal user interface developed with
LabVIEW graphical programming.
CIRCUIT DESCRIPTION
The thermal sensor’s electronics
operate with only a few integrated cir-
cuits. The basic operation of the cir-
cuit is based on a microprocessor that
reads thermal data from a sensor and
writes the data to a wireless transmit-
ter. Additional components were
added for power distribution, stability,
and control (see Figure 1).
We chose the PIC16C717 from
Microchip’s popular PIC family. The
PIC16C717 is an 8-bit microprocessor
available in 18- or 20-pin PDIP, SOIC,
or SSOC packages, with 256 bytes of
RAM and 2 KB of ROM. Additionally,
there are six channels of 10-bit ADC,
three hardware timers, and a serial
peripheral interface. An internal oscil-
lator is available, or you can use an
external crystal of up to 20 MHz.
In our circuit, the 18-pin version is
used. An external 96-kHz crystal is
connected to two pins of port A,
while another pin in port A is used
as an external master reset. The
remaining three pins in port B are
allocated for a hard-wired sensor
identification tag. Using these tags,
eight different sensors can send ther-
mal data simultaneously, allowing
the LabVIEW software to independ-
ently display their readings.
Pins in port B are used for an inter-
face between the PIC and thermal sen-
sor. Pins in port A interface the micro-
processor to the transmitter. The ther-
mal sensor interface is SPI protocol,
requiring pins for the clock and data.
The transmitter data interface is a sin-
gle unidirectional connection, with a
secondary connection for activating a
power-down mode for power reduction.
The feature-rich PIC16C717 is
also fairly easy to program because
the instruction set contains only
35 instructions. Code can be written
and debugged in Microchip’s free
MPLAB integrated development envi-
ronment. Writing code in C will sacri-
A Low-Power Embedded
Thermal Sensor System
t
It’s important that
your embedded elec-
tronics systems have
thermal sensors capa-
ble of monitoring their
external environments.
With a PIC16C717
and this project as
your guide, you can
build your own low-
cost, wireless, thermal
sensor system for
your future designs.
Divyata Kakumanu, Joel Jorgenson,
Tristan Simetkosky, Conrad
Thomas, and Brian Morlock
FEATURE
ARTICLE
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 148 November 2002
39
The HP-2 series has eight user-
selectable operating frequencies (902
to 928 MHz) and a free-space range of
up to 1000
′
. The HP-2 is capable of
transmitting both analog and digital
data using frequency modulation (FM)
or frequency shift keying (FSK) com-
munication schemes.
We also implemented an HP-2
series master development receiver
module from Linx Technologies. The
RS-232 port is tied to a PC running
the LabVIEW software from National
Instruments.
PRINTED CIRCUIT CARD
We used a two-layer printed circuit
card, measuring approximately 2
″
× 2
″
,
to assemble the sensor electronics in
the design (see Photo 1). Because the
microprocessor crystal is operating at
a modest 96 kHz, most of the signal
integrity concerns are eliminated,
specifically problems associated with
transmission lines, crosstalk, and ter-
minations. A few signal integrity
fice some performance and code com-
pactness, but it ultimately increases
the portability of the code.
The thermal sensor we chose for this
design was the LM70 SPI/Microwire
10-bit-plus Sign Digital Temperature
Sensor. It was chosen primarily for its
SPI interface and availability in the
MSOP package. The LM70 provides
temperature data in a Celsius 2’s com-
plement format with a 0.25°C LSb. The
LM70’s low-power Shutdown mode is
another attractive feature.
The power distribution system con-
sists of a REG103 voltage regulator,
power-on reset IC, decoupling capaci-
tors, and a 6-V lithium battery. The
voltage regulator assures a steady 3.3-
V supply that’s further improved
through the use of decoupling capaci-
tors. The lithium battery is capable of
providing 165 mAh. An external con-
nection is also available to allow a DC
input voltage from 5 to 15 V with a
series ferrite for filtering common-
mode injected noise.
The transmitter we used was the
HP-2 series RF module from Linx
Technologies. The only external RF
component required is an antenna,
which also can be obtained from
Linx Technologies as either an exter-
nal whip antenna or surface-mount
patch antenna.
Figure1—
Take a close look at this schematic to see how all of the Thermal Sensor System’s components are interconnected.
Photo 1—
The Thermal Sensor System is a 2
″
× 2
″
device consisting of a thermal sensor, PIC processor,
voltage regulator, and transmitter.
short as possible; it was designed as a
microstrip transmission line. We
used Agilent’s AppCad to calculate
the transmission line characteristic
impedance and select the intercon-
nect geometries for the desired elec-
trical performance.
CIRCUIT FUNCTIONALITY
Upon receiving power, the system
configures the ports of the micro-
processor and sets the wireless trans-
mitter to a power-down mode. The
initialization routine is executed to
provide the parameters that are criti-
cal to the operation of the sensor.
40
Issue 148 November 2002
CIRCUIT CELLAR
®
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issues were addressed, specifi-
cally in the power distribu-
tion system and the connec-
tion between the wireless
transmitter and surface-
mount patch antenna.
To ensure a stable power
supply, the voltage regulator
was supplemented with decou-
pling capacitors populated
throughout the circuit card.
The capacitor values (i.e., 1.0
and 0.1 µF) were chosen to ensure that
the power supply impedance was low
throughout the operating frequencies.
Models for capacitor performance are
available from vendor web sites, such
as AVX (www.avxcorp.com) and
Kemet (www.kemet.com).
For reliable circuit operation, the
signal from the transmitter to the
antenna needs special attention. The
technical manuals provided by Linx
Technologies will give you informa-
tion about the layout guidelines,
including the characteristic imped-
ance restrictions and trace length con-
siderations. The trace was kept as
After the ports are initial-
ized, the microprocessor sets
the chip select pin of the ther-
mal sensor. Data is shifted in
through the SPI communica-
tion protocol. When the
microprocessor receives the
data, it starts arranging the
bits in the form of data pack-
ets and sets the PWR_DN pin
of the transmitter high.
The wireless data packet
structure we chose for this applica-
tion was a 24-bit data sequence that’s
transmitted in three 8-bit sub-pack-
ets. Each packet contains start, stop,
and parity bits.
The first byte contains a preamble
that notifies the receiver/interrogator
that the next two bytes are valid data.
Using a preamble helps to reduce the
likelihood of random noise being
interpreted as valid data.
The next two bytes contain a 3-bit
header that signifies the identity of
the sensor sending the data and
11 bits of temperature data. After
the sensor data has been arranged,
Photo 2—
The LabVIEW interface is useful because it displays the control
parameters, current temperature, and a plot of the temperature history.
42
Issue 148 November 2002
CIRCUIT CELLAR
®
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it’s transmitted through the trans-
mitter. As soon as the transmission
is complete, the PWR_DN pin of the
transmitter is set low to conserve
the power.
The thermal data that has been
transmitted is collected by the receiv-
er and connected to a host PC via the
RS-232 serial port connection. Using
LabVIEW scripts, the data packets
containing the thermal data are read
and displayed in the temperature for-
mat (see Photo 2). The post-processing
of the thermal data is performed easily
by putting the data from the archive
into Excel spreadsheets.
Because we were working with a
battery-powered device, we took sev-
eral steps to minimize power dissipa-
tion. The majority of power dissipa-
tion is consumed during the wireless
transmission; therefore, the update
rate of the thermal data is reduced to
2 Hz (thermal data is transmitted
once every 500 ms). Devices were
placed in power-down modes, and
individual components were selected
for minimal power consumption.
Finally, the processor clock was
selected to be 96 kHz, which provid-
ed ample throughput and assisted in
reducing power demands. In total,
the power dissipation of the device
was approximately 3.75 mW, allow-
ing the thermal sensor to operate
continuously on a single charge for
more than one week.
LabVIEW
After the serial port is initialized,
the first byte of data is read from it.
The first byte of data is compared with
the preamble value. If both are equal,
the next two bytes of data are read and
converted to a decimal value. From the
conversions, the sensor ID and temper-
ature value are obtained. The tempera-
ture value is transmitted in the form
of 2’s complement, so it’s converted to
get the actual temperature value in
Centigrade and Fahrenheit.
SOFTWARE
Embedded C code was written to
sense data from sensors and meet the
system-level timing performance con-
straints. The code is adaptable to dif-
ferent sensors with slight modification
of the core code. Ideally, this code
could be ported to microprocessors
other than the PIC16C717. Our code
design provides the proper functional
control of the hardware architecture
with minimized usage of the PIC’s
built-in peripherals. You may down-
load the code for this project from the
Circuit Cellar
ftp site.
FLEXIBILITY
The design’s flexibility can be
demonstrated by replacing the ther-
mal sensor with a different sensor
with an SPI interface, or by selecting a
sensor with an analog output and con-
necting the sensor to an analog-to-dig-
ital converter that’s SPI-compatible.
Minor changes must be made to the
LabVIEW code in order to display the
appropriate data and units. With a lit-
tle engineering effort, the system can
be reconfigured to act as an infrared
thermal scanner, acoustic sensor,
solid-state volatile organic compound
detector, or accelerometer. Multiple
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 148 November 2002
43
sensors also can be connected to the
same microprocessor with individual
select lines for each sensor.
TROUBLESHOOTING
The basic design is easy to trou-
bleshoot, particularly because the
sensor system is a single master
design. If the circuit is not operating,
the first step is to see if the power
supply is providing 3.3 V to the cir-
cuitry. If the V
CC
is not at 3.3 V, look
for either a failed battery or a prob-
lem in the voltage regulator. When
an external DC power supply is used,
you may check the series ferrite to
ensure that it has not failed and cre-
ated an open circuit.
If the power supply is stable, the
microprocessor should begin commu-
nicating with the thermal sensor and
transmitter. This activity is easily
detected with an oscilloscope probe
on the chip-select line of the thermal
sensor, data pin, and power-down con-
trol of the transmitter.
When activity is not detected, you
should investigate for two different
problems. The microprocessor may be
held in reset, which would be detect-
ed if the external master reset pin of
the microprocessor port A is inadver-
tently held low. Otherwise, the crys-
tal inputs on port A may be inactive,
which would stop the clock input and
prevent functionality.
As for the receiver board, you can
check two signals if the sensor sys-
tem isn’t working. The first is the
power-supply signal, which supplies
5 V to the receiver circuitry. If the
power supply voltage is not at 5 V,
the battery needs to be replaced.
Also, a received signal strength indi-
cator pin on the receiver can be
monitored with an oscilloscope or a
multimeter. This signal will indicate
the presence of a valid transmission
from the wireless transmitter of the
thermal sensor.
Finally, the LabVIEW code is capa-
ble of troubleshooting. The serial port
may be probed for activity, ensuring
that the receiver board is connected
to the correct communications port.
Also, the LabVIEW code can be used
to detect parity error, which can be
indicative of a noisy environment.
ADAPTABILITY
Our thermal sensor system is low
powered and modular, making it ideal
for a wide range of applications. The
design can adapt to different sensors
by replacing the thermal sensor with
other sensors. This capability allows
the wireless thermal sensor system
to act as a versatile wireless sensor
system platform.
I
Divyata Kakumanu is a Ph.D. student
at North Dakota State University. Her
research interests include embedded
systems and integrated circuit
design. You may reach her at divya-
ta.kakumanu@ndsu.nodak.edu.
Joel Jorgenson earned his Ph.D. in
Electrical Engineering from Iowa
State University. Currently, he is an
assistant professor at North Dakota
State University. You may reach him
at joel.jorgenson@ndsu.nodak.edu.
Tristan Simetkosky is a Ph.D. stu-
dent at North Dakota State
University. You may contact him at
tristan.simetkosky@ndsu.nodak.edu.
Conrad Thomas earned a B.S.E.E.
from the University of Kansas. You
may reach him at conrad.thomas@
ndsu.nodak.edu.
Brian Morlock is a Ph.D. student at
North Dakota State University. You
may reach him at brian.morlock@
ndsu.nodak.edu.
To download the code, go to
ftp.circuitcellar.com/pub/Circuit_
Cellar/2002/148/.
RESOURCES
Linx Technologies,
“Considerations for Operation
within the 902-928 MHz Band,”
AN-00126, 1997.
———“HP Series-II Transmitter
Module Design Guide,” 1999,
www.linxtechnologies.com/ldocs/
f_prod.html.
Microchip Technology, Inc.,
“PIC16C717/770/771
Datasheet—18/20-Pin, 8-Bit
CMOS Microcontrollers with
10/12-Bit A/D,” DS41120B, 2002.
National Semiconductor, Corp.,
“LM70 SPI/MICROWIRE 10-Bit
Plus Sign Digital Temperature
Sensor,” DS101223, July 2000.
———“LM809/LM810 3-Pin
Microprocessor Reset Circuits,”
DS101057, April 2001.
J. Peatman, Design with PIC
Microcontrollers
, Prentice Hall,
Upper Saddle River, NJ, 1998.
Texas Instruments, Inc., “DMOS
500 mA Low Dropout Regulator,”
SBVS010A, July 2001.
L. Wells, LabVIEW Graphical
Programming for
Instrumentation
, Prentice Hall
Englewood Cliffs, NJ, 1995.
L. Wells and J. Travis, LabVIEW
for Everyone: Graphical
Programming Made Even Easier
,
Prentice Hall, Upper Saddle
River, NJ, 1996.
SOURCES
AppCad
Agilent Technologies, Inc.
(650) 752-5000
www.agilent.com
MPLAB, PIC16C717
Microcontroller
Microchip Technology, Inc.
(480) 899-9210
www.microchip.com
44
Issue 148 November 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
uch like animals
use stereo sound
detectors (commonly
called ears) to home in
on a sound’s source, the simple and
low-cost circuit described in this arti-
cle can give your robot a pair of ultra-
sonic ears, allowing it the same ability.
The ultrasonic transmitter might be
fixed at the robot’s home port, where
it returns for battery recharging, or it
might be part of a moving target that
your robot can follow around. You
could also impress your friends by
sticking the transmitter in your back
pocket so your robot, and maybe your
dog, can follow you around.
The idea behind this device is a fairly
simple one that takes advantage of the
fact that sound travels slowly through
air, certainly in comparison to light.
At 74 µs per inch (i.e., sea
level), it’s slow enough for
simple timing circuits to
measure how long it takes
to get from the transmit-
ter to the receivers in the
left and right ears. Unless
the transmitter is directly
ahead of both receivers,
wherein they would both
receive the ping simulta-
neously, one receiver has
to be closer. The robot
can differentiate between
the two.
Synchronization is difficult because
the remote transmitter’s ping is not
directly connected to the receiver’s
timing circuits. The solution is to
have the transmitter send pings at a
regular interval, which are then used
in groups of two, as shown in Figure 1.
The first ping is detected by the left
ear and used as the sequence start
marker. After this synchronizing ping
is detected, a blanking period occurs
before a window is opened, allowing
for the detection of the next ping by
the receiver closest to the transmitter.
RECEIVER
The receiver circuit is shown in
Figure 2. The ultrasonic receiver’s
transducers have a narrow reception
bandwidth around their operating fre-
quency of 40 kHz. After receiving the
transmitted acoustical energy, the
receiver generates an AC signal tens of
millivolts in amplitude depending on
the transmitted signal strength and
distance from the transmitter to
receiver. This small signal level is
amplified and converted to logic-level
pulses by two op-amps.
The input signal is capacitively
coupled through resistor R14 to the
inverting input of the first op-amp.
Together, resistors R15 and R14 deter-
mine the gain by which the millivolt-
level signal is amplified using the fol-
lowing equation:
[1]
Because the gain is high, the DC
voltage must be blocked from the
input signal or it will be amplified,
Ultrasonic Homing Device
m
Tom Baraniak is nei-
ther an otologist nor a
plastic surgeon, but
he can definitely fix
the ears on that robot
of yours. With this
project, Tom demon-
strates how to con-
struct a pair of ultra-
sonic ears that will
enable your robot to
steer its way to exact
locations.
Tom Baraniak
ROBOTICS
CORNER
Figure 1—The left ear is used to synchronize with the transmitted pings.
Then, whichever ear hears the next ping is the ear closest to the trans-
mitter. If they both hear the ping at roughly the same time, then the trans-
mitter is more or less directly in front of both ears.
Transmitted
pings
Left ear
Right ear
Left ear
Right ear
Ping travel time
Sync
Left ear detects ping before right
Right ear detects ping before left
Sync
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CIRCUIT CELLAR
®
Issue 148 November 2002
45
than this. Then, when the amplified
AC signal level exceeds the threshold,
the comparator’s output goes high.
Equations 3 and 4 determine the
virtual ground (V
GND
) and threshold
(V
TH
) relative to the virtual ground.
[3]
[4]
Note that R11 determines the thresh-
old, with increasing values raising the
threshold level. Values that are too
small will make the comparator sus-
ceptible to noise. If they are too large,
sensitivity will decrease to an unus-
able level. Typical values range from
100 to 2200
Ω.
The logic-level pulses from each ear
are monitored by two of the PIC
microcontroller’s general-purpose (GP)
I/O bits. Two more I/O bits provide
output indicating which ear hears the
ping first, if both ears hear the ping at
essentially the same time, or if the
signal fails to meet valid input condi-
tions. These can be used to control
the wheel drive motor logic directly or
through another controller.
EAR MOUNTING
The ultrasonic transducers should
be separated by several inches on a
parallel axis, as shown in Figure 3.
This is necessary to provide enough
time difference between when each
ear receives the ping. If they are too
close, unless the transmitter is way
off-center, they will both hear the
causing the output to run up against
the negative rail. This is accomplished
with capacitor C11. However, because
C11 is a reactive component, it has an
associated impedance that must be
added to resistor R14’s value in the
gain equation. The equation for capac-
itive impedance is:
[2]
In Equation 2, f is the ultrasonic fre-
quency of 40 kHz, and Z
C
is measured
in ohms.
Using a value of 0.1 µF for C11
shown in Figure 2, Z
C
= 40
Ω, which
is much less than R14 = 10 k
Ω, so it
can be ignored. The gain is set at 75,
which is less than the maximum
allowable gain at 40 kHz shown in the
datasheet for the OPA2340 op-amp.
Note that you can’t use just any op-
amp; it must be fast enough to pro-
vide the necessary gain at the desired
operating frequency. According to the
OPA2340’s datasheet, the typical max-
imum gain at 40 kHz is 100, which
exceeds the desired operating gain of
75, so this op-amp will work.
Because a single-supply op-amp is
used, it’s necessary to create a virtual
ground at a level approximately half-
way between power ground and 5 V
CC
.
Remembering that the voltage differ-
ence between the inverting and non-
inverting inputs to the op-amp must
be zero, the voltage applied to the
non-inverting input, in this case 2.5 V,
is reflected at the inverting input.
The DC output from the op-amp
will also be 2.5 V because C11 blocks
the effect of R14, effectively removing
it from the circuit so that the op-amp
behaves as a simple voltage follower.
The AC signal is amplified, however,
so the output of the op-amp will then
be the inverted and amplified 40-kHz
signal oscillating about virtual ground
of 2.5 VDC. The fact that the signal is
inverted does not matter because this
is true for both ears’ signals, and
they’re only relative to each other.
The second op-amp after the gain
stage acts as a comparator. When the
signal on the non-inverting input
exceeds the threshold level estab-
lished on the inverting input, the
output goes to the positive rail: 5 V.
When the input signal is less than the
threshold, the output goes to the nega-
tive rail: DC ground.
The threshold and virtual ground
are set with a common resistor divider
network. [1] From above, the DC out-
put level of the gain stage is set to vir-
tual ground. The threshold level of the
comparator should be slightly higher
Figure 2—The ultrasonic receiver’s signals are amplified and converted to digital pulses by dual op-amps. The
PIC microcontroller then determines which ear is closest to the transmitter.
S
d
X
A
B
E
C
D
d
L
d
R
d
T
Transmitter positions
Left ear
Right ear
Figure 3—As the transmitter distance increases, it’s
more difficult to differentiate between positions B, C,
and D. The effective range is greater with increasing
ear separation distance (S).
46
Issue 148 November 2002
CIRCUIT CELLAR
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application has the robot following
you around, range finding and ultra-
sonic bumpers may not be an issue. If
the transmitter is part of a base sta-
tion locator, the robot might commu-
nicate with the base station via a
radio link to command the transmit-
ter to ping when the robot is ready to
take a bearing. During that time, the
robot would disable its other on-board
ultrasonics. There would have to be
some delay between each system’s
operations to allow previously trans-
mitted pings to damp out so one does-
n’t interfere with another.
SOFTWARE
Each synchronize-then-locate cycle
begins by initializing the counters that
keep track of how many times each
ear has had a valid detection out of the
total amount allowed for that cycle.
The example we’re currently analyzing
has it looking for four ping detections
out of seven tries. After a delay of
about 6 ms, the sync routine waits for
detection by the left ear. When it’s
received, it becomes the reference that
the next detection is compared to.
After the sync pulse is detected,
another 6-ms delay is executed (see
Figure 1). After the blanking period,
the ears become active and the soft-
ware loops, waiting for an ear to
hear a ping. However, it loops
256 times, as controlled in the
chktim routine, so it doesn’t get
caught in an endless loop in case
the signal is lost. If no ping is heard
and the 256 loops are used up, the
program returns to the beginning of
the cycle and resets.
If an ear hears the second ping, a
pause is inserted, and the other ear
is also checked to see if it too heard
the ping. The pause allows the
ping at essentially the same time.
This is especially true the farther the
transmitter is from the receiver.
Table 1 shows the distances from the
transmitter at various points to the left
ear as d
L
and to the right ear as d
R
. The
difference between d
L
and d
R
is also
shown. Note that as the transmitter
distance increases, the difference
between when each ear detects the ping
decreases. Eventually, the difference will
be too small for the software to deter-
mine which ear received the ping first.
In Figure 3, the ear separation dis-
tance (S) is 10
″. As S decreases, so
does the difference between d
L
and d
R
.
However, S will be dictated by the size
and shape of your robot, and will
become the overriding constraint as to
how far away from the transmitter the
ears can differentiate the signal source.
The receivers (and the transmitter
for that matter) have decreasing sensi-
tivity the farther they are off the acou-
sical center. Ideally, the transmitter
would be in the same plane as the
receiver so that you’re not fighting a
vertical misalignment. This does not
mean they have to be at the same
height, but rather that they’re pointed
at each other as shown at points A
and E (see Figure 3). In other words, if
the transmitters are located in the
upper corners of a room, the receivers
should be pointed up toward them.
A means of panning the sensors,
either as a sensor unit or as the entire
robot, is necessary for the robot to
localize the transmitted signal. After
one is found, the robot can home in on
the exact location and steer itself to it.
THE TRANSMITTER
The transmitter circuit is shown in
Figure 4. The PIC micro generates a
ping consisting of five 40-kHz pulses
every 8 ms. When operating at 5 V,
the PIC’s I/O output bit can directly
drive the ultrasonic transducer. For
higher transmission power, the PIC
output can be buffered by an FET and
run at a higher voltage.
When using the FET, a resistor is
connected in parallel to the transduc-
er. This is because the transducer is
essentially a capacitor, and it’s neces-
sary to discharge the voltage that is
applied to it when the FET is on.
The resistor has to be small enough
to quickly discharge the capacitor to
maintain fast fall times, but not so
small that it shorts the power supply.
The duty cycle is short and a large
capacitor from the resistor to ground
keeps switching transients to a mini-
mum. Fancy active drivers can be
designed to mimic the PIC output at
voltages higher than 5 V. Step-up trans-
formers also can be employed; howev-
er, the slight performance gain does not
warrant the added complexity and cost
they would bring to this application.
When driven directly by the PIC I/O
output bit, as shown in Figure 5
,
a
resistor isn’t necessary because the
output actively drives both high and
low. What this means is that the cur-
rent is supplied to charge the ultrason-
ic sender capacitance and then a path
is provided to discharge it. Notice that
the sender connects between GP0 and
ground, eliminating C2, Q1, and R1.
Because the PIC is limited to 5 V,
that’s the most the transducer will see.
Your robot may also use ultrasonics
for other purposes such as a non-con-
tact bumper or range finding. Therefore,
it’s necessary to limit when the hom-
ing transmitter is operating. If your
Table 1—The distance (d
X
) between A and B (and D and E) is 36
″. Notice that as d
T
increases, the difference
between when each ear detects the ping decreases. In this example, the distance between receivers (S) is 10
″.
d
T
= 30
″
d
T
= 60
″
d
T
= 120
″
d
L
d
R
d
L
– d
R
d
L
d
R
d
L
– d
R
d
L
d
R
d
L
– d
R
A
46.86
″ 54.92″
8.06
″
69.97
″
75.60
″
5.63
″
125.28
″
128.51
″
3.23
″
B
30
″
31.62
″
1.62
″
60
″
60.82
″
0.82
″
120
″
120.42
″
0.42
″
C
30.42
″ 30.42″
0
″
60.21
″
60.21
″
0
″
120.10
″
120.10
″
0
″
D
31.62
″ 30″
1.62
″
60.82
″
60
″
0.82
″
120.42
″
120
″
0.42
″
E
54.92
″ 46.86″
8.06
″
75.60
″
69.97
″
5.63
″
128.51
″
125.28
″
3.23
″
Figure 4—The transmitter generates a ping every 8 ms. The
version shown here uses a buffer FET to drive the ultrasonic
transducer at a higher power.
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 148 November 2002
47
Tom Baraniak attended the University
of Wisconsin, Madison. Presently, he
is the Electronics and Lab Manager at
Carleton College in Northfield,
Minnesota. As a kid, Tom built his
first robot out of orange crates and
coffee cans. Today, his materials are
a bit more sophisticated. You may
reach him at baraniak@spexotics.com.
SOURCES
Ultrasonic transmitter and receiver
Jameco Electronics (distributor)
(650) 592-8097
www.jameco.com
PIC12C672 Microcontroller
Microchip Technology, Inc.
(480) 899-9210
www.microchip.com
OPA2340 Op-amp
Texas Instruments, Inc.
(800) 336-5236
www.ti.com
To download the code, go to
ftp.circuitcellar.com/pub/Circuit_
Cellar/2002/148/.
the robot’s many sources and commu-
nicate to the robot its location rela-
tive to the receivers via a radio link.
Similarly, multiple transmitters
could be located around the room,
and your robot could, over a radio
link, command each one to ping to
determine which one it’s closest to.
Note that the scheme presented here
is not restricted to the 8-pin PIC
series of microcontrollers; therefore,
it’s easily adaptable to the controller
of your choice.
I
other ear to hear the ping, though not
necessarily at the exact same time,
but rather within a period determined
by the pause. That way, if the trans-
mitter is roughly—though not exact-
ly—in front of the ears, both ears will
hear the ping at approximately the
same time. This is evaluated as equal.
If after the pause the other ear does
not hear the ping, the ear that did hear
it is determined to be closest to the
transmitter and its ping-detected
counter decrements down from four. If
the count is not zero, it means that
enough pings haven’t been detected
during this cycle. Each loop cycle
causes the loop total counter to decre-
ment before the program runs another
sequence. This repetition occurs until
either four ear ping detections have
been made, in which case the pings
detected counter will count down to
zero, or seven attempts were made
after which the loop total counter will
count down to zero.
If the loop total count reaches zero
before the ping detection count, then
there were not four successful detec-
tions in the allowed seven tries. The
program then resets and recycles.
However, if the ear does have four
detections, it will indicate so by set-
ting its I/O bit high and then returning
to reset and recycle. You may down-
load the software listing for this proj-
ect from the Circuit Cellar ftp site.
OPTIONS
Instead of mounting the receivers
on the robot and the transmitter at
the base station, you can put the
receivers at the base station while the
robot transmits the pings. You can
also use multiple receivers to pinpoint
the robot in a room. They could use
the existing ultrasonic radiation from
Figure 5—This transmitter functions in the same way
as the one shown in Figure 4, but does so with the
ultrasonic transducer driven directly by a PIC micro-
controller output port.
REFERENCE
[1] A. Raynus, “Voltage
Comparator Forms Pulse
Demodulator,” EDN,
November 1998.
48
Issue 148 November 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
ne of the entic-
ing things about
microcontrollers is
how they lend them-
selves to so many applications. I have
been able to incorporate them into
many of my hobbies, and, in the case
of this project, that hobby is aviation.
A good friend of mine has an experi-
mental aircraft; what started out as a
simple project—a single-axis autopi-
lot—turned into much more. For vari-
ous reasons the autopilot project lost
its appeal, but it was quickly replaced
by other ideas (a classic case of feature
creep). I eventually ended up with the
Air Data Computer.
Initially, I intended to display altitude
and something called true airspeed on
an LCD module. Many other items
were added, so the current version
requires paging through five screens of
the 2 × 24 LCD to see it all! Let’s start
by looking at the hardware involved.
MICRO DETAILS
The heart of the Air Data Computer
is the Philips P89C51RD2 microcon-
troller. This 8-bit micro has flash mem-
ory and is capable of running in 6-clock
mode, in which it can run twice as fast
as the traditional 8051. The part can
run in 12-clock mode, to allow compat-
ibility with legacy code, by setting an
SFR bit during run time or by setting a
bit during parallel programming. It is
also capable of running peripherals (e.g.,
the timers, UART, watchdog timer, and
the programmable counter array) in 12-
clock mode while the rest of the micro
runs in 6-clock mode, allowing for
increased performance and compatibil-
ity with legacy code.
I use most of the features in the
RD2 except for the entire code memo-
ry space, where I had room to spare.
The part also boasts a built-in boot-
loader that allows it to be programmed
and erased through the serial port.
To allow for programming and serial
communication during operation, the
system includes a MAX232 driver and
serial connector (see Figure 1). Two sep-
arate Windows-based ISP programming
utilities are free and available on the
’Net. This software makes program-
ming, erasing, and verifying the parts
simple. If an emulator is not available,
you can use a crash-and-burn style of
debugging with these software tools.
The Air Data Computer also takes
advantage of the ability to program
and erase sections of the memory
from within the application (in-appli-
cation programming, or IAP).
I originally provided the reset signal
with an RC circuit, but I replaced it
with a Fairchild FM810LSSX superviso-
ry chip. This simple (and tiny) three-pin
device throws the part into reset if the
V
CC
drops below 4.60 V; it also provides
the power-up reset signal (Figure 2).
ADC DETAILS
A Maxim 1294 analog-to-digital
converter handles the analog inputs
from the sensors. This 12-bit succes-
The Air Data Computer
o
When it comes to air-
plane safety and con-
trol, there’s always
room for improvement.
In this article, Richard
shows us how to
enhance a small
plane’s control panel
with an air data com-
puter that’s capable of
displaying speed, alti-
tude, and fuel data on
a 2 × 24 LCD.
Richard Soennichsen
FEATURE
ARTICLE
Photo 1—
The temperature sensor is mounted in an
air inlet duct.
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 148 November 2002
49
Initially, I observed a voltage offset
on the output of the pressure sensors,
but this was easily measured and
compensated for in software. I then
observed that this offset tended to vary
with temperature, so the internal tem-
perature sensor was added to allow a
simple calculation to further calibrate
the sensors dynamically. Luckily, I
had an extra ADC channel available.
The outside sensor is mounted inside
an inlet duct where it’s exposed to the
ambient air temperature (see Photo 1).
The reading from this sensor is used to
produce two temperature values: total
air temperature (TAT) and outside air
temperature (OAT). The former is sim-
ply the temperature as read directly
from the sensor; the latter is the tem-
perature that has been corrected for
ram air heating, which occurs by fric-
tion with the air. A rough correction
for ram air heating is as follows:
[1]
Future variants of the outside air
temperature sensor will be sealed in a
small enclosure, perhaps some alu-
sive-approximation converter boasts
±
0.5-LSB linearity error and has six
input channels and parallel output. I
chose the 1294 because of its single 5-V
supply voltage and it’s parallel output,
which simplifies the code needed to
interface the micro to the ADC.
Its QSOP package also takes up lit-
tle board space. A 470-pF capacitor to
ground was added to each input of the
ADC. Taking a reading with this ADC
means first writing a control byte to
the device, and then reading the result
after the conversion is complete.
The control byte specifies the analog
channel to be read, bipolar or unipolar
modes, single-ended or pseudo-differen-
tial modes, acquisition modes, and
internal or external clock. In this sys-
tem, it specifies one of the six channels,
unipolar mode, internal acquisition,
and whether or not to use the internal
clock. Writing to or reading from the
device is achieved through the manipu-
lation of write, read, and chip select
lines while the control byte is placed on
the lower eight bits of the 12 output
lines that are bidirectional.
Acquisition speed was not a factor in
this application, so I had time to run
many readings through an averaging
routine to smooth the results. The
12 bits of output are connected to
1.5 ports of the Philips controller that
are configured as input by writing ones
to them. In future variants of this proj-
ect I may switch to an ADC with serial
output because the speed of a parallel
interface is not necessary, and it would
free up 10 pins of the microcontroller!
SENSORS
Motorola makes fully integrated pres-
sure sensors—and boy do they make
life easy. The nonintegrated versions
require signal conditioning with an op-
amp and assorted passive devices. The
integrated versions have an output volt-
age swing of almost 5 V that’s propor-
tional to pressure changes. They are
also temperature-compensated over a
wide range and have typical maximum
error of just a few percentage points.
This design utilizes three of the inte-
grated sensors: two MPX4115AP single-
port sensors and one MPX5010DP dual-
port sensor. Both sensors incorporate a
strain gauge produced by micromachin-
ing techniques. The single-port sen-
sors are referenced to a built-in inter-
nal vacuum, and the dual-port sensor
references one port to the other to pro-
vide a differential pressure value.
Two more analog inputs come from a
pair of Analog Devices AD22100 tem-
perature sensors. Like the Motorola
pressure sensors, these also produce an
output that’s close to 5 V at full swing
and is proportional to temperature.
Therefore, they did not require signal
conditioning (see Figure 3).
TEMPERATURES
One sensor measures the outside
temperature and the other measures the
temperature inside the enclosure. The
latter is used for the temperature com-
pensation of the MPX pressure sensors.
Photo 2—
The LCD is mounted on the instrument
panel. On the left is the knob for adjusting the baro-
metric pressure and the switch for selecting screens
and adjusting the fuel remaining value.
Photo 3—
By looking at this screen shot, you can tell
that the FlashMagic programming utility is a slick tool!
Photo 4—
I want you to get an insider’s view of the
computer. The yellow tubes attach to the pressure
sensors. The connectors include a serial connector
that sends and receives data to and from the GPS and
is also used for programming. The others go to the
LCD and receive the revolutions per minute, tempera-
ture, and fuel flow signals. The two buttons are for put-
ting the microcontroller in Programming mode.
Photo 5—
As you can see, the backside of the PCB
shows the surface-mount MAX1294 ADC, the
MAX232, and assorted capacitors.
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CIRCUIT CELLAR
®
Issue 148 November 2002
51
Airspeed that’s compensated for
temperature, or, more specifically, air
density, is called true airspeed (TAS).
TAS represents how fast the aircraft is
moving through the air. Keep in mind
that this does not tell you how fast
you’re traveling over the ground,
because there is undoubtedly some
wind that will produce a component
of headwind or tailwind. A decent
approximation for TAS is:
[2]
where
ρ
is the air density and
ρ
SSL
is
the air density at sea level at a standard
temperature. Here, IAS is calculated as:
[3]
Density (
ρ
) = Pressure/RT. Do you
remember that from chemistry class?
So, if you measure temperature,
atmospheric pressure, and pitot pres-
sure, then you’re able to calculate true
airspeed. Aircraft that travel at greater
speeds need to take into account the
compressibility of air that will affect
the readings. The airspeed value that
accommodates this is called Mach,
which is expressed as a decimal frac-
tion of the speed of sound:
with the equation,
[4]
where OAT is the outside air tempera-
ture. I chose the Motorola MPX5010DP
ρ
minum tubing filled with a thermally
conducting compound and sealed with
epoxy. Somehow that TO-92 package
dangling in the wind is less than aes-
thetically pleasing.
A NEED FOR SPEED
Measuring airspeed was one of my
goals for this project. In an airplane,
airspeed is typically displayed on an
old-fashioned steam gauge, which is
nothing more than a differential pres-
sure gauge. The airspeed indicated by
such a gauge is called indicated air-
speed (IAS). The pressure for the air-
speed indicator comes from something
called a pitot tube, which is an orifice
exposed to an undisturbed portion of
the air stream.
Ram air hitting the opening creates
pressure that’s translated into a speed
indication at the gauge. This pressure
is referenced against static pressure.
Static pressure is obtained from a
small hole that’s exposed to the
atmosphere and located on the air-
frame in a place that’s relatively
undisturbed by airflow. Locating the
static pressure source in such a way is
necessary because the cockpit may be
at a different pressure than that out-
side the aircraft.
So, how do I one-up the indicated
airspeed that’s already available in the
aircraft’s primary instruments?
Indicated airspeed is just that, indicat-
ed. It’s not compensated for tempera-
ture or air density; therefore, it only
gives you a relative indication of how
fast you’re moving through the air.
dual-port sensor for airspeed because
it has the correct pressure range. One
port goes to the static port and the
other to the pitot sensor.
HOW HIGH IS HIGH?
Altitude is, of course, of primary
importance to a pilot. In the following
equation, altitude is given as a func-
tion of the pressure at a given altitude:
[5]
In this instance, P is the pressure at a
given altitude, and P
o
is the local
barometric pressure. I’ve heard that
the U.S. Army derived this equation,
known as the standard atmosphere
equation, in the 1930s. In any case,
I’ve tried it, and it works well.
The local barometric pressure is
not calculated, but is entered manu-
ally using a potentiometer, which
acts as a simple voltage divider. One
channel of the ADC is used to read
this voltage. Then, some math is
done to convert it to pressure, which
is displayed on the LCD. When flying
from one area to another, the baro-
metric pressure will vary; so for an
altimeter to read correctly, it must be
adjusted properly. All aircraft altime-
ters will have a barometric pressure
setting associated with them.
Typically, the pilot will know the
local barometric pressure, because it’s
part of the air traffic controller’s job
to inform him, and he or she will
continually update the altimeter’s
barometric pressure setting.
Another altitude, which is often of
great importance to pilots, is density
altitude. This is altitude that’s correct-
ed for air temperature and air density.
This altitude is important because it
will help the pilot decide if the run-
way at a given elevation and with a
specific air temperature is long enough
for a safe takeoff. It also allows the
pilot to determine the amount of
engine horsepower available.
Density altitude is normally calcu-
lated by hand, so having it displayed
directly aids in preflight planning. An
approximate, but fairly accurate, for-
mula for density altitude is:
Altitude
1
–
Figure 1—
The Air Data Computer includes a power supply, LCD, and RS-232 interface.
52
Issue 148 November 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
DensityAltitude(ft) =
pressure_altitude + 118.6 × (T – T
S
)
[6]
where pressure_altitude is simply the
altitude at a standard barometric pres-
sure setting of 29.92 in Hg, T is the
temperature, and T
S
is a standard tem-
perature. The Motorola MPX4115AP
single-port sensor has the correct
pressure range, so it’s used to sense
the pressure associated with altitude.
MONITORING THE ENGINE
What is the most important device
on a single-engine airplane? The engine
of course! I took advantage of the pro-
grammable counter array (PCA) in the
Philips controller to monitor the rev-
olutions per minute and fuel flow. My
friend’s airplane is equipped with an
electronic ignition unit that provides a
signal to drive a tachometer. The signal
is a square wave, 0.8 ms in duration,
with two pulses per revolution. This
is fed to the PCA that’s configured in
Capture mode. An interrupt routine
detects the first and second edge of a
pulse period, and it starts and stops a
timer appropriately. Performing some
simple math on the time between
edges gives the revolutions per minute.
Engine manifold pressure is used to
set the throttle in many airplanes,
including my friend’s. Adding mani-
fold pressure to the displayed data
was one of the simpler tasks because
it was a pure pressure calculation,
consisting of the transfer function
specified by Motorola plus compensa-
tion for temperature and sensor offset
error. The sensor used for manifold
pressure was also a MPX4115AP.
FUEL
In order to measure fuel flow, a
FloScan 201B-6 turbine flow sensor
was implemented. This is a slick
sender that uses a low-resistance tur-
bine and an optical gate to send about
30,000 pulses per gallon of fuel.
The signal was also fed to a PCA
input of the microcontroller where a
pulse edge causes a PCA interrupt.
When a rising edge is detected, a flag is
set to indicate that this is the first
edge. After the second rising edge caus-
es an interrupt, the timer is stopped
and some arithmetic is performed to
compute gallons per hour. Every sec-
ond, the fuel flow value is subtracted
from the total fuel remaining, which
is also displayed. On fuel-injected air-
craft, because a percentage of the fuel
delivered to the engine is returned to
the fuel tanks, two sensors would be
used with the returned fuel value sub-
tracted from the delivered value.
As I mentioned earlier, the Philips
P89C51Rx2 line of microcontrollers
feature in-application programming
(IAP) capabilities. IAP routines allow
the running application to program
and erase flash memory in code space.
IAP routines include write data byte,
read data byte, erase block, read signa-
ture bytes, and so on.
In this application, I used IAP calls
to save the total fuel remaining to an
unused 4-KB block of flash memory.
The 64 KB of flash memory on the
current Philips RD2 is divided up into
4-KB blocks. This adds versatility
over older devices, which had 8- and
16-KB blocks because the flash mem-
ory is erased via IAP calls in blocks.
Every second, the remaining fuel is
tested against its previous value. If it’s
Figure 2—
Check out the P89C51RD2 microcontroller and analog-to-digital converter section of the Air Data Computer.
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 148 November 2002
53
different, it’s saved as 3 bytes of
BCD. At startup, the flash block
containing the remaining fuel is
scanned by looking for a value
FFH. The erased state of the flash
memory is all ones, so the first
FFH encountered will indicate
that the previous 3 bytes are the
last remaining fuel data stored.
These values are then stored
as variables as the current fuel
quantity. If the address of the
last stored byte is close to the
end of the memory block, then
the IAP block erase function is
called, the block is cleared, and
the remaining fuel values are
stored from the first address of
the block. The pointer to the
fuel remaining is then reset to the
beginning of the block. This is a
handy way to store nonvolatile data
without the need for on- or off-chip
EEPROM memory.
GRAB THE DATA!
Already installed on this airplane is
a commercial GPS/moving map navi-
gation unit, which, through a stan-
dard RS-232 interface, may be config-
ured to output many types of data,
one of which is groundspeed.
Although I’ve calculated and dis-
played true and indicated airspeed, this
doesn’t tell me how fast the aircraft is
moving across the ground. As an air-
plane flies higher, the winds generally
become more and more pronounced.
Indeed, I remember that when I was
learning to fly, cars driving on the high-
way below were giving me a run for
my money because of headwind.
Because the GPS provides accurate
groundspeed, you can combine it with
your fuel values to calculate and dis-
play miles per gallon, endurance (flying
time until the fuel is exhausted),
range (How far can you go?), and, of
course, groundspeed. If you compare
true airspeed with groundspeed, then
you can also calculate how much head-
wind or tailwind you’re experiencing.
The GPS unit also sends out the
distance to your destination, which
you can grab, and use to calculate and
display the amount of fuel remaining
at the destination. If this is a negative
value, you had better stop for gas!
The GPS unit will also accept data
that it is unable to compute—includ-
ing true airspeed, altitude, tempera-
ture, density altitude, and so on—via
the same serial interface. I plan on
adding this feature in future software
revisions (see Figure 4).
THE USER INTERFACE
Because space was limited on the
instrument panel of my friend’s air-
plane, the display size and number of
controls had to be kept to a minimum.
A 2 × 24 LCD was the best fit for a dis-
play, and I was able to limit the con-
trols for user inputs to one push button
and one potentiometer (see Photo 2).
The display is a standard Hitachi
44780-based 2 × 24 LCD module oper-
ating in 8-bit mode. I chose a backlit
super twist-type LCD for maximum
visibility. The data is displayed on a
total of five displays, which are
selected with the push button.
The five screens include: an altitude
screen, which includes altitude, pres-
sure altitude, density altitude, and
barometric pressure (set by the pilot);
an airspeed screen, which includes
indicated airspeed, true airspeed, Mach,
and total air temperature; an engine
screen, which includes manifold pres-
sure, revolutions per minute, and out-
side air temperature; the first fuel page,
which includes gallons per hour, nauti-
cal miles per gallon, fuel used, and fuel
remaining; and the second fuel page,
which includes endurance, range, and
fuel remaining at destination.
Because the pilot will be using
fuel and then refueling, it’s neces-
sary to reset the fuel remaining
value after a fill-up. Pressing and
holding the push button for 5 s,
after which time the computer
will be in Fuel Entry mode,
accomplishes this. The screen
will display the current fuel value
and then slowly increment to the
“full tanks” value (in this case
40 gallons). This repeats from the
minimum takeoff fuel amount to
the full tanks value in case the
pilot misses it. After the button
is released, the value is stored via
an IAP call in the flash memory
and also as the current fuel value.
CODING COMPLICATIONS
The compiler I used was the
Raisonance IDE (RIDE) environment.
RIDE is a suitable development envi-
ronment for all of the Philips 8-bit
controllers as well as the 16-bit XA
parts. In addition, RIDE will port C
code directly to the XA.
RIDE includes a fine simulator that
simulates all of the peripherals, includ-
ing bit-level simulation of the UART. It
also includes a utility called code com-
pressor that’s effective at squeezing the
code size. A fully featured demo ver-
sion is available on the Raisonance
web site (www.raisonance.com).
I wrote the code in C with the
exception of the IAP routines, which
are written in Assembly. The
Embedded Systems Academy makes
a library of IAP routines available on
its web site in addition to ISP pro-
gramming software (FlashMagic) and
other code and utilities for the
Philips microcontrollers. You will
also find there a C library imple-
menting fail-save variable storage in
flash memory sectors.
FlashMagic is a great tool for pro-
gramming the Philips flash memory
microcontrollers; it remembers all of
your settings, reloads the hex file
automatically, and will erase, pro-
gram, and reset the part with one
click (see Photo 3).
The main loop consists of calls to
computation functions and display
routines. All data, TAS, OAT, and so
on are computed repeatedly while a
Figure 3—
The signal inputs for the Air Data Computer come from three
pressure sensors, two temperature sensors, and one potentiometer.
54
Issue 148 November 2002
CIRCUIT CELLAR
®
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display routine updates the LCD
module with the current screen. The
values must be computed because
much of the individual data depends
on other values.
Although performing floating-point
calculations with software is slow,
speed is not much of an issue with
this system. Therefore, I took advan-
tage of the Raisonance math library
and performed the calculations in
code without look-up tables. There’s
plenty of time to do computations,
receive serial data, and so on because
the values on the display have to be
updated only a few times per second.
Care must be taken with the PCA
interrupts to avoid erroneous values,
specifically for the revolutions per
minute and fuel flow in this case.
Because I was measuring the time
between edges, I had to make sure
that a second edge was not missed.
This was the case during early ver-
sions of the code. I saw values that
were twice what they should be.
Some of my routines, including the
reading of the ADC, require that I dis-
able interrupts. If these routines are
long enough to cause a PCA interrupt
to be missed, the revolutions per
minute and fuel flow values will be
twice what they should be. I solved
this problem by clearing the flags
associated with the PCA first-edge
detect in the longer routines. This
way, any missed edges are ignored.
The Screen Select (and fuel level
set) button triggers an external inter-
rupt. The ISR will advance to the
next screen if the button is released
quickly or adjust the fuel remaining
value if held for 5 s. Counting suffi-
cient 16-bit timer overflows while the
button is held, and then entering a
separate routine to change the value,
accomplishes this.
CONSTRUCTION EXPERIENCES
Almost everything resides on a
3.8
″
× 2.5
″
PCB. This size was deter-
mined by the great “Three boards for
$59!” special at expresspcb.com.
Express PCB provides free software
that does the job even though it isn’t
fancy. The top of the board holds the
micro in a PLCC44 socket, the pres-
sure sensors, one temperature sensor,
and other assorted devices (see Photo
4). The backside of the board holds a
MAX232 serial driver, the MAX1294
ADC, and several passive devices (see
Photo 5). You should note that solder-
ing the MAX1294 in its QSOP pack-
age required quite a bit of patience
and strong magnification.
I
RESOURCES
D. Rogers, “Airspeed,” 1999,
web.usna.navy.mil/~dfr/air-
speed_wide.pdf.
E. Williams, “Aviation Formulary
V1.35,” williams.best.vwh.net/
avform.htm.
Embedded Systems Academy, IAP
flash tools, IAP code library, and
more, www.esacademy.com.
Philips Semiconductors, WINISP
programming utility, V. 2.29, 1999,
www.semiconductors.philips.com.
Richard graduated with a BSEE from
San Jose State University. He is a pri-
vate pilot and currently works as a
microcontroller applications engineer
at Philips Semiconductors in
Sunnyvale, California. You may reach
him at richard.soennichsen@philips.com.
SOURCES
Raisonance IDE (RIDE)
American Raisonance, Inc.
(877) 315-0792
www.raisonance.com
AD22100
Analog Devices, Inc.
(617) 329-4700
www.analog.com
FM810LSSX Supervisory chip
Fairchild Semiconductor Corp.
(800) 341-0392
www.fairchildsemi.com
201B-6 Turbine flow sensor
FloScan Instrument Co., Inc.
(206) 524-6625
www.floscan.com
MAX1294, MAX232
Maxim Integrated Products, Inc.
(408) 737-7600
www.maxim-ic.com
MPXxxxx Pressure sensors
Motorola, Inc.
(847) 576-5000
www.motorola.com
P89C51RD2 Microcontroller
Philips Semiconductors
(800) 234-7381
www.semiconductors.philips.com
Pressure sensor
Maxim
MAX1294 ADC
Philips
P89C51RD2
microcontroller
Commercial
GPS
2 × 24 LCD
Manifold pressure
Static port pressure
Pitot pressure
Barometric pressure
(voltage from potentiometer)
Outside temperature sensor
Internal temperature sensor
Screen select push button
Fuel flow sender
RPM sender
Air Data Computer
MAX232
Figure 4—
The three inputs at the top are the pressures applied to the Motorola MPX sensors. All analog inputs
are converted by the MAX1294, while the Screen Select button and the pulse inputs are handled directly by the
P89C51RD2 microcontroller. Communication with the GPS is through an RS-232 interface.
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58
Issue 148 November 2002
CIRCUIT CELLAR
®
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he electric
motor is a useful
and fascinating thing.
We use them daily for
tasks like washing our clothes and
cooling and heating our homes. Today,
it looks like we’re well on our way to
using them to power our automobiles
as well. The growing popularity of
robotics has even put servo- and step-
per-based electric motors on intelligent
mechanical platforms to provide
motion energy for wheels, tracks, and
electronic appendages.
Have you ever considered
where the parts for the
robots, cars, fans, washing
machines, and motors ini-
tially come from? Well,
here’s a suggestion: a com-
puterized numerically con-
trolled (CNC) milling
machine. Many of the
metal and plastic parts, as
well as the molds that
make them, start from a
solid block of metal or plas-
tic positioned on a precise,
electrically motorized x-y
table at the mercy of an
electrically motorized z-axis
CNC milling machine bit.
The key to the CNC machine’s suc-
cess is its ability to maintain precise
control of the electric motors in its
domain. Naturally, the first “C” (i.e.,
computerized) in CNC provides the
bulk of the precision with the help of
specialized programming. However,
the outputs of a computer’s I/O ports
weren’t designed to directly drive
high-voltage, high-current motors. A
buffer or translator must reside
between the computer’s I/O port and
electric motor. That buffer/translator
is called a drive.
Unfortunately, hooking up this com-
puter-drive-motor thing can become a
complex wire trap for the uninitiated
designer. So, I’m going to perform some
word algebra here to help you solve the
computer-drive-motor equation.
First, I’ll replace the unknown com-
puter with a standard desktop PC run-
ning Windows or DOS. Then, I’ll
equate the precision software running
the motors on the PC to a program
called Indexer LPT. Finally, I’ll substi-
tute the motor drive with a Gecko.
No, not the lizard on those television
commercials, I’m referring to an elec-
tronic Geckodrive instead.
In the words and pictures that fol-
low, I’ll describe the electronic side of
a standard milling machine motor
drive retrofit. As you’re reading, keep
in mind that all of the basic concepts
of motor control that apply to milling
machine conversion can be applied to
other applications that require precise
motor control as well.
Geckodriving Your Motor
Control Applications
t
Although not a
machinist, Fred knows
how to retrofit old
milling machines, and
can apply this engi-
neering technique to
various projects. This
month, he shows you
how a Geckodrive and
precision software can
enhance designs that
call for precision motor
control.
Fred Eady
APPLIED
PCs
Photo 1—
The Geckodrive G210 is small and light enough for robotics
and embedded applications. The Geckodrive case is clearly marked,
which makes it fast and easy to hook up the motor.
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CIRCUIT CELLAR
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Issue 148 November 2002
59
the Geckodrive is replacing in the bed
of a pickup truck. Photo 2 is an inside
shot of my little G210, and it shows all
of the jumper points that I’ve described.
INDEXER LPT
The Geckodrive G210 will take care
of the physical part of the computer-
drive-motor equation; however, you’ll
need to add some finesse to the mix
so that you don’t destroy your motors
(or motorized equipment) by abruptly
starting, stopping, and changing the
directions of the motor shafts. Also,
you’ll need a common set of com-
mands that you can issue to affect the
motion provided by the motors. That’s
where Indexer LPT comes in.
Indexer LPT is a 32-bit Windows-
based program that utilizes standard PC
parallel ports to issue step and direction
commands to motor drives like the
Geckodrive G210. In addition, Indexer
LPT has provisions to read the input
lines of the parallel port as well. This
allows limit switches or other signaling
methods to be added to the motor drive
functionality provided by the Gecko-
drive/parallel port combination.
Up to four parallel ports can be driv-
en by the Indexer LPT, which equates
to a maximum of eight axes of motor
operation. My application uses two
standard dual parallel port cards to
provide three axes of motion: x, y, and
z. The remaining parallel ports are
reserved for the Indexer LPT hardware
assist module (HAM) and various
other duties, including spindle con-
trol, coolant control, and operator
push buttons. Each parallel port is
associated to the Indexer LPT soft-
ware by its unique hardware address.
You can enter this association into the
Windows registry when it’s time to
set up the software.
Indexer LPT takes care of the com-
putations needed to control the
motors smoothly. The stepper motors’
speed and acceleration is controlled by
values entered into the Indexer LPT’s
internal registers. Thus, acceleration-
controlled motion is provided via
Indexer LPT by using its Move, Feed,
and Arc commands.
In addition to providing optimal
acceleration and deceleration profiles
for the motors, Indexer LPT also keeps
THE GECKODRIVE
The lizard you see in the left corner
of Photo 1 is a common Florida fence
lizard, or green anole for you lizard
connoisseurs in the audience. It would
take a box full of these to get enough
of their little feet working to turn the
spindle of an electric motor. For
motor control applications, the other
Gecko in Photo 1 is a better choice.
The Geckodrive you see in Photo 1
is a G210 stepper motor driver. The
G210 can drive four-, six-, and eight-
wire stepper motors at phase currents
of 0.3 to 7 A. The minimum drive
voltage that the Geckodrive module
requires is 24 VDC, with the maxi-
mum motor voltage that can be
applied capping off at 80 VDC. This
means that the Geckodrive G210 can
be wired to a motor according to the
performance the application requires.
To drive a stepper motor efficiently,
you must apply four to 20 times the
motor’s rated voltage. It may be desir-
able to connect the motor windings in
parallel for more power. The
Geckodrive G210 is designed to han-
dle almost any stepper motor winding
wiring and power selection scheme
you wish to employ.
The Geckodrive can operate at step
rates as high as 200 kHz, and its
optoisolated motor step and direction
inputs are designed to work with stan-
dard TTL current-sinking logic. If
your motor-driving application com-
puter hardware isn’t TTL-compatible,
there are headers inside the
Geckodrive that allow you to config-
ure the optoisolated step and direction
inputs as common ground or common
5 VDC. Use the common ground set-
ting if the Geckodrive is going to be
driven by a standard PC parallel port,
or any other I/O port that isn’t
equipped with open-collector transis-
tors or TTL logic.
My Geckodrive has all of the good-
ies that machinists and stepper
motors want, such as automatic cur-
rent reduction, low-speed resonance
nulling, and microstepping. Similar to
the optoisolators, there are headers for
the selection of full-step and half-step
operation. For stepping, the mini-
mum logic low input step pulse time
is 0.5 µs, and the logic high minimum
time for a step pulse is 4 µs. The
microstepping occurs on the falling
edge of the step input pulse.
A 5% tolerance quarter-watt current
set resistor is used to program the out-
put current level to the motor wind-
ings. There are standard values for
specific current ranges listed on the
Geckodrive’s casing. You can also use
the following formula:
[1]
Equation 1 allows you to determine
the value of the current set resistor, R.
If you wish to operate the Geckodriver
with a motor that draws less than 1 A,
then the current set resistor formula is:
[2]
Automatic current reduction
reduces the motor phase current to
33% of the set value when the motor
is stopped. A jumper enables or dis-
ables the automatic current reduction
feature of the Geckodrive G210.
Low-speed resonance nulling is per-
formed by adjusting the ADJUST
potentiometer, while turning the step-
per at approximately 15 rpm. What
you’re looking for is a potentiometer
adjustment that minimizes the motor
vibration at this low speed. You’ll gain
better stepping accuracy by making
this adjustment.
The G210 is small and light enough
to ride on your robot as well. The 2.5
″
square brick is only 0.82
″
deep and
weighs less than 4 oz. You’ll have to
haul around the older motor drives that
Photo 2—
This lizard doesn’t sit on a fence; instead, it
packs lots of horsepower in a very small package.
Under the circuit boards, there are eight power
MOSFETs attached to the integral heatsink.
the machine frame. The force of the x-
y table’s impact sheared the frame and
destroyed the x-y table.
Software like Indexer LPT and hard-
ware like the Geckodrive are designed
to work together to get maximum effi-
ciency from the motors under their
control. This means that the motor
generates a tremendous amount of
energy, which could get out of control,
injuring operators and damaging
machinery. Therefore, limit-switch
logic is a necessary component for
overall safety when you’re employing
powerful motors. That’s why Indexer
LPT has made provisions for incorpo-
rating limit-switch logic.
Commands are transferred to Indexer
LPT by accessing the Indexer LPT
ASCII text-based device driver. The
device name that’s used to communi-
cate with Indexer LPT is “motor.” To
transfer a set of Indexer LPT com-
mands using a DOS window, all you
have to do is place the commands in a
file and copy that file to the motor.
For instance, suppose you placed a
set_home command for axis A in a file
called home.cmd. The home.cmd file
would consist of a single statement—
set_home:a—followed by a carriage
return. To pass the command to
Indexer LPT, you would type “copy
home.cmd motor” and hit the Enter
key. This simply copies the home.cmd
file to the motor device.
In addition to being able to accept
user commands from a DOS copy
command and feed them to the
Geckodrive via the PC’s parallel port,
Indexer LPT also can take commands
from Pascal, C, and BASIC programs
programmatically. To accomplish this,
the motor device is opened for read
and write just like a file.
For BASIC users, the
print and
line input statements are used to
send and receive the ASCII com-
mands to and from the device driver.
C users would use
fputs and fgets,
and Pascal users would employ
WriteLn and ReadLn.
Using program languages like BASIC
and C to communicate with Indexer
LPT is not as popular with machinists,
because they predominately use G Code
to do their work. A companion product
called G Code Controller is also avail-
able from the Indexer LPT folks.
G Code is a standard language used
by the machine industry that allows
one language to control almost any
milling machine, lathe, or punch. No
matter what the application or type of
60
Issue 148 November 2002
CIRCUIT CELLAR
®
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up with the number of steps the
motor is commanded to take. This
step accumulation process adds and
subtracts pulses to establish a position
that’s relative to a home point in x-y-z
coordinate space. The set_home and
position commands are used as to
determine relative position during or
after the execution of a set of Move
and Feed commands.
In a milling machine application,
the Jog command is used to position
the x-y table and spindle to a predeter-
mined position. The Jog command
also can be invoked to move the
motor at a constant velocity. One
application of the Jog command is to
allow the operation of the motors to
determine where the limit switches
actually activate.
To explain just how important limit
switches are, I’ll share a true story
with you. A night operator made a
single change to a program running on
a lathe, thinking it would reduce the
time it would take to cut the piece.
He didn’t set or include any limit
switches or limit-switch parameters
into his change. Consequently, when
the operator ran his modified program,
the lathe’s x-y table executed a rapid
reposition and slammed the table into
Figure 1—
The 7524 was originally configured with the WR line being controlled by the ATmega8. Because nothing else is on the DAC data bus, I eliminated having to write
any WR pin strobe code. This freed up an ATmega8 I/O pin by tying both WR and CS to ground.
www.circuitcellar.com
CIRCUIT CELLAR
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Issue 148 November 2002
61
machine the motors are operating on,
the bottom line is that it all comes
down to simple step and direction
pulses applied to the motor drive.
BUILDING THE INTERFACE
Now that the motor driver hardware
and software are defined, let’s move
on to the process of integrating the PC
parallel ports, Geckodrive, and stepper
motors. To make this easy and repeat-
able, I’ll show you how to design an
interface PCB that will house all of the
interface electronics and provide con-
nection points for the parallel ports and
x-, y-, and z-axis Geckodrive modules.
As you can see in Figures 1 and 2,
each parallel port card under the con-
trol of Indexer LPT provides step, direc-
tion, reduced-current, all windings off,
low-limit switch, high-limit switch,
auxiliary-input, and signal ground.
Each parallel port can be broken down
into two axes. The axes are labeled A_B,
C_D, E_F, and G_H. Axes A and B are
the x- and y-axes, and G represents the
milling machine’s z-axis. The axes are
all relative to milling machine termi-
nology: the z-axis is the spindle axis
that moves vertically with positive
motion being downward, and the x-y
axes is defined as the milling machine
x-y table that moves horizontally.
It’s important to note that the h-
axis really isn’t defined as an axis in
the x-y-z sense. Indexer LPT allows
you to designate parallel port pins that
are normally used for step, direction,
and inputs for alternate purposes. In
this application, the y-axis (h-axis) is
used to drive the spindle and coolant
relays via a 74LS541 buffer and a
ULN2003 high-current driver.
Step and direction signals from the
A_B axis parallel port card are pulled
up by 10-k
Ω
resistors and buffered by
a 74LS541. The Geckodrive requires
that the device that drives the optoiso-
lated inputs be able to sink 16 mA.
The 74LS541 can sink 24 mA. In addi-
tion to buffering the step and direction
for axes A and B, IC4 also buffers the
spindle control pins originating at axis
connector G_H.
Another 74LS541 is used to provide
you with visual feedback. IC6 taps
into the step and direction signals
flowing out of IC4 and displays their
levels via a collection of LEDs. The
coolant control signal is also pinned
into IC6 and an LED.
There are times when you’ll want to
move the motors manually. Normally,
this is accomplished by adding an
external pulse-generating encoder for
each axis that can be rotated by hand.
IC7 and IC8 are quad two-input multi-
plexers with A and B inputs that are
selected by a SPDT switch connected
to each IC’s A/B select pin. Step and
direction outputs from IC4 are routed
to the A side of each multiplexer; the
manual encoder outputs are attached
to the B side. By simply flipping the
switch, you can choose between manu-
al and computer control of the motors.
Axes E and F (E_F) are configured to
service the push-button switches that
are mounted on the machine’s control
pendant or in a hand-held control box.
the Indexer LPT program has a func-
tion that allows two sets of four nor-
mally open switches to be scanned and
read. One side of each of the groups of
four push-button switches are tied
together and attached to pins 1 and 14
of the E_F port connector. The other
side of the switches each attach to the
anode of a steering diode (D2–D8).
Indexer LPT uses active-low logic.
Thus, a logical low is sequentially
applied to each set of the diode’s (i.e.,
D2–D8) cathodes from E_F pins 2 to
5. If a switch is closed, the low-logic
signal flows through the closed
switch to either pin 1 or pin 14 of the
E_F axis connector.
For example, assume that the
AXIS_SELECT switch is tied on its
common side to E_F pin 1, and the x-
switch’s common is tied to E_F pin 14.
If pin 5 of the E_F axis connector is
low and the AXIS_SELECT switch is
closed, a low will flow through D8,
through the AXIS_SELECT switch into
pin 1. If the x-switch were closed, the
low would be routed through D4 to
E_F pin 14. You must be careful with
the push buttons, because there is no
way to differentiate when both switch-
es on a diode pair are closed.
The Indexer LPT HAM is a dongle
that plugs directly into the C_D axis
parallel port. The 1-k
Ω
potentiometer
you see between pins 11 and 15 allows
you to manually override the Indexer
. Shipping and handling for the
Limited. NO COD. Prices subject
CHARGE ORDERS to Visa, Mastercard,
High-brightness blue LED. 1000 MCD.
Water-clear in off state. Special price.
62
Issue 148 November 2002
CIRCUIT CELLAR
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used immediately to generate a cur-
rent that’s transformed to voltage by
IC5, an LM358.
To provide the upper voltage level of
10 VDC, 12 VDC powers the LM358.
The 7524 is powered by 5 VDC to
allow TTL compatibility with the
ATmega8’s I/O port. An LM385-2.5
voltage reference is used to provide the
negative reference voltage for the DAC.
The output voltage for the DAC is
determined by the following formula:
[3]
where input_byte is the value applied
to the DAC’s 8-bit digital input port.
Doing the math for input_byte =
0xFF doesn’t even come close to out-
–
LPT feed rate settings. This is termed
feed rate override in machinist speak.
It’s included here as a requirement of
the operators at the shop where the
interface board will be installed.
We’re almost there. There’s only
one motor left on our milling
machine that has not been serviced.
The z-axis stepper motor is responsi-
ble for moving the spindle up and
down. To be able to mill, the spindle
must house a rotating bit.
An AC motor that’s controlled by a
voltage-controlled inverter drives the
bit. Applying a 0- to 10-VDC level to
the spindle speed controller controls
spindle rotation speed. The current
requirements of the spindle speed con-
troller input are small, and a standard
op-amp can be used to drive it.
Indexer LPT contains the function-
ality to output a series of pulses that
can be used to set the spindle speed.
The original idea behind this feature
was to supply you with selected num-
ber of pulses to some external logic
that converted the number of pulses
to a voltage and then drove the spindle
speed controller. Smells like a micro-
controller application to me.
IC1 is an Atmel ATmega8/16 run-
ning at 7.37 MHz. Its only purpose in
life is to count pulses from the Indexer
LPT program and convert them to an
8-bit number that’s placed on the I/O
pins of the ATmega8’s port D.
The port D pins are tied to the digi-
tal inputs of a 7524 DAC. The DAC’s
WR and CS lines are tied low to allow
the bits on its digital inputs to be
Figure 2—
Imagine doing all of this with point-to-point wiring. Well, the first time around, I did! Even though the interface board looks busy, there are plenty of unused pins that
could be controlled from the Indexer LPT program. If there isn't enough action for you, I've included some breadboard space on the interface board for your custom additions.
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CIRCUIT CELLAR
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63
putting the 10 VDC you need for max-
imum motor speed (i.e., 2.49 VDC and
some change). So, adding 33 k
Ω
to the
10-k
Ω
resistor behind the DAC’s RFB
pin provides a gain of four, which puts
you close to the 10-VDC target figure
(i.e., 9.96 VDC).
To avoid having to add voltage regu-
lators to the design, a regulated power
brick supplying 12, –12, and 5 VDC
will supply the interface card’s volt-
ages. It just so happens that those
voltages are also available from the PC
power supply. The completed interface
board is shown in Photo 3.
MORE GECKOS
Although this application was geared
toward retrofitting an milling machine,
the use of Geckodrives and the
Indexer LPT software is not limited to
machinists. In fact, you can even get a
Geckodrive module that drives DC ser-
vomotors. All you have to do is add an
encoder to your servodrive and employ
Photo 4—
Pictures of armatures replace pictures of
stepper motor windings on the casing of the Geckodrive
G320 servodrive. There are also pins on the G320 to
support an encoder. The G320 has made it easy and
affordable to use cheaper servodrives instead of rela-
tively expensive steppers in machine applications.
Fred Eady has more than 20 years of
experience as a systems engineer. He
has worked with computers and com-
munication systems large and small,
simple and complex. His forte is
embedded-systems design and com-
munications. Fred may be reached at
fred@edtp.com.
the services of a model
G320 Geckodrive mod-
ule (see Photo 4).
If you’re planning a
project that doesn’t
require the motor drive
sophistication of a
milling machine, there’s
no reason why you
couldn’t attach a small
microcontroller to the
step and direction
inputs of a Geckodrive
module and perform some small-scale
motion control applications. If you’re
new to motion control, having trou-
ble implementing a motion/motor
control application, or interested in
learning more about it, you should
visit the Geckodrive web site and
check out the motion control and
stepper motor white papers.
I
SOURCES
G Code Controller, Indexer LPT
Ability Systems Corp.
(215) 657-4338
www.abilitysystems.com
ULN2003 high-current driver
Allegro MicroSystems, Inc.
(508) 853-5000
www.allegromicro.com
ATmega8/16 Microcontroller
Atmel Corp.
(408) 441-0311
www.atmel.com
G210 Stepper motor driver, G320
servodrive
Geckodrive, Inc.
(714) 771-1662
www.geckodrive.com
Photo 3—
The axes on the board are connected via 25-pin shell connectors,
and all of the individual wiring is connected to the interface board with screw
terminals. The HAM is recessed to avoid having it knocked off accidentally.
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hances are
you’ve used an
ARM-based device
within the last week and
quite possibly the last hour. ARM
CPUs have been in PDAs since the
days of Newton. Currently, ARM is the
only supported processor architecture
for the latest version of Microsoft’s
PocketPC. And as I write this article,
it’s apparent that ARM chips will soon
be appearing in PalmOS devices, hav-
ing displaced the venerable 68K.
Most mobile phones use ARM cores
either in ASICs or standard CPUs.
They may be controlling your hard
disk, printer, or network switch.
ARMs were one of the root causes for
the transfer of the semiconductor divi-
sion of the last generation’s giant to
this generation’s giant. ARM processors
range from small, embedded microcon-
trollers all the way up to those intend-
ed for the multimedia market.
It’s clear that many industry leaders
have voted with their orders in favor of
ARM. There are reasonable options for
hobbyists and smaller players, too.
Many ARM chips are still available
with wires instead of balls (it’s hard to
believe that 1.0-mm pitch packages are
now the convenient option). Numerous
reasonably priced ARM evaluation
boards are available on the market. For
those of you who want to write soft-
ware for higher-end embedded ARM
processors but don’t have an evaluation
board, removing PocketPC from an
iPAQ is a reasonably priced option.
Compaq sponsored a successful open-
source project based on the idea that
embedded Linux is targeted for iPAQs.
ARM, Ltd. is an IP vendor that’s
licensing the architecture, processor
cores, and system cores. In addition,
ARM has its own development tools,
including an instruction set simulator
and JTAG in-circuit emulator.
TERMINOLOGY AND NOMENCLATURE
Discussing ARM products presents
you with many “secret handshake”
opportunities. In the ARM world, there
is a differentiation between the instruc-
tion set architecture, the basic core, and
the core including all of the embedded
macrocells. The terminology for these
items is similar enough to easily trip up
the product sales representatives. So,
knowing the secret handshake will
show you which FAEs are really knowl-
edgeable enough to help you.
When someone talks about the ARM
architecture version, they’re talking
about the instruction set. Most ARM
chips in embedded devices and current
designs are based on either the ARM
v4 or v4T architecture; however, the
most advanced ARM chips from both
ARM and Intel are based on the v5T
architecture, which is a superset of
the v4T architecture.
The “T” in the architecture’s name
means that the architecture in the chip
supports the 16-bit Thumb instruction
mode, which we’ll discuss later. There
is also an “E” variant of the v5 architec-
ture for DSP extensions. You can imple-
ment one architecture in multiple core
families. If you’re just using an ARM
processor in your design or an ARM
core in your ASIC, then you will only
care about the architecture version
when you’re poring through instruction
set manuals. Companies like the for-
mer Digital Semiconductor and Intel
are concerned with the architecture as
they implement their own core that is
compliant with a given architecture.
Discussions of architecture versions
will cause many engineers’ eyeballs to
ARMs to ARMs
c
Assimilating yourself to
the world of ARM can
be like moving to a
new country: it’s diffi-
cult if you’re not famil-
iar with the language
and landscape. But
with Robert as your
guide and translator,
you’re sure to gain the
confidence needed to
use the architecture in
your own projects.
Robert Martin
FEATURE
ARTICLE
Part 1: Welcome to the World of ARM
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provide a way to perform atomic reads
or writes of up to 15 32-bit words.
These advantages were enough for the
ARM designers to include the instruc-
tions and lose a level of RISC purity.
PROCESSOR MODES
An ARM processor has seven poten-
tial operating modes, including a stan-
dard user mode and six privileged
modes that are used to handle inter-
rupts, exceptions, or system tasks.
The privileged modes are: System,
Supervisor, Interrupt, Fast Interrupt,
Abort, and Undefined Instruction. All
of the privileged modes, with the
exception of System mode, have their
own stack pointer, link register, and
current status register. The System
mode uses User mode register set.
The Supervisor, Interrupt, Fast
Interrupt, Abort, and Undefined
Instruction modes are entered through
hardware or software exceptions.
Exceptions with their own mode and
registers minimize exception-handling
latency and reduce the problems of
nested exceptions. You only need to
save registers that you’re going to use
in your exception handler without con-
cern about the stack pointer, link regis-
ter, and SPSR. You must save these reg-
isters if you’re going to re-enable the
exception in your exception handler.
REGISTERS
The ARM architecture defines
37 registers. Of the 37 registers, 31 are
glaze over as they try to use an ARM
chip in a design. When the discussions
move to the core that’s used in the
chip, the glazed-look should disappear.
The core family is the actual imple-
mentation of the architecture. The
common core families from ARM are:
ARM7 Thumb, ARM9 Thumb, ARM9E
Thumb, and ARM10 Thumb. There are
also ARM core families from Intel: the
StrongARM (originally from Digital
Semi) and XScale Microarchitecture.
The core that you use determines
the maximum performance you’ll get
from the CPU. Different cores within
the same architecture version may have
different pipeline and data path struc-
tures. In addition, with the exception of
the few cores that can be synthesized,
ARM licenses the physical core. The
feature sizes and voltages available
were determined by ARM when the
core was initially implemented.
Having all of the SoCs with the same
ARM core and roughly the same core
CPU performance is beneficial for those
of us who consume the chips. The chip
manufacturers compete with each other
on peripheral sets in the microcon-
troller rather than with benchmark
numbers that are only meaningful to
the marketing department.
Most of the ARM chips on the mar-
ket use a CPU core that’s the combi-
nation of the basic core and embedded
macrocells that provide debug (D),
64-bit multiplication results (M), DSP
extensions (E), and in-circuit emulation
(I). The most common system cores are
the ARM7TDMI and ARM9TDMI
(recall that the “T” stands for Thumb
instruction mode).
You can combine a CPU core with
memory system units to create a sys-
tem core. These system cores are
licensed by ARM and identified by a
name that uses an extended core num-
ber. For example, the ARM720T core
contains separate instruction and data
caches, write buffers, and a memory
management unit. With a better memo-
ry hierarchy, it’s no surprise that CPUs
with system cores tend to perform bet-
ter than ones with only a CPU core.
FEATURES
With a few exceptions, the code for
ARM processors is written in a higher-
level language. Like all RISC machines,
the architecture is well suited to high-
er-level languages like C. So, why
should we discuss the architecture and
instruction set?
First, when writing or porting code to
a new embedded platform, you’ll need
assembly to do the initial start-up code,
to set up some of the on-chip periph-
erals, and to take advantage of archi-
tectural features like fast interrupts.
Second, many of you are bit pushers
who may appreciate some of the fea-
tures in the ARM instruction set.
That being said, I will limit the dis-
cussion of the architecture and instruc-
tion set to a quick overview, as well as
to those things that differentiate the
ARM from its competitors, in an effort
to reduce the risk of losing those of you
still reading this article. Note that
you’ll need to refer to ARM’s The ARM
Architecture Reference Manual
for the
actual instruction documentation.
Obviously, ARM processors are RISC
machines. The only interactions with
memory are to load or store registers.
Arithmetic, logic, and control instruc-
tions operate only on registers. To
accommodate this, a large general-pur-
pose register set is available. Unlike
other RISC processors, the ARM
instruction set has instructions that
take longer than one execution cycle.
The instructions to load or store multi-
ple registers may deviate from theoreti-
cal RISC design, but it does reduce code
space, improve data throughput, and
Register
APCS name
Use
Saving convention
r0
a1
Arg 1/integer result/scratch
Caller
r1
a2
Arg 2/scratch
Caller
r2
a3
Arg 3/scratch
Caller
r3
a4
Arg 4/scratch
Caller
r4
v1
Register variable 1
Callee
r5
v2
Register variable 2
Callee
r6
v3
Register variable 3
Callee
r7
v4
Register variable 4
Callee
r8
v5
Register variable 5
Callee
r9
sb/v6
Static base/register variable 6
No change/callee
r10
sl/v6
Stack limit/register variable 7
No change/callee
r11
fp
Frame pointer
r12
ip
Scratch/new sb in interlink-unit calls
r13
sp
Stack pointer
r14
lr
Link register/scratch
r15
pc
Program counter
Table 1—
The ARM procedure calling standard (APCS) defines how registers should be used. This standard is fol-
lowed by ARM higher-language compilers. Assembly language routines that interface with higher-level languages
must at least follow the convention for the caller or callee saving of the registers.
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CIRCUIT CELLAR
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Register r15 is the program counter,
and it must be treated differently than
the other 15 general-purpose registers.
Care must be exercised when writing
to the program counter, because this
will cause the processor to execute a
branch to the new address. To return
from a function call, you must move
the return address into the program
counter. The simplest way to do this
is to execute the mov pc, lr com-
mand, which will do a register-register
transfer of the return address in the
link register into the program counter.
If the link register was saved on the
stack as it entered into the function,
then the load multiple register com-
mand can be used. For example, if
you’re saving registers r4 through r6
on the stack along with the link regis-
ter using the stmfd sp!, {r4-r6,
lr} command, then executing:
ldmfd sp!, {r4-r6,pc}
will restore registers r4 through r6
and cause a branch back to the
return address.
ARM has defined the convention for
the usage of the registers in the ARM
procedure call standard (APCS). [1]
This convention sets the ground rules
for compiler writers and those of you
general-purpose registers and six are sta-
tus registers. Each program status regis-
ter (PSR) contains the current proces-
sor mode, interrupt and fast interrupt
enable flags, a Thumb mode flag, and
conditional flags. The flags—nega-
tive, zero, carry, and overflow—are
used for the conditional execution of
ARM instructions.
One of the PSRs, the current pro-
gram status register (CPSR), is used for
the current state of the processor. The
five exception processor modes each
have their own saved program status
register, or SPSR. These are referred to
as SPSR_mode.
When the processor is in a mode
other than User mode, the SPSR con-
tains the CPSR from when the proces-
sor left the previous mode. You need
to use the SPSR in some exception
handlers, especially if you are using a
Thumb-enabled processor.
The ARM architecture includes
31 32-bit-wide, general-purpose regis-
ters. At any time, only 15 general-
purpose registers, the program count-
er, and CPSR are visible. The first
eight registers, r0 to r7, are referred to
as unbanked registers. Registers r8
through r14 are referred to as banked
registers, because different registers
may be visible under the same name
in different processor modes.
All of the exception modes use a
banked r13 and r14 for the mode stack
pointer and link register. Only the FIQ
mode banks registers r8 through r12.
The banked registers for a given mode
are designated rN_mode. When in a
given mode, you’ll see the registers for
that mode without using the “_mode”
designation. The internals of the
processor use the _mode registers for
processor mode swapping.
writing assembly code that will inter-
face with higher-level languages.
Because the ARM instruction set is
meant to be used with higher-level
languages, all of the ARM assembly
language routines should at least fol-
low the convention for which registers
need to be saved by the callee rou-
tine. The register usage in APCS is
shown in Table 1.
The first four arguments in a func-
tion call are placed in registers a1 to
a4. APCS allows these registers to
change inside the called function. The
function caller should assume these
values are returned in an unpre-
dictable state. If the registers need to
be preserved, they should be pushed
onto the stack prior to the function
call. A single-word return value comes
back from the function in register a1.
The registers reserved for register
variables, v1–v5/v7, must not change
during a function call. The called
function must save these values prior
to use and restore them prior to
return. Because C compiler writers
follow this standard, this lets you
know the maximum number of opti-
mized variables in any section of code.
EXCEPTIONS
There are seven types of exceptions
for ARM processors: reset, interrupt,
fast interrupt, software interrupt, data
abort, prefetch abort, and undefined
instruction. When an exception condi-
tion occurs, the ARM hardware vec-
tors to a specific address for that
exception. The vector addresses are
listed in Table 2.
Because there is only one machine
word available for all exceptions apart
from fast interrupts, the instruction at
the vector address should be a jump to
the actual exception handler. The
Exception
Processor mode
Vector address
Reset
Supervisor
0x00000000
Undefined instruction
Undefined
0x00000004
Software interrupt
Supervisor
0x00000008
Prefetch abort
Abort
0x0000000C
Data abort
Abort
0x00000010
Interrupt
IRQ
0x00000018
Fast interrupt
FIQ
0x0000001C
Table 2—
When one of the seven ARM exceptions occurs, the processor switches into one of the privileged modes
and vectors to a well-known address. With the exception of the fast interrupts, the vector address for another
exception follows in the next word. For all non-FIQ exception handlers, the instruction in the vector address must
be a jump to the actual exception handler.
Exception
Priority
Banked registers
Link register
Return example
Reset
1
Undefined
Undefined
Undefined
Data abort
2
r13, r14, CPSR
Aborted instruction + 8
subs pc, r14, #8
Fast interrupt
3
r8–r14, CPSR
Next instruction + 4
subs pc, r14, #4
Normal interrupt
4
r13, r14, CPSR
Next instruction + 4
subs pc, r14, #4
Prefetch abort
5
r13, r14, CPSR
Aborted instruction + 8
subs pc, r14, #8
Undefined
6
r13, r14, CPSR
Next instruction
movs pc, r14
Software interrupt
6
r13, r14, CPSR
Next instruction
movs pc, r14
Table 3—
Take a look at the exception priorities, banked registers, and return mechanism for the seven ARM excep-
tions. The priority is used if there are multiple exceptions pending at the completion of an instruction. The undefined
exception and software interrupt are the same priority because they are mutually exclusive.
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exception to this is the fast interrupt.
As the highest exception vector, there
is no need for a jump, and there are
no restrictions on the FIQ handler
starting at address 0x0000001C.
When an exception occurs, the reg-
isters that will be banked for the new
mode are transferred to the appropri-
ate _mode register. Then, the CPSR is
copied into the exception mode’s
SPSR, normal interrupts are disabled,
and the program counter is set to the
exception vector.
If the exception is a reset or fast
interrupt, FIQ is also disabled.
Otherwise, the FIQ disable bit in the
CPSR is not modified. The instruction
pointed to by the banked link register
is determined by the exception type.
The link register for reset is undefined
because it doesn’t make any sense to
return from a processor reset. The link
registers stored for each exception are
listed in Table 3. To return from the
exceptions, special forms of the mov or
sub commands with an “
s“ suffix are
required to notify the processor that
the saved registers must be restored.
This is also shown in Table 3.
You can use a store multiple and
load multiple combination with a cou-
ple of modifications from what is done
to return from a function. First, you
must perform the appropriate subtrac-
tion on the link register prior to issuing
the Store Multiple command. Second,
you must add a ^ suffix to notify the
processor that a mode change must
occur. Listing 1 shows an example.
There are two separate interrupt
mechanisms: normal interrupts and
the fast interrupt. There can be multi-
ple sources of IRQs, but only one
source for the FIQ. As you can tell by
the name, fast interrupts are meant to
occur with a minimum of interrupt
handling time. The ARM architecture
helps this in three ways. First, the limi-
tation on only one source of the FIQ
exception removes the need for soft-
ware vectoring. Second, there is no
need for an additional jump, because
the FIQ handler is at the highest excep-
tion vector address. Third, the proces-
sor will bank registers r8–r14 on an FIQ
exception (see Table 3). This may pro-
vide enough working registers so that
stack operations are not necessary.
Normal IRQs can be caused by on-
chip peripherals or interrupt requests
external to the chip. Each implementa-
tion can handle multiplexing differ-
ently. Some implementations require
external hardware for interrupt multi-
plexing, while others provide internal
registers for this purpose. In general,
software vectoring is required for IRQs.
Even here there are potential differ-
ences between implementations. The
AT91 ARM7TDMI family implements
hardware IRQ vectoring through the
Advanced Interrupt Controller, which
is an on-chip peripheral.
The two abort exceptions are initiat-
ed by the memory system when an
instruction fetch, data load, or store is
requested from an invalid address.
These will normally occur in systems
with a memory management unit or
memory protection unit. The excep-
tion handler will generally resolve the
abort condition and then replay the
instruction that caused the abort. In a
system with an MMU, especially a vir-
tual memory system, the abort excep-
tion handlers will be used to appropri-
ately set up the MMU registers. The
breakpoint (BKPT) instruction in v5T
Listing 1—
When entering an exception handler, you must push the registers that you will use onto the
stack. When you use the store multiple register instruction for your working registers, the final register
pushed on the stack should be the link register. This allows you to use one instruction to restore your work-
ing registers and to perform a return. This listing shows you how to store r0–r6 for an IRQ handler.
sub
r14, r14, #4
//Set return address properly
stmfd sp!, {r0-r5,r14} //Store r0-r5 and return address on
the stack
;
;Execute main part of IRQ handler
;
ldmfd sp!, {r0-r5, pc}^
//Restore registers and return
//Note ^ for changing modes
for Instruments and Automation
• Data Acquisition
• AC& DC Solid State Relays
• Compact Flash Memory
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CIRCUIT CELLAR
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architecture is another way to gener-
ate a prefetch abort exception.
The software interrupt (SWI) is used
to provide User mode access to func-
tions that are only accessible to privi-
leged modes. The execution of the
swi <argument> command causes
the software interrupt exception. The
system will enter Supervisor mode to
service the request. The exception
handler uses the argument, which is
encoded in the instruction, to determine
the system function that’s being
requested. This argument is 24 bits if
the SWI instruction was executed in
ARM mode; it’s only 8 bits in Thumb
mode.
If you’re implementing a system that
will use Thumb instructions or that’s
set up for Thumb Interworking, you
should consider limiting the number of
system commands to 255. The excep-
tion handler will need to extract the
argument from the instruction prior to
the one pointed to by the link register.
The undefined instruction exception
occurs when an undefined opcode is
executed or a coprocessor doesn’t
accept a coprocessor command. This
exception can be used to expand the
ARM instruction set. It can be used,
for instance, in a system without a
coprocessor. The undefined instruction
exception handler would be used to
emulate coprocessor instructions.
To implement an undefined instruc-
tion handler, you have to decode the
instruction prior to the one pointed to
by the link register. Both the unde-
fined instruction and software inter-
rupt handlers require knowledge of
instruction machine code encoding.
The timing of the exception han-
dling depends on the individual
exceptions. When the reset input to
the processor is asserted, the proces-
sor immediately enters the reset state,
interrupting the current instruction.
The other one that’s probably of most
interest to you is the timing of FIQ
and IRQ exceptions. The state of the
interrupt inputs is checked at instruc-
tion boundaries. Individual instruc-
tions are not interrupted. This
means that load multiple, store mul-
tiple, and coprocessor transfer instruc-
tions can delay the processor recogni-
tion of an interrupt.
Robert Martin received a Ph.D. in
Physics from The College of William
and Mary. He’s been working with
embedded and real-time systems for
over 10 years. Currently, Robert is an
engineering manager directing a team
of embedded software engineers near
Phoenix, Arizona. You may reach him at
rmartin@sonoranfoothillseng.com.
REFERENCE
[1] ARM, Ltd., “The ARM-THUMB
Procedure Call Standard,” SWS
ESPC 0002 B-01, 2000.
RESOURCES
ARM, Ltd., ARM Architecture
Reference Manual
, DDI 0100E,
2000.
S. Furber, ARM System-On-Chip
Architecture,
2nd ed., Addison-
Wesley, Harlow, England, 2000.
SOURCES
ARM7 Thumb, ARM9 Thumb,
ARM9E Thumb, ARM10 Thumb
ARM, Ltd.
www.arm.com
AT91 ARM7TDMI family
Atmel Corp.
www.atmel.com
StrongARM, XScale
Intel Corp.
www.intel.com
For load multiple and store multiple
instructions, this is up to the time
required to read or write memory with
16 words or 512 bytes. The coprocessor
designer determines the maximum
number of bytes transferred by
coprocessor transfer instructions. For
this reason, ARM recommends that
coprocessor designer not transfer more
than 512 bytes in a single instruction.
WHAT’S NEXT?
In Part 2 of this series, I’ll explain
what I believe is the best reason for
using ARM in your embedded designs:
the ARM architectural features that
reduce the code size compared to other
RISC processors. In addition, I’ll intro-
duce you to the various CPU and sys-
tem cores, toolchains, and OSs that are
available in the market today.
I
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lthough Thomas
Edison lost the war
of DC versus AC
power distribution, he
clearly saw the light. The hours of
experimentation he spent on finding
the perfect filament has taken us out
of the dark ages, so to speak. I doubt
he realized just how many light
bulbs would be in use today. Is this
all about to change? Have you
noticed how the solid-state indicator
is rapidly replacing the filament
bulb? From traffic signals and brake
lights to flashlights and indicators,
solid-state photon production is so
much cooler than heating to the
point of incandescence.
Ever since the third brake light
became standard on automobiles, I’ve
been thinking about how automotive
lighting hasn’t kept pace with the rest
of automotive design. I believe that
although red is fine for brake lights, I
could be a better defensive driver if I
knew what the driver ahead of me was
thinking (doing). In addition to red as
a foot-on-the-brake indicator, I would
like to see green used for a foot-on-
the-gas indicator and yellow as a no-
action or running light. With this
approach, you would have a clearer
idea of the situation ahead.
But, I digress. The purpose of this
project is to simplify the lighting
arrangement of my ’87 Honda Shadow
and show how this type of design
might be used to improve the style and
safety of motorcycles (and automo-
biles). This is accomplished by the
design of a replacement solid-state
brake light, which can also eliminate
the need for left and right turn signal
lights. In preparation of the design, I
removed the brake light lens cover and
measured the inside dimensions of the
lens to come up with the size for a PCB
that would fit into the existing space.
SOLID-STATE PHOTON EMITTERS
I wanted to place a number of these
emitters within the available area on
one side of the PCB. Eight (or multi-
ples of eight) is a great number to use
when dealing with microcontrollers,
because ports are usually designed in
groups of eight I/Os. Eight rows of
eight columns would fit nicely but
would require eight ports (i.e., one I/O
for each emitter) to have control over
each. To reduce that requirement to
two ports, you have to multiplex the
array of emitters similarly to the way a
keypad is scanned. Because the current
through any device could be greater
than 50 mA (and maximum column
current is eight times that), most
micros can’t be used to drive the rows
or columns directly. External drivers
will be necessary, making it conven-
ient to run the emitters from the high-
er system 12-V battery (see Figure 1).
To achieve minimum height, I looked
for some SMT devices that emit a high-
intensity red output. As with all emit-
ters, there is a trade-off between milli-
candela (mcd) output and the viewing
angle. A wide viewing angle is at the
top of my wish list, so I needed to
select a device with a maximum output
based on a ~130° viewing angle. From
the catalogs and stock available, I chose
a Lite-On LTST-C150KRKT, which is a
clear red emitter that outputs approxi-
mately 80 mcd at 20 mA. This is a
1206-size SMT device (~0.12
″ × 0.06″),
so tweezers are a necessary tool.
The datasheet shows a maximum
continuous current of 30 mA, but a
peak current as high as 80 mA for a
duty cycle of 10%. The eight columns
Smart Auto Brake Light
Eliminates Turn Indicators
a
Small
engineer-
ing proj-
ects won’t
end world
hunger, but they can
make the roads a little
safer. This month, Jeff
gives you a good rea-
son to follow him
closely: he’s building
an animated solid-
state brake light.
Jeff Bachiochi
FROM THE
BENCH
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CIRCUIT CELLAR
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Issue 148 November 2002
71
sufficient overhead (in the series resis-
tors) to allow for additional series
emitters in each leg of the matrix.
for this project give a duty cycle a bit
longer than that (12.5%), so I’ll stay
lower than the 80 mA.
I used eight-channel source and sink
drivers to reduce the parts count. The
drivers are capable of 500 mA. That
current divided by eight channels is
62.5 mA per channel. Each driver has
no more than a 2-V collector-to-emitter
drop, as does the solid-state light emit-
ter. This means the series resistor will
drop about 6 V (12-V power supply –
source device drop – emitter drop – sink
device drop). The resistor then must be
6 V/62.5 mA, which equals about 100
Ω.
Power dissipation in the source and sink
drivers will be 2 V × 500 mA, which
equals 1 W. The maximum recommend-
ed power is 1.5 W of free air, so there is
a comfortable measure of safety.
PCB
Refer to Photo 1 to see both sides of
the PCB. On the front side you can
see the 64 SMT emitters and series
resistors laid out in a nice 8 × 8
matrix. On the backside (with the ICs)
you will see something that might be
of interest. Take a close look at the
DIP sockets. Notice that these are not
mounted as through-hole parts. The
socket pins are bent outward and an
SMT pad layout is used, which will
allow DIP sockets to be surface
mounted. This is done to eliminate
the need for through holes in the PCB,
which would surely interfere with the
SMT stuff on the front of the PCB. I
could have used SMT ICs here, but I
like the advantage of being able to
change parts easily, especially the
processor (even allowing an emulator
to be plugged into the prototype).
The PCB is double-sided; and as
such, about 50% of the surface area is
made up of interconnection traces. If I
had used a multilayer PCB, there
might have been room for three times
the number of emitters. Using the
system’s 12-V supply voltage there is
Figure 1—Source driver U2 and sink driver U3 supply the control signals to multiplex the 8 × 8 matrix of red emitters.
Photo 1—The topside of the PCB has 64 SMT red
photon emitters forming an 8 × 8 matrix. The bottom
side contains a microcontroller, source and sink driv-
ers, and a 5-V regulator.
inside the inner loop. It is scanned
every time the inner loop (column
enable) is cycled. If the program were
allowed to execute at full speed, then
the animation frames would be dis-
played so fast that they would be just
a blur. For this reason, a middle-loop
frametime
counter is used to add a
delay between each animation frame.
STATE MACHINE
There are four main states in this
application. The running state is the
idle branch in which the program will
spend most of its time. Occasionally,
the brakes or one of the turn signal
inputs will be enabled. The running
state sets the row value equal to an
entry in a one-dimensional array table
based on columncount. This lets the
columns have alternating patterns (e.g.,
10101010, 01010101…). The brake state
uses an always on value of 11111111,
which is always on for each column.
Both of these states have static displays.
Even though the animationframe
counter is still cycling, the row data is
always the same for each frame. When
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This would add three times the light
output without increasing the power
requirement at all.
ANIMATION
An alternating pattern of ons and
offs serves as running lights (see
Figure 2a). When the brakes are applied,
all of the emitters are turned on (see
Figure 2b). The left and right turn signal
lights require some animation. The ani-
mation is in the form of a moving
arrow (emitters on) in the direction of
the turn (see Figure 2c). Finally, if the
brakes are applied when the turn signal
is also on, then the moving animation
arrow is comprised of off emitters on a
background of on emitters. This nega-
tive animation has a much higher
photon output (see Figure 2d).
There are basically three loops nec-
essary for this application. An outer
loop continuously increments the ani-
mationframe
count from zero to
seven. This variable is responsible for
determining which of the left and
right animation frames should be
used. There are eight arrow animation
frames to a complete cycle. This
allows the cycle to repeat and look
like a continuous action.
The innermost loop increments the
columncount
counter from zero to
seven. This counter sets the column
enable on the column control port.
Only one of the eight columns is set to
logic 1 (current source) at any one time.
A state machine with look-up tables is
Photo 2—When my bike is idle, I measure a system
voltage of about 13.5 V with only about 0.5 V of noise,
which you can see in the background trace. In the
forefront, you can see alternator noise of about 1 V,
which shows up when cruising.
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CIRCUIT CELLAR
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Issue 148 November 2002
73
the left or right turn signal input steers
the state machine to the
setleft or
setright routines, the row (data)
value is taken from a 2-D array table
based on columncount and animation-
frame.
The
setleft and setright
routines use separate tables.
There is a sub-state that must be
taken into account. This sub-state
takes place when the left or right ani-
mation is cycling and the brake pedal
is applied. I solved the problem by test-
ing for the brake input right after grab-
bing the row data from one of the ani-
mation tables. If the brake is applied
then, the data is XOR’d with 0xFF.
This essentially creates a negative copy
of the animation. With turn animation
designed using about 25% of the emit-
ters, a negative animation displays the
same animation with 75% of the emit-
ters on. Note that this animation has
a considerably higher photon output.
MICRO CONNECTION
Five connections to the motorcycle
are needed for this project: brake, left
and right signals, power, and ground.
Actually, because the tail (running)
light is always on, it serves as the
power connection. In the tail light
assembly, the power, ground, and
brake signals are already available,
that just leaves finding and tapping
the left and right signals.
The brake, left, and right control
signals are the only inputs needed
and they come into Port A. Both
Port B and Port C are used as 8-bit
outputs, one for the row and one for
the column signals. Any micro with
at least 19 I/Os could be used.
I chose a PIC16C62 for its low cost
and support from PicBasic, the BASIC
compiler for PIC chips. Actually, I
used a PIC16F873 for development
because the flash memory can be
reprogrammed. Both are 28-pin
devices that are signal-compatible.
No peripherals or interrupts are need-
ed for this project (in fact, only 758
words out of 2K are used.) The code is
straightforward and required less than
an hour to write (including figuring
out the table data).
The two output ports connect direct-
ly to the source and sink drivers. I
selected these for their 5-V logic inter-
faces. The system’s 12-V power supply
is used for the source and sink sup-
plies. Whereas the processor operated
from a 5-V regulator, the three inputs
to the microprocessor should not be
subjected to the 12-V supply. Series
resistors limit the input current from
each of the three control inputs signals
to 5 mA, allowing the input diode to
clamp the input to 5 V (see Figure 3).
Photo 3—With a still photo, I can show you only a
single frame of the left turn signal animation. Note that
the complete eight-frame loop takes 1 s.
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ALTERNATOR NOISE
I was curious about how
clean (or noisy) the charg-
ing system was while the
bike was running, so I took
the time to look at the 12-V
power supply with an oscil-
loscope. When idle, the sys-
tem ran right around 13.5
V with a few small ripples
of what looked like less
than 0.5 V (see Photo 2).
At higher revolutions per
minute, I took a closer
look (see the inset of Photo
2). Although the spikes
totaled about 1 V at the
higher revolutions per
minute, most were low in
frequency and not going to
cause any problems. No
special filtering was used
to eliminate noise. The
processor required little
current, and the normal
capacitors on the regulator
were sufficient to ensure a
stable 5-V working voltage.
LIVE TEST
After the tedious work of
mounting the SMT compo-
nents on the front side and the
IC sockets to the rear side of
the PCB, I was ready to plug in
the driver ICs and the proces-
sor I had previously pro-
grammed. When I applied
power at my workbench, I
noticed one emitter wasn’t
functioning. At first I thought I
may have placed it backwards,
but a closer look (with a mag-
nifier) showed a small solder
bridge shorting out the emitter.
A quick retouch with an iron
removed the bridge, and things
were looking bright. A clip lead
from the power source to the
brake input immediately pro-
duced full brilliance.
Moving the clip lead to the
right turn signal input gave me
a surprise. An arrow was mov-
ing upward on the display. It
looked as though I laid out the
PCB with the columns and
rows reversed! But, everything
came out right after I quickly recalcu-
lated the table entries and repro-
grammed the processor. The turn sig-
nal inputs worked fine and the brake
reversed the image correctly. It was
time to mount the unit.
The first thing I did was to remove
the bulbs from the rear signal lights
and the taillight. I found the connec-
tor junction for the rear lights con-
veniently (yeah right) located under
the seat. Snaking the five twisted
wires from the PCB in the brake
light enclosure to the connector
junction was definitely a job for
someone more flexible than me. But
finally having made it, I prepared for
the first real test.
Next, I turned on the ignition and
the PCB lit with a pattern of every
other emitter on. It was perfect.
Holding the PCB in my hand and
playing around with the rear brake
lens, I found that the display was
most effective when mounted as
close to the lens as possible. So, I fas-
tened the PCB onto the lens, pushed
everything into the enclosure, and
screwed the lens back on.
Running
Brake
Off
Right turn
Animation frame 1
Animation frame 2
Animation frame 3
Animation frame 4
Animation frame 5 Animation frame 6
Animation frame 7
Animation frame 8
Right turn and brake
Animation frame 1 Animation frame 2
Animation frame 3
Animation frame 4
Animation frame 8
Animation frame 7
Animation frame 6
Animation frame 5
Figure 2a—The running mode displays a static pattern of 50% illumination. b—
Applying the brake pedal increases the illumination to 100%. c—A turn initiates
a repeating eight-frame animation cycle. d—Applying the brake during a turn
inverts the animation data.
a)
b)
c)
d)
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Then, I turned on the left turn sig-
nal switch. The animation began, but
was interrupted when the turn signal
relay alternated the signal on and off.
The animation began anew with each
cycle of power. This essentially dis-
played the same frame of animation
again and again. At this point, I
unscrewed the lens cover, removed
the PCB, and went back to the lab.
I considered my options. The
Yankee in me thought about remov-
ing the turn signal relay. The hard-
ware engineer started doodling an
RC time constant for the two signal
inputs. Then the software guy said,
“Put down your soldering iron. I can
do that with code.”
Instead of branching to the
setleft and setright routines on
the left and right input signals, I creat-
ed
leftsignal and rightsignal bit
variables for the job. In the inner loop,
I added a few lines to set and clear
the variables based on the left and
right input signals and a counter.
This keeps the variables on for
approximately 1 s after the left or
right input stops, essentially creating
a 1-s one-shot that can be triggered
again and again.
INTO THE SUNSET
After I mounted everything back
onto the bike, the newly altered pro-
gram performed perfectly (see Photo 3).
This is the part of the show when the
hero rides his steed onto the hilltop
and his faithful stallion stands on its
hindquarters pawing to keep his bal-
ance. The rider proudly gives a slow
wave and rides off into the sunset.
Although I like to keep both wheels
on the ground, I do occasionally wave
to a fellow rider.
I haven’t figured out how to play
MIDI through the pages of this maga-
zine just yet, so you’ll just have to
imagine some theme song playing in
the background as I ride away.
I
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CIRCUIT CELLAR
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Issue 148 November 2002
75
SOURCES
LTST-C150KRKT SMT Super Red
LED
Lite-On, Inc.
(408) 946-4873
www.liteon.com/opto.index.html
PIC16C62/16F873 MCUs
Microchip Technologies, Inc.
(480) 786-7200
www.microchip.com
PicBasic Compiler for PIC MCUs
microEngineering Labs, Inc.
(719) 520-5323
www.melabs.com
Jeff Bachiochi (pronounced BAH-key-
AH-key) has been writing for
Circuit
Cellar since 1988. His background
includes product design and manu-
facturing. He may be reached at
jeff.bachiochi@circuitcellar.com.
Figure 3—The power and control signals come in through JP1. Ports B and C are configured as output ports and
control the row and column data for the photon emitter matrix.
To download the code, go to
ftp.circuitcellar.com/pub/Circuit_
Cellar/2002/148/.
76
Issue 148 November 2002
CIRCUIT CELLAR
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eaders with kids
are no doubt famil-
iar with the “How
time flies” phenomenon.
From one day to the next, there seems
to be little change; but then, seeming-
ly all of a sudden, the little tyke you
used to bounce on your knee is bor-
rowing your jacket and asking for the
keys to the car.
I’m getting that same “How time
flies” feeling as I review my notes
from the Sensors Expo in San Jose.
Maybe it’s because I only get to the
Expo every couple of years when it
happens to alight in my neck of the
woods; or it could be that the effect is
accentuated by the high-tech panache
that rubs off on the Silicon Valley edi-
tion of the conference.
Was there any dramatic difference
from my last visit? No, nor between
that Expo and the one before it.
Nevertheless, today’s version is hardly
recognizable as the same conference I
covered back in ’94 (Circuit Cellar 49).
Teach your kids the ABCs, and next
thing you know they’re reading
Shakespeare. Well, all of a sudden sen-
sors are getting really smart too. Sure,
you can still find a 4- to 20-mA cur-
rent loop or two, but you’re just as
Sensors and Sensibility
r
Tom Cantrell
At the
2002
Sensors
Expo,
Tom saw
the determination of
designers to create
innovative, sensible
sensor technology.
This month, Tom
explains where sensor
technology has been
and where it’s going.
SILICON
UPDATE
likely to find a “field bus” (i.e., LAN
in sensor speak) of some sort shipping
ones and zeros around.
Although there were still plenty of
booths with big iron, silicon has
increasingly become the material of
choice. These days, you’re just as like-
ly to find familiar embedded micro
suppliers like Microchip, Cygnal, TI,
and Parallax, as you are the old-school
“controls” outfits.
Way back when, data acquisition
and control systems were specialized
and expensive pieces of equipment.
But in more recent years, we’ve seen
computing technology sprawl beyond
the border of the desktop and MIS
department. These days, talk around
the water cooler in the shop or lab is
more likely to be about PCs than PLCs.
There’s no better illustration of this
than National Instruments. Twenty
years ago when the PC hit the scene,
NI was comprised of a few guys barely
able to afford to move out of a garage
on the revenues from their GPIB board
for DOS computers. Today, NI is a
$400-million powerhouse with almost
3000 employees scattered in 37 coun-
tries. Hey, where’s my jacket?
GROOVY GADGETS
If today’s data-acquisition gear
revolves around a PC, tomorrow’s may
piggyback on a PDA. At least that’s
the vision of Silicon Valley’s own
Santa Clara-based Datastick Systems.
Their DAS-1245 turns the ubiquitous
Palm Pilot into a data logger featur-
ing four channels of 0- to 5-V 12-bit
analog-to-digital conversion and one
TTL-compatible digital input (see
Photo 1). High-impedance (1 M
Ω)
inputs facilitate the connection of
typical analog sensors without the
need for external buffering.
Powered by either a pair of on-board
AAA alkaline batteries or an external
power supply, the DAS-1245 module
piggybacks on most Palm m-series
handhelds. Sampling rates of up to
400 Hz (single channel) are possible
with options for real-time display
and/or storing results for later PC
downloading and post-processing.
Other software options include four
different viewing modes (i.e., numeric,
bar chart, line graph, and dial) and pro-
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Networking,” was presented by
Peter L. Fuhr, Associate
Professor of Electrical
Engineering at San Jose State
University.
Let me say that if you think
networking in the computer
and communications world is
chaotic, the situation on the
factory floor is even more con-
fused. In fact, it’s the worst of
both worlds, with a bewildering
variety of standard and propri-
etary factory-centric field buses
(e.g., CAN and Modbus) competing
with hard-hat versions of commercial
standards like Ethernet.
There’s even been talk of using
Bluetooth for sensors networks. Not
so fast. Professor Fuhr’s presentation
described a demonstration at a prior
Sensors Expo of a Bluetooth-based
sensor network that, because of the
complexity and bloat of the protocol
and requisite silicon, suffered rapid
battery depletion.
…IT’S THE HUMIDITY
Like temperature sensors, different
varieties of humidity sensors—resis-
tive, capacitive, and thermal—are
available to best meet the needs of a
particular application. Accuracy,
range, response time, interchangeabili-
ty, and environmental requirements
are all factors that determine the
proper choice. [1]
Another consideration is the partic-
ular version of humidity you’re trying
to measure. Unlike temperature,
which is simply a matter of degrees,
there are at least half a dozen ways to
grammable compensation for a
particular sensor’s nonlinear
response curve.
So what’s next, data acquisi-
tion for cell-phones? Pagers?
GameBoy? I’m not joking, so you
shouldn’t be laughing.
Parallax is another company
known for its clever designs. Over
the years, they’ve expanded on
their BASIC Stamp roots with a
variety of educational and applica-
tion initiatives. OPTAscope,
which is a PC-based two-channel
digital storage oscilloscope (DSO), is
the latest example of their “small is
beautiful” (and affordable) philosophy
in action (see Photo 2).
Make no mistake: OPTAscope won’t
replace your HP or Tektronix gear, nor
will it take the place of higher-perform-
ance PC-based DSOs (e.g., the 100 mil-
lion samples per second DSO-2102
from Link Instruments). The raw sam-
ple rate for OPTAscope is only one mil-
lion samples per second, but that’s cut
in half for the simultaneous sampling
of both channels and derated further
by oversampling. Realistically, the
OPTAscope is limited to a 100- to 200-
kHz bandwidth, which is acceptable for
observing audio or debugging software-
driven I/O such as a bit-banged UART.
Otherwise, this little cutie delivers
the goods with industrial-class fea-
tures: programmable trigger (i.e., ris-
ing, falling, and threshold); automatic
measurements (i.e., minimum, maxi-
mum, peak, mean, and RMS); pan and
zoom; and so on.
I especially like the fact the
OPTAscope USB interface not only
provides the needed bandwidth and
no-hassle installation, but also powers
the scope (i.e., no separate power sup-
ply is required). Best of all, at only
$179.99, the OPTAscope makes digi-
tal debugging affordable for hobbyists,
students, and educators.
IT’S NOT THE HEAT…
Even though it’s easy to spend all of
your time at the Expo checking out
the goodies on the exhibit floor, you
should try to save some time for the
conference sessions. Yes, some of
them are pretty esoteric or target the
manufacturers of sensor technology,
but there are also plenty of opportuni-
ties for users, including newcomers, to
get up to speed.
For instance, Ron Desmarais of
Airpax led a session titled “Selecting
and Using Temperature Sensors,”
which proved to be a welcome refresher
on this basic subject. Ron started by
classifying the most common types of
contact temperature sensors: thermo-
couples, thermistors, RTDs, and semi-
conductors. This is helpful info if
you’re not sure which is most appropri-
ate for what type of applications.
Ron highlighted the golden rule that
applies to any temperature sensor you
choose: “The only temperature that a
temperature sensor ever measures is
its own temperature.”
This means that care must be taken
in terms of mounting and environ-
mental considerations. It may seem
obvious, but I suspect this is a golden
rule that, like 55 mph on the highway,
is all too easy to overlook.
I’m reminded of a house I used to live
in where the thermostat was mounted
in the front entryway. Yes, that was
convenient, but it was dumb. Open the
door on a cold winter day for even just
a few moments, and voila, the furnace
would kick on, never mind that the rest
of the house was already toasty.
I suppose this rule is kind of the
sensor equivalent of the old “garbage
in, garbage out” maxim that computer
types know well. It certainly doesn’t
make sense to fret over the fractional
degree accuracy of a temp sensor, only
to (mis)use it in a way that means the
result is off by 10°.
Another thought-provoking session,
“A Review of Wired and Wireless
Communications for Sensor
100
90
80
70
60
50
40
30
20
10
0
0
5
10
15
20
After 1 minute immersion in water sensor
recovers to 30 ±2%, V
air
= 1 cm/s
RH (%)
Recovery times (minutes)
Figure 1—When shopping for humidity sensors, make sure the one you
choose can tolerate immersion if there’s any chance of it getting dunked.
0-13
mV
Sensor
Difference in resistance
of thermistors is directly
proportional to absolute
humidity.
Ambient air
thermistor
Dry nitrogen
sealed thermistor
+
–
Output
Figure 2—A thermal transfer humidity sensor works by
comparing the heat transfer characteristics of a sample
against a dry reference.
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comes to silicon, the collective wis-
dom of creative designers always
seems to blast through the limits of
conventional wisdom.
For example, consider the Magic
Labs Conjure Wand, which is based on
the micro-machined accelerometer
from MEMSIC (see Photo 3). According
to the Magic Labs web site, “The wand
is operated by moving it in a specific
sequence of motions, called a Spell. If a
particular Spell is performed properly,
the Wand then generates a beautiful
interactive display of lights.”
Maybe they’ll sell a zillion of them,
or maybe not, but it’s this kind of
imaginative design that makes me
believe the MEMS-based sensor story
is far from over.
As well, innovation continues on
the MEMS front despite a purported,
and presumably short-lived, fab over-
capacity situation. In “EFAB—A New
Technology for Micro-Manufacturing,”
Chris Bang of MEMGen Corp. report-
ed on his company’s novel MEMS
manufacturing approach.
express humidity, everything from
water vapor pressure to water activity
to wet-bulb temperature. However,
the three most common and familiar
are relative humidity, absolute humid-
ity, and dew point.
Relative humidity, which is the ratio
of the moisture content of air compared
to the saturated level at the same tem-
perature and pressure, is probably the
most familiar to the average person. It’s
the number to blame in the dog days of
summer when the slightest activity
causes you to break into a sweat.
In the old days, the expansion and
contraction of a silk thread or human
hair in response to changes in RH
simply drove a mechanical gauge.
Similarly, dew point—the temperature
at which a gas begins to condense—
was traditionally handled in a low-
tech way by chilling a mirror until it
began to fog.
These days, resistive and capacitive
humidity sensors deliver decently
accurate results at a far lower cost. One
spec to watch out for is the ability to
tolerate and recover from condensation
and even immersion, which can perma-
nently affect (requiring recalibration) or
ruin the sensor (see Figure 1).
Absolute humidity is simply the
mass of water vapor in a given volume
of gas, commonly expressed as grams
per cubic meter. It can be calculated
from known RH, temperature, and
pressure. More recently, thermal con-
ductivity sensors have emerged that
use the relative heat dissipation from
wet (i.e., vented) and dry (i.e., sealed)
resistors to measure absolute humidi-
ty directly (see Figure 2).
MEMS THE WORD
Microelectronic mechanical struc-
tures (MEMS) are often perceived in
terms of our science fiction-like aspi-
rations. You know, little Roto Rooter
robots that travel through your arter-
ies scraping away the detritus of a fast
food lifestyle. Or, how about silicon
creepy-crawlies that scour your win-
dows, depositing the grunge into neat
little piles on the sill for a quick pass
with the vacuum?
The truth is, MEMS are a fact, not
fiction, especially in the world of sen-
sors. Notably, the technology, driven
by automotive designers who never
met a chip they didn’t love, has found
widespread use in accelerometers (e.g.,
air bags and much more) and pressure
sensors (e.g., engine controls).
Indeed, in her update, “It's Raining
MEMS—Five-Year Forecast Calls for
Nice, Steady Showers,” Marlene
Bourne, a senior analyst at In-Stat/
MDR, said: “Every major market has
now embraced the technology,” and
worldwide revenues for MEMS are
forecast to grow from $3.9 billion in
2001 to $9.6 billion in 2006.
In fact, Bourne reckons that the mar-
ket for MEMS-based sensors is already
mature, and much of the expected
growth will be in non-sensor applica-
tions. For example, MEMS are the great
silicon hope when it comes to RF (i.e.,
small size, low insertion loss, and high
isolation) and optical (i.e., micro-mirror
projectors and fiber optics) applications.
However, I wouldn’t be so quick to
say that the party is over for MEMS in
sensor applications. The one thing I’ve
learned over the years is that when it
Programmable
current source
Four input analog MUX
12-bit A/D
converter
External/Internal
analog reference
+
–
Uncommitted
op-amp
Two digitally
controlled
switches
Two digital
potentiometers
RS-485/422
Differential
UART
Clock
control unit
Power-on
reset
circuitry
I
2
Bus
interface
SPI Port
MAC
and
barrel
shifter
Two external
interrupts
32 I/Os,
interrupt on
port change
three timers
two compare
and capture
256 × 8
and
1 k × 8
SRAM
56 K × 8
Flash
memory
Two serial
ports
Debug
port of
choice
8051
mircoprocessor
single cycle
Four PWM D/As
XTAL
Figure 3—Goal Semiconductor is the latest to join the ’51 fray with a line of parts including the VERSA MIX.
www.circuitcellar.com
CIRCUIT CELLAR
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Issue 148 November 2002
79
Traditional MEMS manufacturing
techniques rely on conventional pho-
tolithography techniques (i.e., the
masking and etching of each layer in
turn). Although well understood, it’s
an expensive, tedious, and error-
prone process.
By contrast, EFAB uses an approach
perhaps best described as stenciling to
electro-deposit layers of combined
structural and sacrificial material (e.g.,
nickel and copper respectively) with a
single etching stage as the final step.
The EFAB story is all about fast and
easy MEMS production. Their tools
automatically generate the stencils
(MEMGen calls them “Instant
Masks”) from standard 3-D mechani-
cal CAD files. Experimental devices,
such as the inductor shown in Photo
4, with up to 25 layers can be fabricat-
ed in as little as three days.
’51 FLAVORS
Work towards making sensors ever
smarter continues apace. Generally
speaking, that involves supplementing
a raw sensor with signal conditioning,
a processor, and a digital interface.
Corporate grass-is-greener machina-
tions fuel the race. Witness the quick
move into mixed signal by Microchip
with their acquisition of TelCom
Semiconductor even as the linear pow-
erhouse Maxim buys their way into
the MCU biz by purchasing Dallas
Semiconductor and that company’s
line of enhanced 8051 controllers.
Speaking of ’51s, the old warhorse is
making notable headway in the sensor-
centric niche. Maybe it’s the de facto
“openness” of that venerable design,
the only multi-sourced 8-bit MCU
architecture, or maybe it’s the fact that
the ’51 is simply a familiar face to most
designers and perceived to offer the
least barriers in terms of tools and
awareness. For whatever reason, sensor-
oriented ’51s seem to be proliferating
like the flavors in the ice cream shop.
Most designers are familiar with
the big guns in the ’51 business like
Philips and Atmel. Meanwhile,
Circuit Cellar
readers like you have
been introduced to the sensor-centric
Photo 1—The Datastick DAS-1245 turns a Palm Pilot
into a four-channel data acquisition system.
Photo 2—Barely larger than a pack of cards and
priced at less than $200, the OPTAscope makes digital
debugging portable and affordable.
Shown Here: BS2 Carrier Board, Motor Mind C, 2 Easy Roller Wheel Kits
Up to 4.0A Current 10-24VDC Motors
Controls 1 or 2 Motors 40 Pin DIP Package
80
Issue 148 November 2002
CIRCUIT CELLAR
®
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offerings from newer players such as
Cygnal Semiconductor and Analog
Devices (see Photo 5).
But did you know that TI is in the
’51 business? À la Maxim and
Microchip, the seemingly strange fel-
lowship traces it’s roots back to TI’s
acquisition of Burr-Brown.
The MSC1210 starts with a sped-up
’51 core (i.e., four clocks per instruc-
tion versus the original’s increasingly
dated 12 clocks per instruction) run-
ning at up to 33 MHz at 5 V (18 MHz
at 3 V) and comes in four versions
with 4, 8, 16, and 32 KB of flash mem-
ory respectively.
As an aside, I applaud the trend for
manufacturers to catch up with the
reality of embedded product life cycles
by specifying longer data retention
time for their flash memory (100 years
for the MSC1210). You can only hope
that the meager 10-year specs for earli-
er flash MCUs were conservative, or it
won’t be long before these first-genera-
tion gadgets start losing their minds!
The most notable feature of the
MSC1210 is on the analog side of the
chip, where TI joins Analog Devices
(whose microconverter is also based
on the ’51) by upping the ante with
an ultra-precise 24-bit ADC. Now, a
24-bit ADC is quite something, even
as a standalone device. All the more
challenging and impressive to contem-
plate combining such a delicate and
precise converter on the same chip as
a noisy high-speed MCU, something
akin to trying to hold a poetry reading
at a heavy metal concert.
Nevertheless, the ’1210 pulls it off
with a combination of eight channels
(single-ended or differential), a pro-
grammable gain amp (PGA) with a
gain of one to 128 times, precision
on-chip voltage reference (0.2% accu-
racy, 5 ppm per degree C drift), and
built-in offset and gain calibration.
Goal Semiconductor is a Canadian
design house that’s also got their hand
in the mixed-signal MCU fray. The
five parts in their current lineup com-
bine hopped-up ’51 cores with a vari-
ety of add-ons covering the analog-
digital spectrum.
The preliminary specs for the
VERSA MIX are intriguing. A single-
cycle ’51 core coupled with a 32-bit
MAC unit and barrel shifter are the
brains; and novel I/O features such as
RS-485/422 transceiver, digital poten-
tiometers, a spare op-amp, and a pro-
grammable current source, are the
brawn (see Figure 3).
VERSA HV100 and HV300 are
notable for their high voltage and cur-
rent capability, with eight open-drain
drivers that can withstand up to 100-
and 300-V inputs, respectively, and
sink up to 100 mA. And as it’s name
implies, VERSA DSP presumes to pig-
gyback an entire DSP instruction set
onto the ’51 to go along with a built-in,
four-channel, 50-KHz, 16-bit ADC.
DOLLARS AND SENSE
Despite the overall gloom and doom
in the high-tech arena, I was glad to
see business almost as usual at the
Sensors Expo. The embedded biz sol-
diers on with real companies making
real products that earn real money.
Photo 4—The E-FAB process from MEMGen proves
you don’t need fancy IC gear or a clean room to
micromachine 3-D components, such as this 200-µm
tall, eight-turn inductor.
Photo 3—A micromachined accelerometer from MEM-
SIC puts the magic in this wand from Magic Labs.
82
Issue 148 November 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
REFERENCE
[1] D. K. Roveti, “Choosing a
Humidity Sensor,” Sensors,
July 2001.
SOURCES
’51-based MCU
Cygnal Integrated Products, Inc.
(512) 327-7088
www.cygnal.com
DAS-1245 PDA data acquisition
add-on
Datastick Systems, Inc.
www.datastick.com
VERSA ’51-based MCUs
Goal Semiconductor, Inc.
(800) 943-4625
www.goalsemi.com
DSO-2102 PC-based oscilloscopes
Link Instruments, Inc.
(973) 808-8990
www.linkins4.com
EFAB MEMS foundry
MEMGen Corp.
(818) 295-3996
www.memgen.com
The Conjure Wand
Magic Labs
www.magic-lab.com
Thermal accelerometer
MEMSIC, Inc.
(978) 738-0900
www.memsic.com
OPTAscope
Parallax, Inc.
(888) 512-1024
www.parallaxinc.com
MSC1210 ’51-based MCUs
Texas Instruments, Inc.
(800) 336-5236
www.ti.com
Photo 5—This Cygnal ’51-based MCU packs a lot of
punch in a very tiny package—3 x 3 mm, or barely
more than 0.1" on a side.
Tom Cantrell has been working on
chip, board, and systems design and
marketing for several years. You may
reach him by e-mail at tom.cantrell@
circuitcellar.com.
RESOURCES
National Instruments Corp., PC-
based data acquisition,
www.ni.com.
Sensors Expo and Conference,
www.sensorsexpo.com.
Some of you may laugh at applica-
tions like the Conjure Wand, but
remember the hula-hoop? At least
they’re actually making a magic
wand, rather than just trying to wave
one over a bogus balance sheet.
Without data to process, an embed-
ded processor is just a silicon paper-
weight. Novel sensor technology
will deliver the real-world data that
drives tomorrow’s real-world applica-
tions. Some will be serious, some
will be whimsical, but they will all
make sense.
I
CadSoft Computer, Inc., 801 S. Federal Highway, Delray Beach, FL 33483
Hotline (561) 274-8355, Fax (561) 274-8218, E-Mail : info@cadsoftusa.com
Schematic Capture • Board Layout
Pay the difference for Upgrades
You can use EAGLE Light for testing and
SMD pads can be rounded or round
Different pad shapes for Top, Bottom,
or Inner layers
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Insert-ready sub-mini SBCs (small as 47x55 mm.) supporting the
Philips
achieved via GND circuitry, 6 to 8 layer PCB, by-
32 KB to 8 MB external SRAM & Flash (controller-dependent)
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Interface Keypads, Switches, or RS-232 to your PC Keyboard Input
Up to 12 x 12 matrix Programmable RS-232 Port Macro Capability
The KE24 is the ultimate in flexibility. Inputs or serial data can
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The KE18 combines a multitude of features with small size at an
economical price. Custom units available.
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• 128 KByte Read & Write FIFO’s
• FIFO Style Interface to FPGA
• Xilinx XC2S200 or Altera EP1K30.
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Driver Software & API Included:
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• C/C++ Functions to Control 24 I/O Bits
• 24 I/O Pins Available from FPGA
• LED's, Switches, Numeric Display
• Connectors to Attach Custom PCB’s
• Documentation & Sample Apps.
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Quad Bench Power Supply
Interfacing with Frequency Synthesizers
ARMs to ARMs—Part 2
Wireless Data Acquisition Using Bluetooth—World Without Wires
Vector-SoC—A 1-GHz Vectorial Network Analyzer
Robotics Corner: A Low-Power Photoflash
Above the Ground Plane: Far Front Panels
I Applied PCs: A Wireless Temperature Sensor Stew
I From the Bench: Don’t Put All Your Eggs in One Basket—Smart RF
I Silicon Update: Hot Chips, Cold Sweat
Preview of December Issue 149
Theme: Wireless Communication
94
Issue 148 November 2002
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INDEX
85
Abacom Technologies
84
Abia Technology
85
ActiveWire, Inc.
61
All Electronics Corp.
83
Allied Component Works
85
Amazon Electronics
8
Amulet Technologies
92
AP Circuits
90
Appspec Computer Tech. Corp.
88
Atlantic Quality Design, Inc.
7
Atmel
90
Avocet Systems, Inc.
86
Bagotronix, Inc.
17,84
Basic Micro
90
Bellin Dynamic Systems, Inc.
82
CadSoft Computer, Inc.
85,95
CCS-Custom Computer Services
91
Cermetek Microelectronics Inc.
88
Concept Circuit Design
92
Conitec
11
Connecticut mircoComputer, Inc.
68
Copeland Electronics
9
Cyberguys
91
Cyberpak Co.
55
Cypress MicroSystems
C4
Dataman Programmers, Inc.
90
DataRescue
84
Decade Engineering
87
Delcom Engineering
74
DesignCon 2003
87
Designtech Engineering Co.
86
Digital Products
The Advertiser’s Index with links to their web sites is located at www.circuitcellar.com under the current issue.
Page
1
Earth Computer Technologies
80
ECD (Electronic Controls Design)
85
EE Tools
(Electronic Engineering Tools)
11
EMAC, Inc.
88
ePROTOS.com
50
ESC Boston
91
EVB Plus
80
ExpressPCB
84
FDI-Future Designs, Inc.
84
Hagstrom Electronics
72
HI-TECH Software, LLC
91
HVW Technologies Inc.
73
ICOP Technology Inc.
87
IMAGEcraft
91,92
Intec Automation, Inc.
90
Intronics, Inc.
69
Intuitive Circuits, LLC
10
Jameco
32
JK microsystems, Inc.
47
JR Kerr Automation & Engineering
69
LabJack Corp.
90
LabMetric
69
Lakeview Research
81
Lemos International
2
Link Instruments
93
Lynxmotion, Inc.
42
MaxStream
89
MCC (Micro Computer Control)
36
Microchip
15
Microchip Design Contest
90
Microcross
89
Micro Digital Inc.
92
microEngineering Labs, Inc.
84
MicroSystems Development, Inc.
18
Mid-Atlantic System Consultants, Inc.
87
MJS Consulting
68
Mosaic Industries Inc.
31
Motorola
34
MVS
93
Mylydia Inc.
33
NetBurner
87
OKW Electronics, Inc.
86
Ontrak Control Systems
47
PCB123
C2
Parallax, Inc.
86
Paradigm Systems
83
Phytec America LLC
83
Phyton, Inc.
91
Picofab Inc.
86
Pioneer Hill Software
90
Prairie Digital, Inc.
89
Pulsar, Inc.
83
QKITS.COM
89
R2 Controls
41
R4 Systems Inc.
66
Rabbit Semiconductor
40
Remote Processing
40
RF Digital
89
RLC Enterprises, Inc.
88
RPA Electronics Design, LLC
92
Rutex
5
Saelig Company
88
Scidyne
3
Scott Edwards Electronics Inc.
Page
Page
Page
ADVERTISER’S
21
SeaFire Micros, Inc.
88
Sealevel Systems Inc.
85
Senix Corp.
84
Sensory, Inc.
83
Signum Systems
86
Softools
16,79
Solutions Cubed
92
Spectrum Engineering
83
Square 1 Electronics
86
SUMBOX Pty Ltd.
63
Systronix
85
TALtech Instrumental Software
C3
Tech Tools
89
Techniprise Inc.
56,57
Technologic Systems
91
Technological Arts
88
Tern Inc.
23
Texas Instruments
90
Triangle Research Int’l Inc.
36
Trilogy Design
68
Vantec
86
Vesta Technology
93
Weeder Technologies
91
Xeltek
93
Xilor Inc.
87
Z-World
47
Zagros Robotics
91
Zanthic Technologies Inc.
January Issue 150
Deadlines
Space Close: Nov.11
Material Due Date: Nov. 18
Theme:
Embedded Applications
A
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ver sit and muse about the future of computing? I can’t speak for you, but as someone involved at the beginning of this revolution
I’ve still never been very good at predicting the future. I’m sure it’s the myopic nature of being hardware guys that makes us temper
every design idea with the practicality of whether or not the hardware exists to actually build it. Software guys have the advantage of living
in a fantasy world where the ideas reign and where concerns about computing power are satisfied by the guiding rule of, “It will come.”
The revolution we’ve experienced so far has increased communication and computing performance primarily at the individual level. The processor on your desk
today is 100 times more powerful than the one you had a few years ago. And, aside from the constant struggle of, “what Intel giveth, Microsoft taketh away,” we are
constantly increasing our individual productivity.
Until now our ability to exercise computing activities like video editing, photo manipulation, stock analysis, etc. has been bounded by the limits of our own PCs.
In order to do bigger and better things, we have to constantly invest in bigger and better machines. This fact isn’t lost on Dell, HP, and other PC manufacturers as
they promote a never-ending upgrade market.
As you know, the greatest factor driving individual computer usage today is the Internet. However, the primary purpose of the Internet is directing message traf-
fic from one place to another. It is not organized nor does it teach you how to share computing power or share technical assets like a CAT scanner or particle
accelerator connected to it.
Unfortunately, the software guys have been thinking outside the box again and attempting to alter conventional wisdom. The latest concept is called the “grid.”
In it’s simplest abstraction you can think of the grid like the power generation system used in our country. Many independent utilities push or pull power in and out
of this massive interconnected system. They might have incompatible generating techniques (wind, coal, gas, geothermal, etc.), but they speak a common lan-
guage in the shared benefit of –60-Hz AC power.
The idea of the grid has been around for a while, but used mostly by academics looking for less costly ways to analyze data than with a supercomputer. A sim-
ple version of this idea is to spread out a task among hundreds of computers across the Internet and poll each for results later. While this is probably better thought
of as distributed processing, it still leads us closer to the grid.
The first users of real grid computing have been the large corporations that need lots of computing power, most notably the car companies. Statistics show that
the average business server runs at only 30% of capacity and the 2-gig P4 on your desk is barely pushing 5%. The logical solution is to divert all of the excess
power of idle computers toward running complex applications, formerly the exclusive dominion of supercomputers. As you might expect, the next thought on the
minds of people producing grid-system software is to link companies, consumers, governments, and institutions. Together, all of this becomes one big grid engine.
The concept is wonderful, don’t get me wrong. It’s the operation of it that scares me. Today we have this wonderful communication system called the Internet and
what do we spend half our life doing? Getting rid of spam and protecting ourselves from hackers and viruses. While the predictions are rosy, if history is the exam-
ple, I doubt my 95% surplus will be utilized for anything I’ll be happy about. And, although computer makers say that future processors will allow us to retain individ-
ual privacy, these are the same people who have been caught with their hands in the cookie jar a few times about secret tags, embedded serial numbers, and
undisclosed tracks.
Our present computing strategy is built around using firewalls and strategic interception to keep unwelcome people out. For the grid to be truly beneficial, every
computer has to be in virtual contact with everyone else. This is achievable within a company computing system where they maintain a perfect environment of
hardware commonality and network access, but it’s a tough integration in the chaotic computing world outside.
My predictions of the power and the predicament of the grid will undoubtedly pale by comparison to what really happens. A lot of grid power will be consumed,
keeping the grid itself secure, but processing power will continue to expand as well. What we call supercomputers today may in fact be run-of-the-mill PCs tomor-
row. If I had to prognosticate, I’d say that because of its sheer ubiquity, ultimately the grid will pervade our lives almost like another intelligence. But, as most things
universal, we’ll also end up taking it for granted. Like flipping a light switch today, we’re not going to care how it works, but rather just that the light goes on.
As Long as the Light Goes On
INTERRUPT
e
steve.ciarcia@circuitcellar.com
96
Issue 148 November 2002
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