Ai Overclock Tuner: Auto, Manual, and XMP. Auto runs the board at default (optimal) settings with no overclock, Manual allow the user to set each individual overclocking parameter and XMP instructs the board to attempt to set CPU and MCH parameters as necessary in order to configure the system to operate the memory as defined by one of the memory's pre-programmed eXtreme Memory Profiles.
eXtreme Memory Profile, or XMP, is Intel's version of the same experience offered by NVIDIA's EPP (Enhanced Performance Profile), in which memory overclocking settings - including frequency, timings, and voltages - are programmed into the memory module's SPD chip. Assuming the CPU is capable of supporting the profile, selecting either Profile #1 or Profile #2 (as they exist) gives the user an easy way to experience overclocking without getting too involved in the setup process.
After selecting Manual the following options become available for change:
CPU Ratio Control: Auto and Manual. Selecting Manual allows for altering the CPU's operating multiplier. Leaving this set to Auto instructs the BIOS to use the CPU's default multiplier, or in the case of XMP operation, to select a multiplier that would most closely maintain the default CPU frequency when automatically overclocking the memory.
CPU Ratio Setting: Available options range from 6 to the installed CPU's default multiplier (in the case of the Q6600 this would be 9). Extreme-series CPUs (QX6850, QX9650, etc.) are also upwards unlocked and can be set as high as 31x.
FSB Strap to Northbridge: Auto, 200, 266, 333, and 400. There once was a time when this single setting controlled a whole series of MCH performance configuration registers. Implemented in its current form, this option does little more than determine what memory dividers are available for use. Lower straps can impose early front side bus (FSB) limitations - if you experience problems, choose the next higher strap and select the appropriate divider to keep your memory frequency at an achievable target. The general practice when overclocking is to keep the strap as low as possible after setting an acceptable CPU and memory speed. The P5E3 seems to break this wisdom and often performs best using the 333 strap regardless of FSB speeds.
Memory Divider Ratios Available by FSB Strap (DRAM:FSB) |
|
200 |
5:3, 2:1 |
266 |
5:4, 3:2, 2:1 |
333 |
1:1, 6:5, 8:5, 2:1 |
400 |
1:1. 4:3, 3:2, 2:1 |
FSB Frequency: This value, when multiplied by the CPU Ratio Setting, sets the processor frequency. For example, 400 FSB x 9 = 3.6GHz. This setting, along with the FSB Strap to Northbridge, influences what DRAM Frequency(s) are available for selection. (Most 65nm quad-cores are FSB limited by this board to around 480-500MHz without serious tweaking and voltages.)
PCI-E Frequency: Set no higher than 115-118MHz and you may see a small increase in 3D game/benchmark performance. Exceeding this recommendation will cause problems with the Southbridge to Northbridge DMI interface making it appear as though attached peripherals, including hard disk drives, have failed.
DRAM Frequency: Choose from those listed to set the system DDR memory frequency. Altering the FSB Frequency or FSB Strap to Northbridge settings will influence the selections available. Refer to the table above when targeting a specific memory speed. For example, if the 333 strap is selected with an FSB setting of 400 then the list would contain the following selection choices: 2 x 400 FSB x 1/1 = DDR-800, 2 x 400 FSB x 6/5 = DDR-960, 2 x 400 FSB x 8/5 = DDR-1280, and 2 x 400 FSB x 2/1 = DDR-1600.
DRAM Command Rate: Auto, 1T, and 2T. Incorrectly labeled as 1T and 2T, these settings are really 1N and 2N, as implemented by the Intel X38 MCH. Auto allows the BIOS to assign the value automatically based on FSB Strap to Northbridge and final memory frequency. In most cases, system stability is not affected and a 3-5% improvement in memory bandwidth boost is available when set to 1N.
DRAM Timing Control: Auto and Manual. Auto allows the BIOS to read and set all primary and secondary timings for the installed memory as detailed by SPD. Manual gives the user control over individual memory timings while allowing the option of having some timings remain automatically assigned based on programmed values. In most cases the only timings that need to be manually configured are: CAS# Latency (tCL), RAS# to CAS# Delay (tRCD), RAS# PRE Time (tRP) and RAS# ACT Time (tRAS) - leave all others sub-timings set to Auto unless you have a good reason for changing them.
DRAM Static Read Control: Auto, Enabled, and Disabled. We were unable to affect any measurable performance change because of toggling this setting. This setting is curious by its very nature as Ai Transaction Booster (explained below) manipulates the MCH Static Read Control Delay setting directly, implying there would be no reason for this option.
DRAM Dynamic Write Control: Auto, Enabled, and Disabled. See above.
Ai Clock Twister: Auto, Light, Moderate, and Strong. This setting controls the number of memory access phases that are "pulled-in" to the next lower (higher performance) Static Read Delay value. In essence, this allows for smaller, incremental performance gains if the user is unable to achieve stability when using the next lower Static Read Delay value.
Ai Clock Skew for Channel A/B: This setting allows you to either advance or delay the signal timings for Channel A or Channel B DIMMs. Because it's not possible to locate all memory modules an equal distance from the MCH, it's important to be able to adjust signal timing to ensure all data (or requests for data) arrive at the same point at precisely the same time. When experimenting with this setting either slightly delay Channel A (since it's closer to the MCH) or advance Channel B - do not change both simultaneously unless you find you need more than 350ps (picoseconds) of total skew (highly unlikely).
Ai Transaction Booster: Auto, Enabled (Boost: 1-8), and Disabled (Relax: 1-8). This is probably one of the most important BIOS settings when it comes to extracting every possible bit of performance from the system. Setting these fields can improve total memory bandwidth up to 15% and produce a considerable reduction in access latency.
Static Read Control Delay, sometimes referred to as Performance Level, is a primary MCH "timing" value and has a rather significant impact on memory read performance as well as overall memory access latency. In case you are wondering why low access latency matters, we submit to you the following quick-and-dirty response: improved memory latency (courtesy of the Integrated Memory Controller/IMC) is the primary reason that AMD Athlon 64 chips have performed so well. Latency is one of the few areas where AMD maintains a lead over Intel, and Intel will move to an IMC design late next year (starting with Nehalem).
Much like primary memory timings, this MCH "timing" is measured in clock cycles and is relative to the base transmission frequency (2 x FSB). This explains why Static Read Control Delay should increase as FSB rates rise. Similar to memory timings, maintaining a lower value longer with the proper application of MCH voltage can lead to improved performance. In other words, "boosting" the Ai Transaction level may require a higher MCH voltage than would be otherwise required if a more relaxed level were set.
Because these settings effectively apply an offset to the default value it can sometimes be difficult to confirm exactly what is going on - it is almost like flying blind. Thankfully, a wonderful tool exists that reads and reports "Performance Level" from within Windows, allowing us to verify that the board is operating as intended. Memset 3.4 (beta 3), available as freeware, can be found through a simple search using your favorite search engine. Here we see Performance Level, as reported by Memset 3.4, as well as Command Rate and memory latency from EVEREST 4.20.
Auto allows the BIOS to set the values automatically which, through simple experimentation and observation, has been simplified to the following relationship: Static Read Control Delay (default) = tCL. Knowing this makes adjusting the value rather simple. Keep in mind that workable values are in the range of 1-3 (boost or relax) only; selecting values from 4 through 8 will always result in a POST failure.
For example, with memory set to DDR-1600 6-6-6-15, the BIOS will establish a default Static Read Control Delay of 6. Setting Ai Transaction Booster to Enabled with a Boost Level of 1 results in a final Static Read Control Delay setting of 6 - 1 = 5. Alternatively, selecting Disabled with a Relax Level of 1 results in a final value of 6 + 1 = 7. Just like in the case of memory timings, lower is tighter (higher performance).
Finally, a simple rule to keep in mind when setting Static Read Control Delay - 4 requires a CAS Latency (tCL) of 6 or lower, 5 requires a tCL of 7 or lower, and 6 requires a tCL of 8 or lower. There are no other known limitations at this time.
CPU Voltage: Maximum of 1.7000V. Our experience with the ASUS P5E3 Deluxe has shown a rather large voltage offset when it comes to VCore. For example, setting 1.4675V in the BIOS results in an in-Windows idle voltage of ~1.4250V by DMM. Under load we see the voltage settle out as low as 1.39V. While we understand the need and requirement for VDroop, a total difference in programmed BIOS voltage to full-load voltage of more than 0.07V is excessive. Keep this in mind when setting this value if you already know the minimum voltage your CPU needs for stable operation or utilize the load-line calibration setting listed below to reduce VDroop.
CPU PLL Voltage: Maximum of 2.78V. Out of all the voltages the user can manipulate this one is by far the most dangerous. Maximum vCPUpll, as established by Intel, is 1.60V (default for this board) making 2.78V a whopping ~75% over specification! (As an aside, this would be the equivalent of subjecting your 65nm CPU to a core voltage of over 2.5V). Exercise extreme caution when utilizing higher values as setting this value too high can result in the CPUs "losing cores" after being subjected to voltage in excess of ~2.0V. The good news is that we did not see an increase in overclocking potential with voltages above 1.68V.
FSB Termination Voltage: Maximum of 1.50V. Undeniably the Achilles' heel of this fine board, 1.5V (VTT) is simply not enough to carry most 65nm quad-cores above ~500MHz FSB. Most CPUs/MCHs require this voltage to quickly ramp up from the default (1.20V) to near maximum when overclocking from about 450MHz FSB and higher.
DRAM Voltage: Maximum of 2.78V. Base DDR3 voltages are set to 1.5V with most performance kits requiring somewhere between 1.8V and 1.95V. Our recommendation is never to exceed the manufacturer's maximum specified voltage. With that said, values in excess of ~2.2V with DDR3 are a death sentence. In light of this, allowing a voltage as high as 2.78V seems irresponsible but is a required marketing feature.
NB Voltage: Maximum of 1.91V. NB Voltage, also known as VMCH, is an integral part of high-FSB overclocking, especially when running a "boosted" Ai Transaction Booster level. Maximum FSB achieved with a 65nm quad-core was around ~1.75V VMCH. Voltages above 1.75V, being excessive, will more than likely accelerate the failure of your board and cause unneeded heating of the MCH die.
Certain instabilities arose when running Northbridge voltages in excess of ~1.75V, caused by high internal die temperatures because of the voltage. Simply lowering VMCH was enough to return to stable operation. We've also found that the X38 chipset is far more sensitive to heat than any other Intel chipset to date. In fact, the BIOS is kind enough to warn the inexperienced user that Northbridge voltages in excess of 1.75V require a more effective cooling solution as the stock heatsink and heatpipe assembly can only do so much.
SB Voltage: Maximum of 1.20V. Some users have claimed that a higher Southbridge voltage provides for additional stability when running the PCI-E frequency out of specification. We have found leaving this voltage on Auto as the most appropriate solution, even when overclocking.
Clock Over-Charging Voltage: Maximum of 1.00V. Phase change, dry ice (DI) and liquid nitrogen (LN2) benchers may find higher settings here useful when cooling the CPU and surrounding area down to very low levels. All others would do best to leave this on Auto.
Load-Line Calibration: Acts to reduce the affects of VDroop during periods of heavy CPU loading. Enabling Load-Line Calibration may allow you to set a lower CPU Voltage in the BIOS while retaining overall system stability.
CPU/NB GTL Voltage Reference: CPU: Auto, 0.63x, 0.61x, 0.59x, and 0.57x. NB: Auto, 0.67x, and 0.61x. CPU Gunning Transceiver Logic (GTL) voltages are nothing more than reference levels that the CPU uses when determining if a data or address signal is either high (1) or low (0). Precision voltage dividers generate these voltages and are usually specified as a percentage of VTT. In the case of 0.67, this would be 67% of VTT. For example, if VTT is 1.20v then a CPU GTL Voltage Reference of 0.67x would result in a GTLREF value of 0.67 x 1.20V = ~0.80V.
These reference values are particularly important when overclocking quad-core CPUs, especially when venturing above about 450FSB. The ability to tune these values per die can mean the difference between 475FSB and 500FSB. Unfortunately, ASUS' implementation of this functionality is rather incomplete as manipulation of only a single GTLREF value is possible (and in a somewhat imprecise manner). The real power in GTLREF tuning comes in the ability to provide each quad-core die with separate reference values. (Recall that current quad-cores are an MCM consisting of two dual-core dies on a single package.) Unfortunately, this is not a matter of future BIOS modification as providing two distinct voltages to separate pins on the CPU would require nothing less than a PCB revision. As such, this board will most likely never see its full potential when clocking quad-core CPUs but it still performs admirably.
This same information applies to the NB GTL Voltage Reference setting except that there is no need for more than one reference value. In the case of each, we would like to see much finer control of these values. Ironically, the board's controllable voltages that need the least amount of precision seem to have the most. However, ASUS is working on these requests for their next boards; in the meantime, unless you push the board past about 98% of its maximum, these shortcomings will not affect the typical user of this board. We might add that other manufacturers face the same problem.
CPU/PCIE Spread Spectrum: Set both to Disabled for a more stable clocking signal.