Analogowe układy CMOS
Analogowe układy CMOS
Analogowe układy CMOS
Analogowe układy CMOS
w VLSI
w VLSI
w VLSI
w VLSI
w technice VL
w technice VL
w technice VL
w technice VL
W.Kucewicz Analogowe układy CMOS w technice VLSI 1
Analogowe układy CMOS
Analogowe układy CMOS
Analogowe układy CMOS
Analogowe układy CMOS
w VLSI - p
w VLSI - p
w VLSI - p
w VLSI - p
w technice VL part II
w technice VL part II
w technice VL part II
w technice VL part II
El t ni s Hist
El t ni s Hist
El t ni s Hist
El t ni s Hist
Electronics History
Electronics History
Electronics History
Electronics History
& Progress
& Progress
& Progress
& Progress
g
g
g
g
W.Kucewicz Analogowe układy CMOS w technice VLSI 2
Contents
Contents
Contents
Contents
1 Transistor Story
1 Transistor Story
1 Transistor Story
1 Transistor Story
1. Transistor Story
1. Transistor Story
1. Transistor Story
1. Transistor Story
2 Pro ress in the
2 Pro ress in the
2 Pro ress in the
2 Pro ress in the
2. Progress in the
2. Progress in the
2. Progress in the
2. Progress in the
VLSI P d ti
VLSI P d ti
VLSI P d ti
VLSI P d ti
VLSI Production
VLSI Production
VLSI Production
VLSI Production
W.Kucewicz Analogowe układy CMOS w technice VLSI 3
Transistor story
Transistor story
Transistor story
Transistor story
Transistor story
Transistor story
Transistor story
Transistor story
W.Kucewicz Analogowe układy CMOS w technice VLSI 4
Electron D y 98
Electron D y 98
Electron D y 9
Electron D y 9
EDiscovery - 189
EDiscovery - 1898
EDiscovery - 189
EDiscovery - 1898
"To the electron - may it never be of any use to anybody."
"To the electron - may it never be of any use to anybody."
- JJ. Thomson's favorite toast
- JJ. Thomson's favorite toast
W.Kucewicz Analogowe układy CMOS w technice VLSI 5
Electron D y 98
Electron D y 98
Electron D y 9
Electron D y 9
EDiscovery - 189
EDiscovery - 1898
EDiscovery - 189
EDiscovery - 1898
"To the electron - may it never be of any use to anybody."
"To the electron - may it never be of any use to anybody."
- JJ. Thomson's favorite toast
- JJ. Thomson's favorite toast
9
9
9
9
1 Elektron 1,6 10 C
1 Elektron 1 6 10 C
1 Elektron 1 6 10 C
1 Elektron 1 6 10 C
1 Elektron 1 6 �10-19 C
1 Elektron 1,6 �10-19 C
1 Elektron 1,6 �10-19 C
1 Elektron 1,6 �10-19 C
1 Elektron 9,1�10-31 kg
1 Elektron 91 10 kg
1 Elektron 91 10 kg
1 Elektron 91 10 kg
1 Elektron 91 10 kg
1 Elektron 9,1�10-31 kg
1 Elektron 9,1�10-31 kg
1 Elektron 9,1�10-31 kg
1 Elektron 511 keV/c2
1 Elektron 511 keV/c2
1 Elektron 511 keV/c2
1 Elektron 511 keV/c2
W.Kucewicz Analogowe układy CMOS w technice VLSI 6
Mechanical Computer
Mechanical Computer
Mechanical Computer
Mechanical Computer
Mmpu
Mmpu
Mmpu
Mmpu
The Babbage Engine, developed in 1834, was
perceived as a general-purpose computing
perceived as a general purpose computing
machine, with features strikingly close to
modern computers. Besides executing the
basic operations (addition, subtraction,
basic operations (addition, subtraction,
multiplication, and division) in arbitrary
sequences, the machine operated in a two-
cycle sequence, called  store and  mill
yq,
(execute), similar to current computers.
Unfortunately, the complexity and the cost of
yp y
the designs made the concept impractical.
For instance, the design of Difference Engine
I (part of which is shown) required 25,000
25,000
mechanical parts at a total cost of Ł17,470
mechanical parts at a total cost of Ł17,470
hl l f Ł
hl l f Ł
(in 1834!).
(in 1834!).
Babbage Difference Engine
Babbage Difference Engine
W.Kucewicz Analogowe układy CMOS w technice VLSI 7
1945 - Fmpu ENIAC
1945 - Fmpu ENIAC
1945 - Fmpu ENIAC
1945 - Fmpu ENIAC
9 First Computer  EN
9 First Computer  EN
9 First Computer  EN
9 First Computer  EN
ENIAC - Electronic Numerical Integrator Analyzer and Computer
ENIAC - Electronic Numerical Integrator Analyzer and Computer
Filling up a 30 X 50 foot room, ENIAC was made of 17, 468 vacuum
Filling up a 30 X 50 foot room, ENIAC was made of 17, 468 vacuum
tubes,70,000 resistors, and 10,000 capacitors -- not to mention all
tubes,70,000 resistors, and 10,000 capacitors -- not to mention all
those lights and switches Most importantly the metal giant could
those lights and switches Most importantly the metal giant could
those lights and switches. Most importantly, the metal giant could
those lights and switches. Most importantly, the metal giant could
add 5,000 numbers in a single second.
add 5,000 numbers in a single second.
W.Kucewicz Analogowe układy CMOS w technice VLSI 8
Bipolar transistor history
Bipolar transistor history
Bipolar transistor history
Bipolar transistor history
py
py
py
py
Ohl develops pn junction (Bell Lab)
Ohl develops pn junction (Bell Lab)
Ohl develops pn junction (Bell Lab)
Ohl develops pn junction (Bell Lab)
1940
1940
1940
1940
1940
1940
1940
1940
Established Shockley s Lab (Bell Lab)
Established Shockley s Lab (Bell Lab)
1945
1945
1945
1945
1945
1945
1945
1945
Bardeen and Brattain invent
Bardeen and Brattain invent
Bardeen and Brattain invent
Bardeen and Brattain invent
1947
1947
1947
1947
1947
1947
1947
1947
transistor (Bell Lab)
transistor (Bell Lab)
W.Kucewicz Analogowe układy CMOS w technice VLSI 9
Bipolar transistor history
Bipolar transistor history
Bipolar transistor history
Bipolar transistor history
py
py
py
py
The transistor was invented in 1947 at Bell Labs by the team of John Bardeen, Walter
The transistor was invented in 1947 at Bell Labs by the team of John Bardeen, Walter
Brattain, and William Shockley, for which they received the Nobel Prize (1956).
Brattain, and William Shockley, for which they received the Nobel Prize (1956).
The first transistor was about half an inch high
The first transistor was about half an inch high.
W.Kucewicz Analogowe układy CMOS w technice VLSI 10
Bipolar Transistor H y
Bipolar Transistor H y
Bipolar Transistor H y
Bipolar Transistor H y
pHistory
pHistory
pHistory
pHistory
The first transistor was a germanium point-contact
The first transistor was a germanium point-contact
The first transistor was a germanium point contact
The first transistor was a germanium point contact
transistor consisting of two thin electrodes in point-
transistor consisting of two thin electrodes in point-
contact with the surface of a piece of germanium and
contact with the surface of a piece of germanium and
with a third wire attached to the base.
with a third wire attached to the base.
B h d l f ld f l h
Brattain attached a single strip of gold foil over the
point of a plastic triangle. With a razor blade, he sliced
through the gold right at the tip of the triangle. Voila:
two gold contacts just a hair-width apart
two gold contacts just a hair width apart.
The whole triangle was then held over a crystal of
germanium on a spring, so that the contacts lightly
touched the surface. When a bit of current came
through one of the gold contacts, another even
h h f h ld h
stronger current came out the other contact.
Emitter Collector
Emitter Collector
Ge
Ge
Base
Base
W.Kucewicz Analogowe układy CMOS w technice VLSI 11
Bipolar Transistor H y
Bipolar Transistor H y
Bipolar Transistor H y
Bipolar Transistor H y
pHistory
pHistory
pHistory
pHistory
J. Bardeen and W. H. Brattain. The transistor, a semiconductor triode.
Physical Review, 74:230, July 15 1948
Transient Resistor
Transient Resistor
Transient Resistor
Transient Resistor
Ti
Ti
Transistor
Transistor
W.Kucewicz Analogowe układy CMOS w technice VLSI 12
Bipolar transistor
Bipolar transistor
Bipolar transistor
Bipolar transistor
p
p
p
p
License price 25 k$
License price 25 k$
W.Kucewicz Analogowe układy CMOS w technice VLSI 13
Bipolar Ju 951
Bipolar Ju 951
Bipolar Ju 9
Bipolar Ju 9
pJunction Transistor - 19
pJunction Transistor - 1951
pJunction Transistor - 19
pJunction Transistor - 1951
Emitter
Emitter
n
n
Base
Base
p
p
n
n
Collector
Collector
Shockley develops junction transistor which can be
Shockley develops junction transistor which can be
maufactured in quantity
maufactured in quantity
W.Kucewicz Analogowe układy CMOS w technice VLSI 14
1958: Invention of the Integrated
1958: Invention of the Integrated
1958: Invention of the Integrated
1958: Invention of the Integrated
Circuit
Circuit
Circuit
Circuit
u
u
u
u
Jack Kilby from Texas Instruments.
Jack Kilby from Texas Instruments.
N b l P i i 2000
N b l P i in 2000
Nobel Price in 2000
Nobel Price i 2000
1 Transistor and 4 other Devices on 1 Chip
1 Transistor and 4 other Devices on 1 Chip
The reason integrated chips are possible
The reason integrated chips are possible
at all is because engineers learned ways to
at all is because engineers learned ways to
build layers, making millions of transistors
build layers, making millions of transistors
build layers, making millions of transistors
build layers, making millions of transistors
across the chip all at the same time.
across the chip all at the same time.
W.Kucewicz Analogowe układy CMOS w technice VLSI 15
1958: Invention of the Integrated
1958: Invention of the Integrated
1958: Invention of the Integrated
1958: Invention of the Integrated
Circuit
Circuit
Circuit
Circuit
u
u
u
u
Kilby s notebook pages -summer 1958, Texas Instruments
Integrated circuit patent
Integrated circuit patent
Integrated circuit patent
Integrated circuit patent
W.Kucewicz Analogowe układy CMOS w technice VLSI 16
1953: Dg
1953: Dg
1953: Dg
1953: Dg
9 Darlington Patent
9 Darlington Patent
9 Darlington Patent
9 Darlington Patent
 Just after the transistor was invented at Bell Labs, Sidney
checked out for the weekend two of the few existing
transistors from the head of Bell Labs. Transistors were
not generally available and the head of the Labs kept the
few that had been made in his desk. Sidney played with
them at home on the weekend and discovered/invented
the Darlington pair. He realized that they could be put
th Dar ngt n pa r. H r a z that th y c u put
in one package ( on one chip ), and that in fact any
number of transistors could be put in one package. The
next week he was encouraged to have the lawyers draw
up the patent application. He said it should be written
He said it should be written
for any number in one package but the lawyers only
for any number in one package but the lawyers only
for any number in one package, but the lawyers only
for any number in one package, but the lawyers only
wanted to do it for two which is what was applied for.
wanted to do it for two which is what was applied for.
As it turned out, if it had not been restricted to two
As it turned out, if it had not been restricted to two
transistors, Bell Labs and Dr. Darlington would receive a
transistors, Bell Labs and Dr. Darlington would receive a
royalty on every IC chip made today!
royalty on every IC chip made today! Anyway, that s
the story he tells.
h h ll 
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: FUNDAMENTAL
THEORY AND APPLICATIONS, VOL. 46, NO. 1, JANUARY 1999
Darlington s Contributions to Transistor Circuit Design
D id A H d Fellow, IEEE
David A. Hodges, F ll IEEE
W.Kucewicz Analogowe układy CMOS w technice VLSI 17
Invention of the Integrated Circuit
Invention of the Integrated Circuit
Invention of the Integrated Circuit
Invention of the Integrated Circuit
fg u
fg u
fg u
fg u
Robert Noyce get his PhD at MIT where  few
Robert Noyce get his PhD at MIT where  few
peaple had even heardabout the transistor
peaple had even heardabout the transistor
peaple had even heardabout the transistor
peaple had even heardabout the transistor
1953
1953
1953
1953
1953
1953
1953
1953
He arriving to Shockley s Lab
He arriving to Shockley s Lab
1955
1955
1955
1955
1955
1955
1955
1955
He left Shockley s and forms Fairchild
He left Shockley s and forms Fairchild
Semiconductor with Jean Hoerni and Gordon
Semiconductor with Jean Hoerni and Gordon
Semiconductor with Jean Hoerni and Gordon
Semiconductor with Jean Hoerni and Gordon
1957
1957
1957
1957
1957
1957
1957
1957
Moore
Moore
H i i ts t h i f diff si impurities
H i i ts t h i for diffusion impurities
Hoerni invents technique for diff si i iti s
Hoerni invents technique f diffusion i iti s
into Silicon to build planar transistor and then
into Silicon to build planar transistor and then
1958
1958
1958
1958
using SiO2 as insulator
using SiO2 as insulator
Noyce develops first true IC using planar
Noyce develops first true IC using planar
transistor, diode-isolated silicon resistor, SiO2
transistor, diode-isolated silicon resistor, SiO2
1959
1959
1959
1959
1959
1959
1959
1959
insulation and evaporated metal wiring
insulation and evaporated metal wiring
W.Kucewicz Analogowe układy CMOS w technice VLSI 18
1959: Invention of the Integrated
1959: Invention of the Integrated
1959: Invention of the Integrated
1959: Invention of the Integrated
Circuit
Circuit
Circuit
Circuit
u
u
u
u
Noyce develops first true IC
Noyce develops first true IC
Noyce develops first true IC
Noyce develops first true IC
N y p f u
N y p f u
N y p f u
N y p f u
using
using
using
using
" planar transistor,
" planar transistor,
" planar transistor,
" planar transistor,
planar transistor,
planar transistor,
planar transistor,
planar transistor,
" diode-isolated silicon resistor,
" diode-isolated silicon resistor,
" diode-isolated silicon resistor,
" diode-isolated silicon resistor,
" SiO2 insulation
" SiO2 insulation
" SiO2 insulation
" SiO2 insulation
" and evaporated metal wiring
" and evaporated metal wiring
" and evaporated metal wiring
" and evaporated metal wiring
W.Kucewicz Analogowe układy CMOS w technice VLSI 19
First Commercial Planar IC 1961
First Commercial Planar IC 1961
First Commercial Planar IC 1961
First Commercial Planar IC 1961
Fairchild 
Fairchild 
Dual flip-flop Chip
Dual flip-flop Chip
4 Transistors and 5
4 Transistors and 5
4 Transistors and 5
4 Transistors and 5
Resistors
Resistors
START OF SMALL SCALE
START OF SMALL SCALE
INTEGRATION
INTEGRATION
INTEGRATION
INTEGRATION
TECHNOLOGY
TECHNOLOGY
W.Kucewicz Analogowe układy CMOS w technice VLSI 20
First Linear IC
First Linear IC
First Linear IC
First Linear IC
Fairchild
Fairchild
1964
1964
1964
1964
First Linear IC The źA 702 OPAMP
First Linear IC The źA 702 OPAMP
Fairchild
Fairchild
First IC źMOSAIC - created with Computer-
First IC źMOSAIC - created with Computer-
Aided Design.
Aided Design.
g
g
1967
1967
1967
1967
1967
1967
1967
1967
Transistors (organized in columns) could be
Transistors (organized in columns) could be
easily rewired using a two-layer interconnect to
easily rewired using a two-layer interconnect to
create different circuits. This circuit contains
create different circuits. This circuit contains
~150 logic gates.
~150 logic gates.
W.Kucewicz Analogowe układy CMOS w technice VLSI 21
1K bit RAM
1K bit RAM
1K bit RAM
1K bit RAM
Noyce and Moore leave Fairchild and found Intel.
Noyce and Moore leave Fairchild and found Intel.
No business plan just a promise to specialize in memory chips
No business plan just a promise to specialize in memory chips
No business plan, just a promise to specialize in memory chips.
No business plan, just a promise to specialize in memory chips.
They raise $3M in two days and move to Santa Clara. By
They raise $3M in two days and move to Santa Clara. By
1968
1968
1968
1968
1971 Intel had 500 employees; by 1983 it had 21,500
1971 Intel had 500 employees; by 1983 it had 21,500
employees and $1100M in sales
employees and $1100M in sales
employees and $1100M in sales.
employees and $1100M in sales.
Intel
Intel
1970
1970
1970
1970
starts selling a 1K bit RAM, the 1103.
Intel
Intel
1971
1971
1971
1971
starts selling a first EPROM, the 1702.
W.Kucewicz Analogowe układy CMOS w technice VLSI 22
Microprocessor Intel 4004 ( 9 )
Microprocessor Intel 4004 ( 9 )
Microprocessor Intel 4004 ( 9 )
Microprocessor Intel 4004 ( 9 )
Mp (1971)
Mp (1971)
Mp (1971)
Mp (1971)
2300 transistors on one chip
2300 transistors on one chip
Freq. -108 kHz
Freq. -108 kHz
Technology 10ź
Technology 10ź
Technology  10ź
Technology  10ź
It was 1/8" by 1/16" and it was
It was 1/8" by 1/16" and it was
y
y
as powerful as ENIAC
as powerful as ENIAC
performing about 60,000
performing about 60,000
calculations in a second.
calculations in a s d
l l ti s i s d
l l ti s i second.
It was as powerful as ENIAC but was
It was as p
powerful as ENIAC but was
p
eclipsed by its more capable brothers
eclipsed by its more capable brothers
Ted Hoff s invention
Ted Hoff s invention
W.Kucewicz Analogowe układy CMOS w technice VLSI 23
Microprocessor Intel 8008
Microprocessor Intel 8008
Microprocessor Intel 8008
Microprocessor Intel 8008
Mp
Mp
Mp
Mp
Intel -
Intel - The microprocessor 8008
1972
1972
1972
1972
1972
1972
1972
1972
It had 3 500 transistors supporting a byte wide data path
It had 3,500 transistors supporting a byte-wide data path.
Despite its limitations, the 8008 was the first
microprocessor capable of playing the role of computer CPU
Intel -
Intel - The microprocessor 8008
1974
1974
1974
1974
1974
1974
1974
1974
the 8080 had 6,000 transistors fab ed in a 6um
h h d f  d
process. The clock rate was 2Mhz, more than
enough to ignite the personal computer industry.
At l t P l All d hi t thought h
At least Paul Allen and his partner th ht so when
they wrote a BASIC interpreter for the 8080 in
1975.
W.Kucewicz Analogowe układy CMOS w technice VLSI 24
MOS transistor history
MOS transistor history
MOS transistor history
MOS transistor history
My
My
My
My
MOSFET transistor - Lilienfeld (Canada) in 1925
MOSFET transistor - Lilienfeld (Canada) in 1925
CMOS  1960 s, b t plagued with manufacturing problems
CMOS  1960 but l d ith manufacturing problems
CMOS 1960 b t l d ith f t i bl
CMOS 1960 s, but plagued with f t i bl
PMOS in 1960 s (calculators)
PMOS in 1960 s (calculators)
NMOS in 1970 s (4004, 8080)  for speed
NMOS in 1970 s (4004, 8080)  for speed
CMOS in 1980 s  preferred MOSFET technology because of
CMOS in 1980 s preferred MOSFET technology because of
CMOS in 1980 s preferred MOSFET technology because of
CMOS in 1980 s  preferred MOSFET technology because of
power benefits
power benefits
BiCMOS
BiCMOS
BiCMOS
BiCMOS
SOI, Copper-Low K
SOI, Copper-Low K
W.Kucewicz Analogowe układy CMOS w technice VLSI 25
Lilienfeld p
Lilienfeld p
Lilienfeld p
Lilienfeld p
Lfpatent
Lfpatent
Lfpatent
Lfpatent
W.Kucewicz Analogowe układy CMOS w technice VLSI 26
A New Form of Transistor -- 1962
A New Form of Transistor -- 1962
A New Form of Transistor -- 1962
A New Form of Transistor -- 1962
Metal-Oxide
Metal-Oxide
Semiconductor Field-
Semiconductor Field-
Eff T i
Eff Transistor
Effect Transistor
Effect T i
Radio Corporation of
Radio Corporation of
America (RCA)
America (RCA)
Sarnoff Laboratories
Sarnoff Laboratories
Sarnoff Laboratories
Sarnoff Laboratories
W.Kucewicz Analogowe układy CMOS w technice VLSI 27
One of the Most Powerful 16-Bit
One of the Most Powerful 16-Bit
One of the Most Powerful 16-Bit
One of the Most Powerful 16-Bit
Microprocessors -- 1979
Microprocessors -- 1979
Microprocessors -- 1979
Microprocessors -- 1979
p
p
p
p
The Motorola 68000
The Motorola 68000
WELL INTO THE
WELL INTO THE
WELL INTO THE
WELL INTO THE
LARGE SCALE
LARGE SCALE
INTEGRATION
INTEGRATION
ERA
ERA
ERA
ERA
W.Kucewicz Analogowe układy CMOS w technice VLSI 28
A Very Early 32-Bit Microprocessor -
A Very Early 32-Bit Microprocessor -
A Very Early 32-Bit Microprocessor -
A Very Early 32-Bit Microprocessor -
1981
1981
1981
1981
The HP Focus Chip, Hewlett-
The HP Focus Chip, Hewlett-
Packard Co 450 000
Packard Co 450 000
Packard Co.  450,000
Packard Co.  450,000
Transistors
Transistors
THE VERY L RGE SCALE
THE VERY LARGE C LE
THE VERY LARGE C LE
THE VERY L RGE SCALE
INTEGRATED CIRCUIT
INTEGRATED CIRCUIT
ERA BEGINS
ERA BEGINS
W.Kucewicz Analogowe układy CMOS w technice VLSI 29
Microprocesor Intel Pentium 4 ( )
Microprocesor Intel Pentium 4 ( )
Microprocesor Intel Pentium 4 (2001)
Microprocesor Intel Pentium 4 (2001)
Mp um ( )
Mp um (2001)
Mp um ( )
Mp um (2001)
42 millions transistors on
42 millions transistors on
one chip
one chip
hi
hi
Freq.  1.5 GHz
Freq.  1.5 GHz
Techn. 0.18ź
Techn. 0.18ź
Techn.  0.18ź
Techn.  0.18ź
Performing billions of
calculations each second
l l h d
The density of the
The density of the
transistors is more than
transistors is more than
100k/mm2
100k/mm2
40 transistor will fit on
40 transistor will fit on
40 transistor will fit on
40 transistor will fit on
the cross section of the
the cross section of the
hair.
hair.
W.Kucewicz Analogowe układy CMOS w technice VLSI 30
Today
Today
Today
Today
y
y
y
y
Many disciplines have contributed to the current
Many disciplines have contributed to the current
state of the art in VLSI design:
state of the art in VLSI design:
state of the art in VLSI design:
state of the art in VLSI design:
solid-state physics
solid-state physics
materials science
materials science
materials science
materials science
lithography and fabrication
lithography and fabrication
device modeling
device modeling
device modeling
device modeling
circuit design & layout
circuit design & layout
architecture
architecture
algorithms
algorithms
CAD tools
CAD tools
W.Kucewicz Analogowe układy CMOS w technice VLSI 31
Computer Aided Design  CAD
Computer Aided Design  CAD
Computer Aided Design  CAD
Computer Aided Design  CAD
pg
pg
pg
pg
CAD tools are doing following tasks:
CAD tools are doing following tasks:
CAD tools are doing following tasks:
CAD tools are doing following tasks:
" organize
" organize
" organize
" organize
" generate
" generate
" generate
" generate
" generate
" generate
" generate
" generate
" verify
" verify
" verify
" verify
The main goal of using CAD is designing circuits with
The main goal of using CAD is designing circuits with
The main goal of using CAD is designing circuits with
The main goal of using CAD is designing circuits with
increasing complexity in always shorter times
increasing complexity in always shorter times
computer has to take over routine work
computer has to take over routine work
computer has to take over routine work
computer has to take over routine work
deliberate the designer from unnecessary low qualification work
deliberate the designer from unnecessary low qualification work
shift of design activities to higher level abstract work
shift of design activities to higher level abstract work
shift of design activities to higher level abstract work
shift of design activities to higher level abstract work
computer has to support new design methods
computer has to support new design methods
W.Kucewicz Analogowe układy CMOS w technice VLSI 32
Computer Aided Design  CAD
Computer Aided Design  CAD
Computer Aided Design  CAD
Computer Aided Design  CAD
pg
pg
pg
pg
CAD tools are doing following tasks:
CAD tools are doing following tasks:
CAD tools are doing following tasks:
CAD tools are doing following tasks:
" organize
" organize
" organize
" organize
" generate
" generate
" generate
" generate
" generate
" generate
" generate
" generate
" verify
" verify
" verify
" verify
The main goal of using CAD is designing circuits with
The main goal of using CAD is designing circuits with
The main goal of using CAD is designing circuits with
The main goal of using CAD is designing circuits with
increasing complexity in always shorter times
increasing complexity in always shorter times
computer has to take over routine work
computer has to take over routine work
computer has to take over routine work
computer has to take over routine work
deliberate the designer from unnecessary low qualification work
deliberate the designer from unnecessary low qualification work
shift of design activities to higher level abstract work
shift of design activities to higher level abstract work
shift of design activities to higher level abstract work
shift of design activities to higher level abstract work
computer has to support new design methods
computer has to support new design methods
W.Kucewicz Analogowe układy CMOS w technice VLSI 33
Gate Array, Semi-Custom, and Full-
Gate Array, Semi-Custom, and Full-
Gate Array, Semi-Custom, and Full-
Gate Array, Semi-Custom, and Full-
Custom ICs
Custom ICs
Custom ICs
Custom ICs
Custom ICs
Custom ICs
Custom ICs
Custom ICs
VLSI Technology
VLSI Technology
Gate Array
Gate Array
Chip Area Ratios:
Chip Area Ratios:
3:2:1
3:2:1
Standard Cell
Standard Cell
Full Custom
W.Kucewicz Analogowe układy CMOS w technice VLSI 34
Progress in VLSI
Progress in VLSI
Progress in VLSI
Progress in VLSI
Progress in VLSI
Progress in VLSI
Progress in VLSI
Progress in VLSI
production
production
production
production
production
production
production
production
W.Kucewicz Analogowe układy CMOS w technice VLSI 35
Prawo M
Prawo M
Prawo M
Prawo M
w Moore a
w Moore a
w Moore a
w Moore a
W roku 1965 Gordoon Moore
W roku 1965 Gordoon Moore
(założyciel firm Fairchild i Intel)
(założyciel firm Fairchild i Intel)
(założyciel firm Fairchild i Intel)
(założyciel firm Fairchild i Intel)
przewidział, że liczba tranzystorów
przewidział, że liczba tranzystorów
w układzie scalonym będzie
w układzie scalonym będzie
zwiększała się eksponencjalnie w
zwiększała się eksponencjalnie w
funkcji czasu .
funkcji czasu .
W l t h 80-tych k b i
W latach 80 t h k b i
W latach 80 t h przekroczono barierę
W l t h 80-tych przekroczono barierę
1 miliona tranzystorów upakowanych w
1 miliona tranzystorów upakowanych w
jednej strukturze
jednej strukturze
jednej stru turze
jednej stru turze
" 2300 transistors (Intel 4004)  1971
" 2300 transistors (Intel 4004)  1971
" 42 Million (Intel P4) - 2001
" 42 Million (I t l P4) - 2001
42 Milli (Intel P4) 2001
42 Milli (I t l P4) 2001
W.Kucewicz Analogowe układy CMOS w technice VLSI 36
Postęp w p u j układów scalonych
Postęp w p u j układów scalonych
Postęp w p u j układów scalonych
Postęp w p u j układów scalonych
ęp w produkcji u wy
ęp w produkcji u wy
ęp w produkcji u wy
ęp w produkcji u wy
G.Moore - Cramming more
components onto integrated circuits
- Electronics, Volume 38, Number 8,
April 19 1965
April 19, 1965
Ilość tranzystorów w układzie scalonym podwaja się w
Ilość tranzystorów w układzie scalonym podwaja się w
Ilość tranzystorów w układzie scalonym podwaja się w
Ilość tranzystorów w układzie scalonym podwaja się w
ciagu roku
ciagu roku
W.Kucewicz Analogowe układy CMOS w technice VLSI 37
Technology Influence
Technology Influence
Technology Influence
Technology Influence
gy f u
gy f u
gy f u
gy f u
0.5 �m
0.18 �m 0.12�m
l
Devices
1993
1999
2002
3 layers
Interconnects
7 layers
8 layers
F
Frequency
1200 MH
1200 MHz
120MHz 500MHz
W.Kucewicz Analogowe układy CMOS w technice VLSI 38
Technology p g
Technology p g
Technology p g
Technology p g
gy progress
gy progress
gy progress
gy progress
1992 2002
1992 2002
1992 2002
1992 2002
0. �m, 7 metal layers
0.12�m, 7 metal layers
0.7�m, 2 metal layers
0 7�m 2 metal layers
Up to 500,000,000 devices
Up to 100,000 devices on a chip
CPU frequency 1,5GHz
CPU frequency 50MHz
1000 pins
1000 pins
10 years of
10 years of
10 years of
10 years of
IC
40 p
40 p
pins
pins
evolution
evolution
evolution
evolution
W.Kucewicz Analogowe układy CMOS w technice VLSI 39
Postęp w p u j procesorów
Postęp w p u j procesorów
Postęp w p u j procesorów
Postęp w p u j procesorów
ęp w produkcji p w
ęp w produkcji p w
ęp w produkcji p w
ęp w produkcji p w
P. Gargini  Sailing with the ITRS into nanotechnology - 2004
Ilość tranzystorów w układzie podwaja się w ciagu 2 lat
Ilość tranzystorów w układzie podwaja się w ciagu 2 lat
W.Kucewicz Analogowe układy CMOS w technice VLSI 40
Postęp w p u j procesorów
Postęp w p u j procesorów
Postęp w p u j procesorów
Postęp w p u j procesorów
ęp w produkcji p w
ęp w produkcji p w
ęp w produkcji p w
ęp w produkcji p w
P. Gargini  Sailing with the ITRS into nanotechnology - 2004
Powierzchnia układu scalonego podwaja się w ciagu 6 lat
Powierzchnia układu scalonego podwaja się w ciagu 6 lat
W.Kucewicz Analogowe układy CMOS w technice VLSI 41
Nanotechnologia
Nanotechnologia
Nanotechnologia
Nanotechnologia
Ng
Ng
Ng
Ng
P. Gargini  Sailing with the ITRS into nanotechnology - 2004
Reasonably familiar Nanotube Different technology
Reasonably familiar Nanotube Different technology
W.Kucewicz Analogowe układy CMOS w technice VLSI 42
DRAM chip capacity evolution
DRAM chip capacity evolution
DRAM chip capacity evolution
DRAM chip capacity evolution
DM p p y u
DM p p y u
DM p p y u
DM p p y u
Memory/chip
Memory/chip
doubles every 1.5 year
doubles every 1.5 year
Year
Year
W.Kucewicz Analogowe układy CMOS w technice VLSI 43
p
p
t
t
y
y
M
M
Memory (kBits/chip)
Memory (kBits/chip)
Cost p
Cost p
Cost p
Cost p
per Transistor
per Transistor
per Transistor
per Transistor
cost:
cost:
cost:
cost:
ó-per-transistor
ó-per-transistor
Fabrication capital cost per
Fabrication capital cost per
transistor (Moore s law)
transistor (Moore s law)
transistor (Moore s law)
transistor (Moore s law)
1
1
0.1
0.1
0.01
0.01
0.001
0.001
0.0001
0.0001
0.00001
0.00001
0.000001
0.000001
0.0000001
0.0000001
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012
W.Kucewicz Analogowe układy CMOS w technice VLSI 44
Wiring Levels and Mask L
Wiring Levels and Mask L
Wiring Levels and Mask L
Wiring Levels and Mask L
Wg L M Levels
Wg L M Levels
Wg L M Levels
Wg L M Levels
35
29
29
29
27
27
30
27
25 25 25
25 25
25
25
20
Max. Wiring Levels
15 mProcessor Mask Levels
10
10
10
9
9
9
8
10
8
8
7
7
5
0
0
2001 2002 2003 2004 2005 2006 2007 2010 2013 2016
Year
Year
W.Kucewicz Analogowe układy CMOS w technice VLSI 45
e
r
Number of Levels
On-Chip Clock Ć and Power Supply VDD
On-Chip Clock Ć and Power Supply VDD
On-Chip Clock Ć and Power Supply VDD
On-Chip Clock Ć and Power Supply VDD
35 1 2
35 1,2
1,1
1 1
1 28,751
30
0,9
1
0,9
0,9
25
0,8
0,7
20
20
19 348
19,348
06
0,6
0,6
0,5
15 Clock Frequency
0,4
VDD
VDD
11 511
11,511
04
0,4
10
5,631
5,173
3,99
3,088
6,739
0,2
1,684
2,317
5
0 0
2001 200220032004 20052006 20072010 2013 2016
Year
W.Kucewicz Analogowe układy CMOS w technice VLSI 46
G
y
u
e
o
Power Supply (Volts)
C
Chip Clock Frequency (GHz)
źProcessor and DRAM Fault Density
źProcessor and DRAM Fault Density
źProcessor and DRAM Fault Density
źProcessor and DRAM Fault Density
Targets
Targets
Targets
Targets
Targets
Targets
Targets
Targets
3000
2748
2493
2493
2148
2500
2236
1963
1752
2000
2000
1426
1464
1356
1356
1500
1356
1356 1356
1356
1356
1356 1356 1356
1000
1116 1134
źProcessor (83% yield)
źProcessor (83% yield)
500
DRAM (89.5% yield)
0
2001 2002 2003 2004 2005 2006 2007 2010 2013 2016
Year
W.Kucewicz Analogowe układy CMOS w technice VLSI 47
2
t
Faults / m
Long-Term Trends
Long-Term Trends
Long-Term Trends
Long-Term Trends
L g m
L g m
L g m
L g m
1. IC market growth averaged 17% per year
1. IC market growth averaged 17% per year
2. CMOS circuits represent more than 75% of the world s
2. CMOS circuits represent more than 75% of the world s
semiconductors
semiconductors
3. 16% annual chip feature size reduction 1995-2001
3. 16% annual chip feature size reduction 1995-2001
4. 11% annual chip feature size reduction 2002  future
4. 11% annual chip feature size reduction 2002  future
5. DRAM chip size increases 12% / year
5. DRAM chip size increases 12% / year
6. Pins/balls on packages increase 10% / year
6. Pins/balls on packages increase 10% / year
7. Pin cost decreases 5% / year
7. Pin cost decreases 5% / year
8. Average package cost increases 5% / year
8. Average package cost increases 5% / year
9. Packaging share of system cost doubles over 15 years
9. Packaging share of system cost doubles over 15 years
Drives migration to SoC, Multi-Chip Modules (MCMs)SIP devices
W.Kucewicz Analogowe układy CMOS w technice VLSI 48
Postęp w p u j płytek krzemowych
Postęp w p u j płytek krzemowych
Postęp w p u j płytek krzemowych
Postęp w p u j płytek krzemowych
ęp w produkcji p yz m wy
ęp w produkcji p yz m wy
ęp w produkcji p yz m wy
ęp w produkcji p yz m wy
P. Gargini  Sailing with the ITRS into nanotechnology - 2004
Powierzchnia płytki krzemowej podwaja się w ciagu 8 lat
Powierzchnia płytki krzemowej podwaja się w ciagu 8 lat
W.Kucewicz Analogowe układy CMOS w technice VLSI 49
Mikroelektronika Nan t chn g a
Mikroelektronika Nan t chn g a
Mikroelektronika Nan t chn g a
Mikroelektronika Nan t chn g a
M r tr n a Nanotechnologia
M r tr n a Nanotechnologia
M r tr n a Nanotechnologia
M r tr n a Nanotechnologia
P. Gargini  Sailing with the ITRS into nanotechnology - 2004
Powierzchnia płytki krzemowej podwaja się w ciagu 8 lat
Powierzchnia płytki krzemowej podwaja się w ciagu 8 lat
W.Kucewicz Analogowe układy CMOS w technice VLSI 50
Mikroelektronika Nan t chn g a
Mikroelektronika Nan t chn g a
Mikroelektronika Nan t chn g a
Mikroelektronika Nan t chn g a
M r tr n a Nanotechnologia
M r tr n a Nanotechnologia
M r tr n a Nanotechnologia
M r tr n a Nanotechnologia
P. Gargini  Sailing with the ITRS into nanotechnology - 2004
Powierzchnia płytki krzemowej podwaja się w ciagu 8 lat
Powierzchnia płytki krzemowej podwaja się w ciagu 8 lat
W.Kucewicz Analogowe układy CMOS w technice VLSI 51
Technology D
Technology D
Technology D
Technology D
gy Directions
gy Directions
gy Directions
gy Directions
Year 1999 2002 2005 2008 2011 2014
Year 1999 2002 2005 2008 2011 2014
Feature size [nm] 180 130 100 70 50 35
Feature size [nm] 180 130 100 70 50 35
Feature size [nm] 180 130 100 70 50 35
Feature size [nm] 180 130 100 70 50 35
Mtrans/cm2 7 14-26 47 115 284 701
Mtrans/cm2 714-26 47 115 284 701
Chip size [mm2] 170 170 214 235 269 308 354
Chip size [mm ] 170 170-214 235 269 308 354
Chip size [mm ] 170 170 214 235 269 308 354
Chip size [mm2] 170 170-214 235 269 308 354
Signal pins/chip 768 1024 1024 1280 1408 1472
Signal pins/chip 768 1024 1024 1280 1408 1472
Wiring levels 6-7 7-8 8-9 99-10 10
Wiring levels 6-77-88-999-10 10
Power supp [V] 1.8 1.5 1.2 0.8 0.6 0.6
Power supp [V] 1.8 1.5 1.2 0.8 0.6 0.6
Power [W] 90 130 180 170 174 183
Power [W] 90 130 180 170 174 183
Battery power [W] 1.4 2.0 2.4 2.0 2.2 2.4
Battery power [W] 1.4 2.0 2.4 2.0 2.2 2.4
W.Kucewicz Analogowe układy CMOS w technice VLSI 52
Moore s L w Predictions  2025?
Moore s L w Predictions  2025?
Moore s L w Predictions  2025?
Moore s L w Predictions  2025?
MLaw
MLaw
MLaw
MLaw
Assumptions in 1995 based on 1960-1995
Assumptions in 1995 based on 1960-1995
Transistors per chip doubles every 1.5 years
Transistors per chip doubles every 1.5 years
Transistors per chip doubles every 1.5 years
Transistors per chip doubles every 1.5 years
Minimum feature size is cut in half every six years
Minimum feature size is cut in half every six years
Chip area goes up 2.3 times every six years
Chip area goes up 2.3 times every six years
Manufacturing costs remain about constant
Manufacturing costs remain about constant
Manufacturing costs remain about constant
Manufacturing costs remain about constant
This leads us to the following predictions
This leads us to the following predictions
Wafer size will be 32 inches!
32 inches!
A wafer fabrication will cost a tens of G$
The chips will be 3 by 6 inches
3 b 6 i h
3 b 6 inches
3 by 6 i h
The minimum feature size will be 100 Angstroms (which is
100 Angstroms
about 5 photoresist molecules wide)
about 5 photoresist molecules wide)
A Memory chip will hold 64 TERA bits
64 TERA bits
will they come true?!
will they come true?!
W.Kucewicz Analogowe układy CMOS w technice VLSI 53