JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 12, NO. 4, AUGUST 2003 465
Arrays of Monocrystalline Silicon Micromirrors
Fabricated Using CMOS Compatible Transfer
Bonding
Frank Niklaus, Member, IEEE, Sjoerd Haasl, Member, IEEE, and Göran Stemme, Member, IEEE
Abstract In this paper, we present CMOS compatible fab- cromirrors have been made of aluminum, polycrystalline
rication of monocrystalline silicon micromirror arrays using
silicon, and monocrystalline silicon. Micromirrors that are
membrane transfer bonding. To fabricate the micromirrors, a thin
made of monocrystalline silicon or other monocrystalline
monocrystalline silicon device layer is transferred from a standard
materials have several advantages. The mechanical stability of
silicon-on-insulator (SOI) wafer to a target wafer (e.g., a CMOS
monocrystalline silicon is superior over metals. In contrast to
wafer) using low-temperature adhesive wafer bonding. In this way,
very flat, uniform and low-stress micromirror membranes made metal micromirror hinges, there are no recrystallization effects
of monocrystalline silicon can be directly fabricated on top of
due to material deformation in monocrystalline silicon hinges.
CMOS circuits. The mirror fabrication does not contain any bond
This minimizes hysteresis and memory effects as a result of
alignment between the wafers, thus, the mirror dimensions and
repeated or prolonged micromirror actuation, which is very
alignment accuracies are only limited by the photolithographic
important in applications where the mirrors must be actuated
steps. Micromirror arrays with 4 4 pixels and a pitch size of
16 m 16 m have been fabricated. The monocrystalline to a number of discrete tilting angles (analog addressing) [8],
silicon micromirrors are 0.34 m thick and have feature sizes as
[10]. The achievable optical quality, the surface roughness and
small as 0.6 m. The distance between the addressing electrodes
the uniformity of monocrystalline silicon surfaces is superior
and the mirror membranes is 0.8 m. Torsional micromirror
compared to most other surfaces [1], [11], [13]. The integration
arrays are used as spatial light modulators, and have potential
of micromirrors and integrated circuits is most commonly
applications in projection display systems, pattern generators for
maskless lithography systems, optical spectroscopy, and optical achieved with monolithic integration of the micromirrors
communication systems. In principle, the membrane transfer
on integrated circuits [3], [6] [10]. The disadvantage is that
bonding technique can be applied for integration of CMOS circuits
no monocrystalline materials and only CMOS compatible
with any type of transducer that consists of membranes and that
fabrication processes with temperatures below 450 can be
benefits from the use of high temperature annealed or monocrys-
used for the integrated mirrors. Hybrid integration techniques
talline materials. These types of devices include thermal infrared
detectors, RF-MEMS devices, tuneable vertical cavity surface such as flip-chip bonding or compression bonding [15],
emitting lasers (VCSEL) and other optical transducers. [917]
[16] circumvent these problems and allow the combination
of integrated circuits with high-temperature annealed and
Index Terms Adhesive bonding, CMOS compatible, membrane
transfer bonding, micromirror, monocrystalline silicon, SLM, spa- monocrystalline mirror materials. However, these techniques
tial light modulator.
have severe limitations in terms of minimum achievable feature
size and thickness of the micromirrors and in the alignment and
distance control between the micromirrors and the electrodes
I. INTRODUCTION
on the integrated circuits. In this paper we present the first
ICROMIRROR arrays are spatial light modulators
wafer-level fabrication of arrays of monocrystalline silicon
(SLM) that can modulate the phase or amplitude of in-
M
micromirrors using membrane transfer bonding [17]. With this
cident light [1] [5]. The main application areas of micromirror
technique it is possible to directly fabricate monocrystalline
arrays are projection display systems [6], pattern generators in
silicon micromirrors on top of standard CMOS wafers. The
maskless lithography systems [7] [10], optical scanners [11],
micromirror arrays consist of 4 4 individual micromirrors
printers, optical spectroscopy, aberration correction, adaptive
with a membrane thickness of 0.34 ( 5%) and a pitch
optical systems [12], [13] and switches and cross connectors
size of . For the micromirror fabrication, a
in optical communication systems [14]. Some of these appli-
thin monocrystalline silicon device layer is transferred from
cations require large two-dimensional arrays of individually
a standard silicon-on-insulator (SOI) wafer to a wafer that
addressable micromirrors. To achieve this, it is necessary
contains electrode structures (e.g., a CMOS wafer). This is
to combine the micromirrors with on-chip electronics. Mi-
done using low-temperature adhesive wafer bonding [18],
[19] in combination with sacrificial removal of the SOI wafer
Manuscript received August 9, 2002; revised January 30, 2003. Subject Editor [17], [20]. The transferred silicon film is then patterned and
N. C. Tien.
connected to the new substrate wafer with electroplated gold
The authors are with the Royal Institute of Technology (KTH) Dept. of Sig-
posts. Finally, the intermediate adhesive bonding material is
nals, Sensors, and Systems SE-100 44 Stockholm, Sweden.
Digital Object Identifier 10.1109/JMEMS.2003.815833 sacrificially removed to release the mirror membranes.
1057-7157/03$17.00 © 2003 IEEE
466 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 12, NO. 4, AUGUST 2003
Fig. 1. Schematic view of a monocrystalline silicon micromirror.
II. MICROMIRROR DESIGN
Fig. 1 shows a schematic drawing of the torsional mi-
cromirror. It consists of a monocrystalline silicon membrane
that is connected to a silicon substrate via two gold posts.
Aluminum addressing electrodes are formed on the silicon
substrate below the mirror plate. The mirror plate is electrically
connected via the gold posts to the gold metalization layer on
the silicon wafer. To actuate the mirror, a voltage is applied
between the mirror membrane and one of the two addressing
electrodes. Consequently, the electric field forces actuate the
silicon mirror similar to a seesaw. The mirror hinges create
torsional spring forces that oppose the electric field forces.
These spring forces grow linearly with the hinge deformation
for small rotation angles. The electric field forces grow as
the square of the voltage for a (hypothetical) fixed distance
between the mirror and the addressing electrode. For a fixed
voltage, the electric field forces grow inversely to the square of
the distance between the mirror membrane and the addressing
electrode (assuming that there is no tilting of the mirror
Fig. 2. Process flow for CMOS compatible fabrication of monocrystalline
membrane). As a result, typical deformation characteristics of
silicon micromirrors using membrane transfer bonding.
torsional micromirrors are strongly nonlinear and a voltage
exists at which the mirror is suddenly pulled in. Distance
50-nm-thick titanium (Ti) seed layer and a 1- -thick gold
holders prevent the mirror membrane from contacting the
(Au) layer is evaporated onto the silicon wafer which is
addressing electrodes when the pull-in voltage is exceeded.
then covered with a 0.5- -thick plasma-enhanced chemical
A pulled-in mirror membrane is released again at a much
vapor deposited (PCVD) silicon nitride layer and a
smaller voltage than the pull-in voltage. A detailed study of
0.15- -thick sputtered aluminum (Al) layer. Second, the
design parameters and characteristics of torsional micromirrors
top aluminum layer is patterned and wet etched to define the
is given elsewhere [21], [22]. To demonstrate the concept,
addressing electrodes of the micromirrors and the connected
we have designed arrays of 4 4 monocrystalline silicon
probing pads as illustrated in Fig. 2(a). Third, a 0.2- -thick
micromirrors, that can be addressed and actuated line by line.
silicon nitride layer is deposited on top of the addressing
The mirror membranes are 0.34 thick and the mirror plates
electrodes and patterned with reactive ion etching to define
are . The hinges are 4 long, 0.6 wide
the distance holders. Next, the 0.5- -thick silicon nitride
and the posts are in size. The distance between
layer covering the gold is patterned with reactive ion etching
the addressing electrodes and the mirror membranes is 0.7
to define the holes for the posts. The photoresist for the nitride
and the effective size of the addressing electrodes is 79 .
patterning remains on top of the silicon nitride layer as shown
The fill factor of the mirrors is 51%.
in Fig. 2(b) and acts as a mold for the posts during the gold
electroplating. The gold seed layer is exposed at the bottom
III. FABRICATION OF MONOCRYSTALLINE SILICON
of the holes. It is used as the plating base for electroplating
MICROMIRRORS
the 1.45 high gold posts. Consequently, the gold posts
Fig. 2 shows the process flow for the fabrication of the extend 0.8 over the surface of the aluminum addressing
monocrystalline silicon micromirrors with membrane transfer electrodes. After this, the resist is removed. Fig. 2(c) shows a
bonding. The substrate for the micromirrors (target wafer) schematic drawing of the cross section of the target wafer with
is a 500- -thick, 10-cm-diameter silicon wafer. First, a the addressing electrodes and the electroplated posts. Fig. 3
NIKLAUS et al.: ARRAYS OF MONOCRYSTALLINE SILICON MICROMIRRORS 467
Fig. 4. SEM image of the target wafer with transfer bonded and patterned
Fig. 3. SEM image of the target wafer with the mirror addressing electrodes
monocrystalline silicon micromirror membranes. The top surface of the mirrors
and the electroplated gold posts.
is covered with photoresist.
shows an SEM image of these structures. An SOI wafer from
etching. Fig. 4 shows an SEM image of the transferred and pat-
SOITEC (France) with a 0.34- ( 5%) thick silicon device
terned mirror membranes with the underlying posts, distance
layer, a 0.3- -thick layer and a 535- -thick silicon
holders and addressing electrodes. The resist mask is removed
substrate was used as the sacrificial wafer. It was bonded to
with a short oxygen plasma etch as illustrated in Fig. 2(f). A
the target wafer using low-temperature adhesive wafer bonding
thin layer of adhesive bonding material that remained on top of
as illustrated in Fig. 2(d). A 0.8- -thick layer of ULTRA-i
the gold posts is removed in the same etching step. The etching
310 (a negative photoresist from Shipley) that is spin-coated on
time has to be short to prevent a large underetch of the adhe-
the SOI wafer was used as the intermediate adhesive bonding
sive bonding material underneath the mirror membranes. The
material. An SB6 bonder from Karl Suss was used for bonding.
electrical and mechanical via connectors between the gold posts
The electroplated posts are pressed into the adhesive bonding
and the mirror membranes are formed by electroplating another
material during the bonding procedure. Their height of 0.8 ,
0.8 of gold on top of the posts. Thus, the silicon mirror
also defines the distance between the addressing electrode and
membranes are joined and mechanically locked to the posts as
mirror membranes. The adhesive bonding procedure consists
can be seen in Fig. 2(g). Finally, the adhesive bonding mate-
of the following steps:
rial (ULTRA-i 310) under the silicon membranes is sacrificially
1) Rinse and dry the wafers.
removed to free the monocrystalline silicon micromirrors as il-
2) Spin-coat the ULTRA-i 310 negative photoresist to the
lustrated in Fig. 2(h). This is done in an oxygen plasma etcher
sacrificial wafer (SOI wafer).
at 1000 W for 3 h.
3) Precure the photoresist coating on a hotplate at 70 for
2 minutes.
IV. RESULTS AND DISCUSSION
4) Join the sacrificial wafer and the target wafer in the
vacuum environment of the bond chamber.
The critical steps in the fabrication of the micromirrors are the
5) Cure the photoresist at 110 for 20 min while pressing
adhesive wafer bonding process and the removal of the sacrifi-
the wafers together with the bond chuck using a pressure
cial wafer. The use of the extremely thin intermediate adhesive
of 4 bar.
bonding layer caused some unbonded areas at the bond interface
The sacrificial wafer (SOI bulk material) is removed with a com- [18]. The grinding procedure did not induce any visible damage
bination of grinding and deep-reactive ion etching (DRIE). A or cracking of the sacrificial wafer. However, when further thin-
depth of 465 of the sacrificial wafer is removed by grinding ning down the sacrificial wafer with DRIE, the transferred thin
and the remaining 70 silicon is etched down to the film peeled off the target wafer at the unbonded areas. The trans-
etch stop layer using DRIE. The layer is removed using a ferred thin film remained undamaged and without cracks over
buffered HF etch solution. As illustrated in Fig. 2(e), a 0.34 the areas that were bonded. To increase the yield of the mi-
thick monocrystalline silicon layer remains on top of the adhe- cromirror fabrication, adhesive wafer bonding with very thin in-
sive bonding material on the target wafer. A photoresist mask termediate adhesive layers needs to be further optimized.
that defines the mirror membranes is patterned on top of this Arrays of 4 4 monocrystalline silicon micromirrors have
transferred monocrystalline silicon film using standard lithog- been fabricated using membrane transfer bonding. Fig. 5 shows
raphy with a mask aligner. The photoresist pattern is aligned to the micromirrors with the underlying aluminum addressing
the addressing electrodes on the target wafer, which can be seen electrodes. The mirrors are addressable line-by-line. All mirrors
through the transferred thin monocrystalline silicon film. Thus, in the tested array were operational. The pull-in voltage of the
the alignment accuracy between the addressing electrodes and mirrors was measured to be 12.5 V and the release voltage
the mirror membranes is only limited by the alignment accuracy of pulled-in mirrors was 7 V. Fig. 6 shows the surface profile
of the photolithography (with our equipment below 1.5 ). of a monocrystalline silicon micromirror surface taken with
The monocrystalline silicon film is patterned using reactive ion an atomic force microscope. The root-mean-square roughness
468 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 12, NO. 4, AUGUST 2003
during wafer bonding, thus, the achievable mirror dimensions
and alignment accuracies are only limited by photo-lithography.
The distance between the addressing electrodes and the mirror
membranes is defined by the height of electroplated posts.
The torsional micromirror arrays have potential applications
as spatial light modulators in projection display systems, in
maskless lithography systems and in optical communication
systems. In principle, the CMOS compatible membrane transfer
bonding technique can be applied to any type of transducer
that consists of membranes and that benefits from the use of
high-temperature annealed or monocrystalline materials. Such
transducer includes thermal infrared detectors, RF-MEMS de-
vices, tuneable vertical cavity surface emitting lasers (VCSEL)
and other optical transducers.
ACKNOWLEDGMENT
Fig. 5. SEM image of the fabricated monocrystalline silicon micromirrors.
The authors wish to thank E. Kälvesten, H. Westin, and N.
Svedin from Silex AB for help with the measurement setup and
with gold electroplating. They also would like to O. Douhéret
for help with the atomic force microscope measurements.
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Göran Stemme (M 98) was born in Stockholm,
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Sweden, on February 4, 1958. He received the
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M.Sc. degree in electrical engineering and the Ph.D.
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degree in solid state electronics from the Chalmers
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University of Technology, Gothenburg, Sweden, in
[23] A. Gehner, Entwicklung hochauflösender Flächenlichtmodula-
1981 and 1987, respectively.
toren mit Deformierbaren Spiegelanordnungen für die Maskenlose
In 1981, he joined the Department of Solid State
Mikrolithographie. Aachen, Germany: Shaker Verlag, 1997.
Electronics, Chalmers University of Technology,
Gothenburg, Sweden. In 1990, he became an
Associate Professor (Docent) heading the silicon
Frank Niklaus (M 00) was born in Malsch, sensor research group. In 1991, he was appointed a
Germany, in 1971. He received the M.Sc. degree Professor at The Royal Institute of Technology, Stockholm, Sweden, where
in mechanical engineering from the Technical he heads the Microsystem Technology group at the department of Signals,
University of Munich (TUM), Germany, in 1998. In Sensors and Systems. His research is devoted to microsystemtechnology based
2002, he received the Ph.D. degree from the Royal on micromachining of silicon. He has published more than 80 research journal
Institute of Technology in Stockholm, Sweden. and conference papers and has been awarded eight patents.
Currently, he is a Research Associate in the MST Dr. Stemme was a member of the International Steering Committee of the
group at the Royal Institute of Technology. His re- Conference series IEEE Microelectromechanical Systems (MEMS) between
search focus is on CMOS compatible adhesive wafer 1995 and 2001 and he was General Co-Chair of that conference in 1998.
bonding for different applications. These applications He is a member of the Editorial Board of the IEEE/ASME JOURNAL OF
include the fabrication and integration of uncooled MICROELECTROMECHNICAL SYSTEMS and of the Royal Society of Chemistry
infrared detector arrays and torsional micromirror arrays on CMOS circuit and journal Lab On A Chip. In 2001, he won, together with two colleagues, the
wafer level packaging of electronic and MEMS components. final of Innovation Cup.