library IEEE;
use IEEE.STD_LOGIC_1164.all;

package memory_package is

component memory_controller is
port( ready,read_write,burst,clk,reset,cs : in STD_LOGIC;
oe,we : out STD_LOGIC;
addr_burst : out std_logic_vector(1 downto 0) );
end component;

component memory is
port( oe,we,cs : in STD_LOGIC;
address : in std_logic_vector(7 downto 0);
addr_burst : in std_logic_vector(1 downto 0);
data : inout STD_LOGIC_VECTOR(7 downto 0) );
end component;

end package;


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity memory_controller is
port( ready,read_write,burst,clk,reset,cs : in STD_LOGIC;
oe,we : out STD_LOGIC;
addr_burst : out std_logic_vector(1 downto 0) );
end memory_controller;

architecture memory_controller of memory_controller is

type state is (idle,decision,write,read1,read2,read3,read4);
signal ps,ns : state;

begin
process(ps,reset,cs,read_write,ready,burst) begin
case ps is
when idle => oe <= '0'; we <= '0'; addr_burst <= "00";
if cs ='1' then ns <= decision;
else ns <= idle;
end if;
when decision =>oe <= '0'; we <= '0'; addr_burst <= "00";
if read_write='1' then ns <= read1;
else ns <= write;
end if;
when write => oe <= '0'; we <= '1'; addr_burst <= "00";
if ready='1' then ns <= idle;
else ns <= write;
end if;
when read1 => oe <= '1'; we <= '0'; addr_burst <= "00";
if ready='1' then
if burst='0' then ns <= idle;
else ns <= read2;
end if;
else ns <= read1;
end if;
when read2 => oe <= '1'; we <= '0'; addr_burst <= "01";
if ready='1' then ns <= read3;
else ns <= read2;
end if;
when read3 => oe <= '1'; we <= '0'; addr_burst <= "10";
if ready='1' then ns <= read4;
else ns <= read3;
end if;
when read4 => oe <= '1'; we <= '0'; addr_burst <= "11";
if ready='1' then ns <= idle;
else ns <= read4;
end if;
end case;

if reset='1' then ns <= idle;
end if;
end process;

process(clk) begin
if (clk'event and clk='1') then ps <= ns;
end if;
end process;
end memory_controller;


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;

entity memory is
port( oe,we,cs : in STD_LOGIC;
address : in std_logic_vector(7 downto 0);
addr_burst : in std_logic_vector(1 downto 0);
data : inout STD_LOGIC_VECTOR(7 downto 0) );
end memory;

architecture memory of memory is
--type memory is array (natural range <>) of std_logic_vector(7 downto 0);
type memory is array (0 to 255) of std_logic_vector(7 downto 0);
--signal mem: memory(255 downto 0);
signal mem : memory;
signal address_plus_burst : std_logic_vector(7 downto 0);

begin
address_plus_burst <= address + addr_burst;
mem(conv_integer(address_plus_burst)) <= data when (cs='1' and we='1' and oe='0')
else mem(conv_integer(address_plus_burst));
data <= mem(conv_integer(address_plus_burst)) when (cs='1' and we='0' and oe='1')
else (others => 'Z');
end memory;