library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
use work.memory_package.all;

entity pamiec is
port ( address : in std_logic_vector (7 downto 0);
addr_burst : inout std_logic_vector(1 downto 0);
data : inout std_logic_vector (7 downto 0);
cs,ready,read_write,burst,clk,reset : in STD_LOGIC );
end pamiec;

architecture pamiec of pamiec is
signal oe,we : std_logic;

begin
u1 : memory_controller port map (ready,read_write,burst,clk,reset,cs,oe,we,addr_burst);
u2 : memory port map (oe,we,cs,address,addr_burst,data);
end pamiec;