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counter binary 2bit summary
Xilinx Design Summary counter_binary_2bit Project Status (05/28/2013 - 19:07:00) Project File: seven_seg_bright_control.xise Parser Errors: No Errors Module Name: counter_binary_2bit Implementation State: Synthesized Target Device: xc6slx16-3csg324 Errors: Product Version:ISE 14.2 Warnings: Design Goal: Balanced Routing Results: Design Strategy: Xilinx Default (unlocked) Timing Constraints: Environment: Final Timing Score: Detailed Reports [-] Report NameStatusGenerated ErrorsWarningsInfos Synthesis Report Translation Report Map Report Place and Route Report CPLD Fitter Report (Text) Power Report Post-PAR Static Timing Report Bitgen Report Secondary Reports [-] Report NameStatusGenerated ISIM Simulator LogCurrentWt 28. maj 19:09:09 2013 Date Generated: 05/28/2013 - 19:09:50
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