Xilinx Design Summary top Project Status (06/10/2013 - 12:32:17) Project File: vhdl.xise Parser Errors: No Errors Module Name: top Implementation State: Synthesized (Failed) Target Device: xc2c256-6TQ144 Errors: X 8 Errors (0 new) Product Version:ISE 14.4 Warnings: No Warnings Design Goal: Balanced Routing Results:   Design Strategy: Xilinx Default (unlocked) Timing Constraints:   Environment: System Settings Final Timing Score:      Detailed Reports [-] Report NameStatusGenerated ErrorsWarningsInfos Synthesis ReportCurrentPn 10. cze 12:32:16 2013X 8 Errors (0 new)00 Translation ReportOut of DatePn 10. cze 12:26:15 2013000 CPLD Fitter Report (Text)Out of DatePn 10. cze 12:26:22 201301 Warning (1 new)1 Info (1 new) Power Report        Secondary Reports [-] Report NameStatusGenerated Post-Fit Simulation Model Report   Date Generated: 06/10/2013 - 12:32:17