Xilinx Design Summary top Project Status Project File: wysw.xise Parser Errors: No Errors Module Name: top Implementation State: Fitted Target Device: xc2c256-6TQ144 Errors: No Errors Product Version:ISE 14.4 Warnings: 10 Warnings (6 new) Design Goal: Balanced Routing Results:   Design Strategy: Xilinx Default (unlocked) Timing Constraints:   Environment: System Settings Final Timing Score:      Detailed Reports [-] Report NameStatusGenerated ErrorsWarningsInfos Synthesis ReportCurrentPn 10. cze 10:29:51 2013010 Warnings (6 new)0 Translation ReportCurrentPn 10. cze 10:29:58 2013000 CPLD Fitter Report (Text)CurrentPn 10. cze 10:30:02 201301 Warning (1 new)1 Info (1 new) Power Report        Secondary Reports [-] Report NameStatusGenerated Post-Fit Simulation Model Report   Date Generated: 06/10/2013 - 10:37:21