7 (176)

,    .__r.,-_V7Tfw,,

http://www.weiti. 13.net.pl/pliki/ucyf/aut_cd2_zad 1

LIBRARY ieee;

OSE ieee.std_logic_l164.all;

ENTITY aut IS PORT (

xl,x2, clk : IN STDJLOGIC; z : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)

) ;

END aut;

ARCHITECTURE aut_beh OF aut IS

TYPE State IS (A, B, C, D, E) ; SIGNAL curr_state : State :=A;

BEGIN

PROCESS(clk)

BEGIN

IF(clk'EVENT and clk=’l') THEN CASE curr State IS

WHEN A =>

IF (xl=*1') THEN curr_state<=A;

EŁSE curr_state<=B;

END IF;

WHEN B =>

IF (x2='1' AND xl='0*) THEN curr_state<=D; ELSIF (x2=*1* AND xl-^,l’) THEN curr_state<=£; EŁSE curr_state<=C;

END IF; ~

WHEN C =>

IF (xl='l') THEN currstate <=C;

EŁSE curr_state <=E;

END IF;

WHEN D =>

curr_state<=E;

WHEN E =>

IF(x2='1') THEN curr_state<=A;

EŁSE curr_state<=C;

END IF;

END CASE;

END IF; END PROCESS;

z <= "000" WHEN curr_state=A EŁSE

"001" WHEN curr_state=B EŁSE "010" WHEN curr_state=C EŁSE "011" WHEN curr_state=D EŁSE "100";

END aut beh;