tat off part1

tl Statistics

h|| Statistics

- n x

Total:

7541 Cycle(s) executed.

ID executed by 2653 Insłrucłion(s).

2 Insłrucłion(s) currently in Pipeline.

Hardware cor.figuratior.:

Memory size: 32768 Bytes faddEX-Stages: 1, required Cycles: 2 fmulEX-Stages: 1, required Cycles: 5 fdivEX-Stage$: 1, required Cycles: 13 Forwarding disabled.

Stalla:

RAW stalls: 4646 (61.61 % of all Cycles)

WAW stalls: 0 (0.00% of all Cycles)

Structural stalls: 0 (0.00% of all Cycles)

Confrol sfalls: 233 (3.10% of all Cycles)

T rap sfalls: 3 (0.04% of all Cycles)

Tofal: 4332 Stall(s) (64.74% of all Cycles)

Cor.ditional 3ranches) :

T otal: 235 (3.34% of all Instructions), fhereof: taken: 233 (99.15% of all cond. Branches) nof taken: 2 (0.35% of all cond. Branches)

Load-/Store-Instructior.s :

T otal: 372 (32.81 % of all Instructions), thereof:

Loads: 636 (72.94% of Load7Store-lnsłrucłions)

Stores: 236 (27.06% of Load7Store-lnsłrucłions)

Floating point stage instructior.s :

T otal: 367 (32.62% of all Instructions), thereof:

Addiłions: 552 (63.67% of Floating point stage inst.) Multiplications: 210 (24.22% of Floating point stage inst.) Divi$ions: 105 (12.11 % of Floating point stage inst.)

Traps:

Traps: 1 (0.04% of all Instructions)

hk Statistics    - |n|

Total:

7541 Cycle(s) executed.

ID executed by 2658 Instrucłion(s)

2 Instruction(s) currently in Pipeline.

Hardware configuration:

Memory size: 32768 Bytes faddEX-Stages: 1, required Cycles: 2 fmulEX-Stages: 4, required Cycles: 5 fdivEX-Stages: 1, required Cycles: 19 Forwarding disabled.

3t*Ui :

RAW stalls: 4646 (61.61 % of all Cycles)

WAW stalls: 0 (0.00% of all Cycles)

Structural stalls: 0 (0.00% of all Cycles)

Control stalls: 233 (3.10% of all Cycles)

T rap stalls: 3 (0.04% of all Cycles)

Total: 4882 Stall(s) (64.74% of all Cycles)

Conditional SrancHes) :

Total: 235 (8 84% of all Instructions), thereof: taken: 233 (99.15% of all cond. Branches) not taken: 2 (0 85% of all cond. Branches)

Load-/3core-Inscruccions:

Total: 872 (32.81 % of all Instructions), thereof:

Loads: 636 (72.94% of Load7Store-lnstructions)

Stores: 236 (27 06% of Load /Store lnstructions)

Floating point stage instructions:

Total: 867 (32.62% of dl Instructions), thereof:

Additions: 552 (63.67% of Floating point stage inst.) Multiplications: 210 (24 22% of Floating point stage inst.) Divisions: 105 (12.11 % of Floating point stage inst.)

Traps:

Traps: 1 (0.04% of all Instructions)

Total:

7541 Cycle(s) executed.

ID executed by 2653 Insłrucłion(s). 2 Instruction(s) currently in Pipeline.

Hardware cor.figuratior.:

Memory size: 32768 Bytes faddEX-Stages: 4, required Cycles: 2 fmulEX-Stages: 1, required Cycles: 5 fdivEX-Stages: 1, required Cycles: 19 Forwarding disabled.

Stalla:

RAW stalls: 4646 (61.61 % of all Cycles)

WAW stalls: 0 (0.00% of all Cycles)

Structural stalls: 0 (0.00% of all Cycles)

Control stalls: 233 (3.10% of all Cycles)

T rap stalls: 3 (0.04% of all Cycles)

Total: 4382 Stall(s) (64.74% of all Cycles)

Cor.ditional 3rar.ches) :

Total: 235 (3.84% of all Instructions), thereof: taken: 233 (99.15% of all cond. Branches) not taken: 2 (0.35% of all cond. Branches)

Load-/3tore-Instructions:

Total: 872 (32.81 % of all Instructions), thereof:

Loads: 636 (72.94% of Load7Store-lnsłrucłions)

Stores: 236 (27.06% of Load7Store-lnsłrucłions)

Floating point stage instructions:

Total: 367 (32.62% of all Instructions), thereof:

Addiłions: 552 (63.67% of Floating point stage inst.) Multiplications: 210 (24.22% of Floating point stage inst.) Divisions: 105 (12.11 % of Floating point stage inst.)

Traps:

Traps: 1 (0.04% of all Instructions)

11 Statistics    - [□]! x|

Total:

7541 Cycle(s) executed.

ID executed by 2658 Instruction(s).

2 Insłrucłion(s) currently in Pipeline.

Hardware configuration:

Memory size: 32768 Bytes faddEX-Stages: 1, required Cycles: 2 fmulEX-Stages: 1, required Cycles: 5 fdivEX-Stages: 4, required Cycles: 19 Forwarding disabled.

3talls:

RAW stalls: 4646 (61.61 % of all Cycles)

WAW stalls: 0 (0.00% of all Cycles)

Structural stalls: 0 (0.00% of all Cycles)

Control stalls: 233 (3.10% of all Cycles)

T rap stalls: 3 (0.04% of all Cycles)

Total: 4332 Stall(s) (64.74% of all Cycles)

Cor.ditional 3ranches) :

Total: 235 (3.34% of all Instructions), thereof: taken: 233 (99.15% of all cond. Branches) not taken: 2 (0.85% of all cond. Branches)

Load-/3tore-Instructions:

Total: 872 (32.31 % of all Instructions), thereof:

Loads: 636 (72.94% of Load7Store-lnstructions)

Stores: 236 (27.06% of Load7Store-lnstructions)

Floating point stage instructions:

Total: 367 (32.62% of all Instructions), thereof:

Addiłions: 552 (63.67% of Floating point stage inst.) Multiplications: 210 (24.22% of Floating point stage inst.) Divisions: 105 (12.11 % of Floating point stage inst.)