11290 Slajd25 (145)

SE RIAL PE RIPH ERALINTE RFACE - SPI

♦    SCK— PortB. Bit?

SCK: Master Clock output, Slave Clock input pin for SPI chaiinel. Wlien the SPI is enabled as a Slave, this pin is configured as an input regardless ofthe setting of DDB?. Wlien the SPI is enabled as a Master, the data direction of this pin is controlled by DDE?. Wlien the pin is forced by the SPIto be an input, the pull-up can still be controlled by the PORTE? bit.

♦    MISO - Port B. Bit 6

MISO: Master Data input, Slave Data output pin for SPI channel. Wlien the SPI is enabled as a Master, this pin is configured as an input regardless ofthe setting of I)DE6. Wlien the SPI is enabled as a Slave, the data direction ofthis pin is controlled by I)DE6. Wlien the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB6 bit.

♦    MO SI - Port B, Bit 3

MOSI: SPI Master Data output, Slave Data input for SPI channel. Wlien the SPI is enabled as a Slave, this pin is configured as an input regardless ofthe setting of DDB5. Wlien the SPI is enabled as a Master, the data direction of this pin is controlled by DDB5. Wlien the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB5 bit.